Abstract: An apparatus and method for efficient microcode patching.

Abstract: Infection by viruses and rootkits from data memory devices, data messages and data operations are rendered impossible by construction for the Simultaneous Multi-Processor (SiMulPro) cores, core modules, Programmable Execution Modules (PEM), PEM Arrays, STAR messaging protocol implementations, integrated circuits (referred to as chips herein), and systems composed of these components. Greatly improved energy efficiency is disclosed. A system implementation of an Application Specific Integrated Circuit (ASIC) communicating with a DRAM controller interacting with a DRAM array is presented with this resistance to virus and rootkit infection, and simultaneously capable of 1 Teraflop (Tflop) FP16, 1 TFlop FP32 and 1 Tflop FP64 performance while accessing 1 Tbyte of DRAM with a power budget comparable to today's desktop or notebook computers accessing 8 Gbytes of DRAM.

Abstract: Provided is a method of operating a semiconductor device. A method of operating a semiconductor device includes storing secure data in a secure area of a memory in response to detecting a system failure; encrypting the secure data stored in the secure area by using a random key to generate encrypted secure data; storing the encrypted secure data in the secure area; and dumping the secure area and a non-secure area of the memory.

Abstract: Configurable architectural placement control. A control is provided that specifies a location in memory at which one or more in-memory configuration state registers are stored. The control is used to access an in-memory configuration state register of the one or more in-memory configuration state registers. The control may be a configuration state register in which a base address specifying the location in memory is included.

Abstract: Address translation of a base address prior to receiving a storage reference to use the address. A determination is made that an address has been obtained that is to be used as a base address for a memory location at which one or more in-memory configuration state registers are stored. Based on the determining, the address is translated into another address, and the translating is performed prior to receiving a storage reference to use the base address.

Abstract: Grouping of memory-based configuration state registers based on execution environment. A first set of configuration state registers is assigned to one memory region corresponding to a first execution environment, and a second set of configuration state registers is assigned to another memory region corresponding to a second execution environment. The first set of configuration state registers is separate from the second set of configuration state registers.

Abstract: Infection by viruses and rootkits from data memory devices, data messages and data operations are rendered impossible by construction for the Simultaneous Multi-Processor (SiMulPro) cores, core modules, Programmable Execution Modules (PEM), PEM Arrays, STAR messaging protocol implementations, integrated circuits (referred to as chips herein), and systems composed of these components. Greatly improved energy efficiency is disclosed. A system implementation of an Application Specific Integrated Circuit (ASIC) communicating with a DRAM controller interacting with a DRAM array is presented with this resistance to virus and rootkit infection, and simultaneously capable of 1 Teraflop (Tflop) FP16, 1 TFlop FP32 and 1Tflop FP64 performance while accessing 1 Tbyte of DRAM with a power budget comparable to today's desktop or notebook computers accessing 8 Gbytes of DRAM.

Abstract: Disclosed is a method of managing a memory of an electronic device, including: dividing a physical memory into one or more regions including consecutive pages; when there is a memory allocation request of a process or an operating system, allocating a physical memory space to a region including a free page; and configuring a domain by collecting one or more regions having the same characteristic among the regions, to which the memory is allocated.

Abstract: In order to enable dynamic scaling of network services at the edge, novel systems and methods are provided to enable addition of add new nodes or removal of existing nodes while retaining the affinity of the flows through the stateful services. The methods provide a cluster of network nodes that can be dynamically resized to handle and process network traffic that utilizes stateful network services. The existing traffic flows through the edge continue to function during and after the changes to membership of the cluster. All nodes in the cluster operate in active-active mode, i.e., they are receiving and processing traffic flows, thereby maximizing the utilization of the available processing power.

Abstract: A graphics processing unit core 26 includes a plurality of processing pipelines 38, 40, 42, 44. A program instruction of a thread of program instructions being executed by a processing pipeline includes a next-instruction-type field 36 indicating an instruction type of a next program instruction following the current program instruction within the processing thread concerned. This next-instruction-type field is used to control selection of to which processing pipeline the next instruction is issued before that next instruction has been fetched and decoded. The next-instruction-type field may be passed along the processing pipeline as the least significant four bits within a program counter value associated with a current program instruction 32. The next-instruction-type field may also be used to control the forwarding of thread state variables between processing pipelines when a thread migrates between processing pipelines prior to the next program instruction being fetched or decoded.

Abstract: Methods and apparatus to provide virtualized vector processing are disclosed. In one embodiment, a processor includes a decode unit to decode a first instruction into a decoded first instruction and a second instruction into a decoded second instruction, and an execution unit to: execute the decoded first instruction to cause allocation of a first portion of one or more operations corresponding to a virtual vector request to a first processor core, and generation of a first signal corresponding to a second portion of the one or more operations to cause allocation of the second portion to a second processor core, and execute the decoded second instruction to cause a first computational result corresponding to the first portion of the one or more operations and a second computational result corresponding to the second portion of the one or more operations to be aggregated and stored to a memory location.

Abstract: A data processing apparatus comprises processing circuitry arranged to process processing threads using resources accessible to the processing circuitry. A pipeline is provided for handling at least two pending threads awaiting processing by the processing circuitry. The pipeline includes at least one resource-requesting pipeline stage for requesting access to resources for the pending threads. A priority controller controls priority levels of the pending threads. The priority levels define a priority with which pending threads are granted access to resources. When a pending thread reaches a final pipeline stage, if the request resources are not yet available then the priority level of that thread is raised selectively and the thread is returned to a first pipeline stage of the pipeline. If the requested resources are available then the thread is forwarded from the pipeline.

Abstract: An instruction is provided to establish various operational parameters for an adapter. These parameters include adapter interruption parameters, input/output address translation parameters, resetting error indications, setting measurement parameters, and setting an interception control, as examples. The instruction specifies a function information block, which is a program representation of a device table entry used by the adapter, to be used in certain situations in establishing the parameters. A store instruction is also provided that stores the current contents of the function information block.

Abstract: The present invention provides techniques for encapsulating device-level embedded logic into user-defined instructions using configuration software. More specifically, the disclosed embodiments enable add-on instructions for device configuration embedded logic. Programming interfaces specific to an application or device may be combined into a single instruction as a reusable Macro component that may be reused in the same or different applications or devices.

Abstract: A method and circuit arrangement utilize a programmable microcode unit that is capable of being programmed via software to modify the instruction sequences output by the microcode unit in response to microcode instructions issued to the microcode unit. Multiple instruction sequences may be stored in different partitions defined in one or more rewriteable memories such that different instruction sequences may be output for different instances of a microcode instruction executing in different, concurrently-executing instruction streams.

Abstract: A storage system which has flash memories constituting a storage area and a function of placing and handling the flash memories in on-line mode and off-line mode, and which stores and manages management information of the flash memories in on-line mode. The storage system includes: when some or all of flash memory in on-line mode is placed in off-line mode, creating a management area in off-line mode in the flash memories by moving existing data in an area used as the management area to an area other than the management area; writing the management information of the flash memories to the created management area; and placing the flash memories in off-line mode.

Abstract: In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache synchronization, the system controller includes a cache synchronization unit which monitors an address contention between a preceding request and a subsequent request and a setting unit which sets different monitoring range of the contention between the preceding request and the subsequent request for each capacity of the cache memory in each of the CPU units.

Abstract: A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant multithreading mode, whether or not to synchronize an operation of the thread and an operation of the duplicate thread.

Abstract: Generally, the present disclosure provides systems and methods to generate a two-stage commit (TSC) region which has two separate commit stages. Frequently executed code may be identified and combined for the TSC region. Binary optimization operations may be performed on the TSC region to enable the code to run more efficiently by, for example, reordering load and store instructions. In the first stage, load operations in the region may be committed atomically and in the second stage, store operations in the region may be committed atomically.

Abstract: Described is a technology for preloading modules, such as modules that show clinical/medical data maintained at a service, so as to reduce a user's wait time to use a module. The modules for which a user is authenticated are preloaded according to a loading order that is based upon the user's historical usage data. If a user interacts to use a selected module that is not yet loaded, the selected module may be loaded immediately, independent of the order. A background thread preloads the modules according to the order. A normal thread loads the selected module, unless already being preloaded by the background thread; in either situation the loading thread's priority may be temporarily increased to expedite loading. The historical data may be in the form of weight values associated with the modules, with the weight values adjusted based upon module usage.

Abstract: An apparatus for executing fixed width instructions in a multiple execution unit system has a device for fetching instructions from a memory, and a decoder for decoding each fetched instruction in turn. A determination is made as to whether each decoded instruction includes a portion to fetch a locally stored instruction from a local store. If it does, the locally stored instruction is fetched and locally stored portion are executed.

Abstract: A firmware socket module is deployed on a reconfigurable logic device, wherein the firmware socket module is configured to provide both commands and target data to an entry point in a data processing pipeline, wherein each command defines a data processing operation that is to be performed by the data processing pipeline, and wherein the target data corresponds to the data upon which the data processing pipeline performs its commanded data processing operation. Also, the firmware socket module may be configured to (1) access an external input descriptor pool buffer that defines an order in which commands and target data are to be provided to the data processing pipeline, and (2) transfer the commands and target data from an external memory to the data processing pipeline in accordance with the defined order.

Abstract: Described is a technology for preloading modules, such as modules that show clinical/medical data maintained at a service, so as to reduce a user's wait time to use a module. The modules for which a user is authenticated are preloaded according to a loading order that is based upon the user's historical usage data. If a user interacts to use a selected module that is not yet loaded, the selected module may be loaded immediately, independent of the order. A background thread preloads the modules according to the order. A normal thread loads the selected module, unless already being preloaded by the background thread; in either situation the loading thread's priority may be temporarily increased to expedite loading. The historical data may be in the form of weight values associated with the modules, with the weight values adjusted based upon module usage.

Abstract: The present invention provides a method and apparatus for detecting and decoding data. The method comprises: receiving a set of data signals from an external data source; detecting a size of said received set of data signals; decoding said received set of data signals; extracting a destination address from said set of data signals; comparing said destination address extracted from said data signals to a known data value; determining whether said received data signals should be received by a host circuitry based upon said comparison of said destination address extracted from said data signals to a known data value; generating at least one status signal alerting said host circuitry of said determination that said received data signals should be received by said host circuitry; and waking up said host circuitry upon a determination that said received set of data is addressed to said host circuitry.

Abstract: A microprocessor that can perform sequential processing in data array unit includes: a load store unit that loads, when a fetched instruction is a load instruction for data, a data sequence including designated data from a data memory in memory width unit and specifies, based on an analysis result of the instruction, data scheduled to be designated in a load instruction in future; and a data temporary storage unit that stores use-scheduled data as the data specified by the load store unit.

Abstract: An operation apparatus includes a plurality of operation device units; a configuration memory storing setting information provided for each predetermined state of the plurality of operation device units; and a sequencer controlling the plurality of operation device units by outputting transition destination addresses designating relevant information from configuration information comprising the setting information provided for each state of the operation device units stored in the configuration memory, wherein the sequencer carries out operation based on task information previously loaded and a change-over condition signal output from the plurality of operation device units, and generates the transition destination address to output to the configuration memory.

Abstract: A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A multiplexer receives input signals from both the ROM microcode and RAM microcode, and a control signal which is one or more RAM data bits is used to select from the RAM or ROM microcode inputs for further execution by the microprocessor.

Abstract: An improved architectural approach for implementation of a microarchitecture for a low power, small footprint microcoded processor for use in packet switched networks in software defined radio MANeTs. A plurality of on-board CPU caches and a system of virtual memory allows the microprocessor to employ a much larger program size, up to 64k words or more, given the size and power footprint of the microprocessor.

Abstract: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

Abstract: A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault processing unit is external and different with respect to said central processing unit and said further fault processing unit comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller. Validation of operations of said central processing unit is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check.

Abstract: A processor comprises an arithmetic unit for processing operands, a register memory for storing operands with a register memory space and a register memory configuration unit. The register memory configuration unit is designed to configure the register memory such that memory space in the register memory is assigned to operands, and that memory space in the register memory that is not assigned to operands will be made available for other data than the operands. Thereby, on the one hand the number of operand transfers between an external bus and the arithmetic unit is decreased, since as many operands as possible are stored in the register memory, while on the other hand, when part of the register memory is not needed for storage of operands, this part will not be idle but made available for other data, so that the memory resources of the processors are always utilized optimally.

Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.

Abstract: Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory write operations local to a CPU to occur in an arbitrary order, and places constraints on shared memory operation to occur in a specified order. Multiple sets of instructions are provided in which order of execution of the instructions is maintained through the use of CPU registers, write buffers in conjunction with assignment of sequence numbers to the instruction, or a hierarchical ordering system. The system ensures that an earlier designated instruction has reach a specified state of execution prior to a latter instruction reaching a specified state of execution. The ordering of operations allows memory operations local to a CPU to occur in conjunction with other memory operations that are not affected by such execution.

Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debug monitor mechanism.

Abstract: In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a plurality of paths through a mapping array T are being handled by a processor. This sequence of operations, including instructions from the plurality of sets of operations, ensures that there is another operation in the pipeline if a cache miss on any given lookup operation in the mapping array results in a slower main memory access. In this way, the processor utilization is improved. While the sets of operations in the sequence of operations are independent of another other, there will be an overlap of a plurality of the main memory access operations due to the long time required for main memory access.

Abstract: A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set associated therewith. Associated with the second control unit is at least one programming element for rendering the second instruction set selectively modifiable. Also present is at least one circuit element for supplying instruction codes to be executed to the first control unit and to the second control unit, so that each instruction can be executed under the control of at least one between the first control unit or the second control unit according to whether the instruction is comprised in the first basic instruction set and/or in the second selectively modifiable instruction set.

Abstract: An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N?2) waiting data and respective data valid flags in one address; a constant storage that stores constants and a constant valid flag; a constant readout unit that reads out a constant and a constant valid flag from the constant storage with the node number of an input packet as the address; a unit that calculates a hash address and selects a process for data waiting depending upon a combination of a data valid flag, a constant valid flag, and the number of instuction inputs; and a unit that performs a waiting process in response to a select signal.

Abstract: Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for storing microcode instructions; execution circuitry operable to execute microcode instructions from the control store; and means for loading a suite of one or more microcode-device modules defining an optional peripheral device, the optional peripheral device being implemented by microcode instructions executed by the execution circuitry in accordance with the definition provided by the microcode-device modules.

Abstract: A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is halted. The standby mode is exited by input of an interrupt. The microcontroller also has a control circuit that, by storing the next few program instructions internally before placing the memory in standby, or by delaying the interrupt signal, provides extra time for memory operation to stabilize on exit from the standby mode. Malfunctions on recovery from standby are thereby prevented, and the microcontroller can conserve power by placing the memory in a deep standby mode with a comparatively long recovery time.

Abstract: In one embodiment, a method is provided. The method of this embodiment includes generating, by a processor that includes a plurality of processing engines capable of executing program instructions, a packet. The method of this embodiment also includes transmitting the packet to at least one of the processing engines. Additionally, the method of this embodiment also includes, in response, at least in part to receipt of the packet by the at least one of the processing engines, modifying at least in part, by the at least one of the processing engines, a set of program instructions that the at least one processing engine is capable of executing. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: This invention is a method and system for hybrid prediction of load addresses and/or values. The new scheme for value prediction provides prediction based on last values and strides, as well as context prediction, without the use of a sophisticated switching scheme between several predictors. The system collects patterns of deltas of subsequent values instead of the values itself in a first table. Thus, a last value prediction can be achieved by predicting a ‘pattern’ of just one stride equal to zero. A stride predictor uses a pattern of one constant stride. And a certain pattern of values is modeled by recording the pattern of deltas between the values and adding the deltas to the last value. The switching scheme is inherently included in the system itself and operates basically by immediate evaluation of counters in the pattern history table.

Abstract: An apparatus comprising a microcontroller configured to (i) send or receive data over one or more data lines when in a first mode and (ii) be programmed through said data lines when in a second mode.

Abstract: A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath unit. The instruction processing unit further contains a configurable microcode unit and a non-configurable sequencing unit. The programmable integrated circuit can be programmed so that a microcode compatible with a target microprocessor is installed in the configurable microcode unit. The superset datapath unit is a superset of the datapath elements of all the target microprocessors.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Abstract: Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select a particular portion of an associated register file to be accessed by the corresponding processor thread. In an illustrative embodiment, the register file is divided into even and odd portions, with a least significant bit or other portion of the thread identifier being used to select either the even or the odd portion for use by a given processor thread. The thread-based register file selection may be utilized in conjunction with token triggered threading and instruction pipelining. Advantageously, the invention reduces register file port requirements and thus processor power consumption, while maintaining desired levels of concurrency.

Abstract: Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes) singly or in groups in accordance with one or more execution bits set during post-processing in opcodes preceding opcodes to be skipped. Thus portions of an application program which consume excessive power or are unsupported in particular operating environments can be easily and selectively de-activate while maintaining the integrity of the applications program. Local or cache memory is also effectively expanded and processor performance improved by eliminating opcodes from local or cache memory which will not be called.

Abstract: Methods for optimizing of memory resources during an initialization routine of a computer system which prepares the computer system for loading of an operating system is disclosed. One exemplary method includes receiving a request from a system BIOS to locate an amount of conventional memory where the amount of conventional memory accommodates at least a decompressed version of data located in an option ROM BIOS. Then the amount of conventional memory requested by the system BIOS is determined. If the amount of conventional memory requested by the system BIOS is not available, the method continues and system BIOS data located within the conventional memory is read where the system BIOS data occupies at least the amount of conventional memory requested by the system BIOS. After the system BIOS data is read, the system BIOS data is written from the conventional memory to an extended memory, and the system BIOS data located in the conventional memory that has been written into the extended memory is deleted.

Abstract: A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an instruction set. From the first output signal, the dependencies between currently fetched instructions of the instruction set and previous in-flight instructions can be determined and used to generate a dependency matrix for all in-flight instructions. From the second output signal, the physical register addresses of the data required to execute an instruction, once the dependencies have been removed, may be determined.

Abstract: A pipelined, simultaneous and redundantly threaded (“SRT”) processor comprising, among other components, load/store units configured to perform load and store operations to or from data locations such as a data cache and data registers and a cycle counter configured to keep a running count of processor clock cycles. The processor is configured to detect transient faults during program execution by executing instructions in at least two redundant copies of a program thread and wherein false errors caused by incorrectly replicating cycle count values in the redundant program threads are avoided by implementing a cycle count queue for storing the actual values fetched by read cycle count instructions in the first program thread. The load/store units then access the cycle count queue and not the cycle counter to fetch cycle count values in response to read cycle count instructions in the second program thread.

Abstract: Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by associating with each of the threads at least one register which stores a value identifying a next thread to be permitted to issue one or more instructions, and utilizing the stored value to control the instruction issuance sequence. For example, each of a plurality of hardware thread units of the multithreaded processor may include a corresponding local register updatable by that hardware thread unit, with the local register for a given one of the hardware thread units storing a value identifying the next thread to be permitted to issue one or more instructions after the given hardware thread unit has issued one or more instructions. A global register arrangement may also or alternatively be used.