Abstract: A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

Abstract: Systems and/or methods can include techniques to exploit dynamic timing slack on the chip. By using a special clock generator, the clock period can be shrunk as needed at every cycle. The clock period is determined during operation by checking “critical path messengers” to indicate how much dynamic timing slack exists. Elastic pipeline timing can also be introduced to redistribute timing among pipeline stages to bring further benefits.

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

Abstract: A controller configured to perform a training process of sampling data using multi-phase signals which are internally generated according to a data strobe signal, and compensating for a delay time of the data strobe signal using a control code which is generated according to the sampling result.

Abstract: A memory device includes a plurality of input/output (I/O) nodes, a circuit, a latch, a memory, and control logic. The plurality of I/O nodes receive a predefined data pattern. The circuit adjusts a delay for each I/O node as the predefined data pattern is received. The latch latches the data received on each I/O node. The memory stores the latched data. The control logic compares the stored latched data to an expected data pattern and sets the delay for each I/O node based on the comparison.

Abstract: A memory system in which a timing drift that would occur in distribution of a first timing signal for data transport in a memory device is determined by measuring the actual phase delays occurring in a second timing signal that has a frequency lower than that of the first timing signal and is distributed in one or more circuits mimicking the drift characteristics of at least a portion of distribution of the first timing signal. The actual phase delays are determined in the memory device and provided to a memory controller so that the phases of the timing signals used for data transport may be adjusted based on the determined timing drift.

Abstract: A phase calibration method includes sweeping phase codes applicable to a serial clock signal, identifying a first, a second, a third, and a fourth phase code, wherein the first phase code causes zero plus a first threshold number of bits extracted from the serial data signal to be a particular value, wherein the second phase code causes all minus a second threshold number of bits extracted from the serial data signal to be the particular value, wherein the third phase code causes all minus a third threshold number of bits extracted from the serial data signal to be the particular value, wherein the fourth phase code causes zero plus a fourth threshold number of bits extracted from the serial data signal to be the particular value, determining an average phase code based on the identified phase codes.

Abstract: The present disclosure includes apparatuses and methods for providing indications associated with power management events. An example apparatus may include a plurality of memory units coupled to a shared power management signal. In this example apparatus, each of the plurality of memory units may be configured to provide to the other of the plurality of memory units, via the shared power management signal, an indication of whether the one of the plurality of memory units is entering a power management event. Further, each of the plurality of memory units may be configured to, if the one of the plurality of memory units is entering the power management event, an indication of a particular operation type associated with the power management event.

Abstract: A chip transferring method includes providing a plurality of chips on a first load-bearing structure; measuring a photoelectric characteristic value of each of the plurality of chips; categorizing the plurality of chips into a first portion chips and a second portion chips according to the photoelectric characteristic value of each of the plurality of chips; providing a second load-bearing structure; weakening a first adhesion between the first portion chips and the first load-bearing structure or between the second portion chips and the first load-bearing structure; and transferring the first portion chips or the second portion chips to the second load-bearing structure.

Abstract: A circuit receives an input signal having a first level and a second level. A logic circuit includes a finite state machine circuit, an edge detector circuit, and a timer circuit. The finite state machine circuit is configured to set a mode of operation of the circuit. The edge detector circuit is configured to detect a transition between the first and second level. The timer circuit is configured to determine whether the first or second level is maintained over an interval, which starts from a transition detected by the edge detector circuit. The finite state machine circuit is configured to change the mode of operation based on the timer circuit determining that the first or second level has been maintained over the interval.

Abstract: A system comprises a plurality of computing devices that are communicatively coupled via a network and have a file system distributed among them, and comprises one or more file system request buffers residing on one or more of the plurality of computing devices. File system choking management circuitry that resides on one or more of the plurality of computing devices is operable to separately control: a first rate at which a first type of file system requests (e.g., one of data requests, data read requests, data write requests, metadata requests, metadata read requests, and metadata write requests) are fetched from the one or more buffers, and a second rate at which a second type of file system requests (e.g., another of data requests, data read requests, data write requests, metadata requests, metadata read requests, and metadata write requests) are fetched from the one or more buffers.

Abstract: An embodiment method is disclosed for deriving an estimation value of a clock-error for a slave clock, wherein the slave clock is set at a nominal slave period and outputs a sequence of slave clock signals at an actual slave period, and wherein a difference between the actual slave period and the nominal slave period is approximated by the estimation value of the clock-error.

Abstract: A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

Abstract: A system includes a plurality of oscilloscopes, each oscilloscope having an output port and an input port, a cable connecting the output port of an initial oscilloscope of the plurality of oscilloscopes to the input port of a second oscilloscope of the plurality of oscilloscopes, the initial oscilloscope having a processing element to generate a master run clock, the second oscilloscope having a processing element including a phase-locked loop to lock a slave run clock to the master run clock, wherein the processing element of one of the oscilloscopes executes code to cause the processing element to manipulate one of the run clocks to pass trigger information to another of the plurality of oscilloscopes.

Abstract: Optical apparatus (20) includes a transparent envelope (26) configured to be mounted in a spectacle frame. An electro-optical layer (46) is contained within the envelope, with an array of transparent excitation electrodes (50) disposed over a first surface of the transparent envelope. A transparent common electrode (52) is disposed over a second surface of the transparent envelope, opposite the first surface, and is electrically separated into a central region defining an active area (24) of the electro-optical layer and a peripheral region, which at least partially surrounds the central region. Control circuitry (72, 82, 92) holds the central region of the transparent common electrode at a predefined common voltage while allowing the peripheral region to float electrically, and to apply control voltage waveforms to the excitation electrodes, relative to the common voltage, so as to generate a specified phase modulation profile in the active area of the electro-optical layer.

Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.

Abstract: According to one embodiment, a transmission terminal, a time information processing device, and a synchronization method capable of improving synchronization accuracy in a wireless network are provided. According to an embodiment, a sensor system includes a sensor, a transmission terminal, and a time information processing device. The transmission terminal includes an event signal generator, an event time determiner, a communication time determiner, and a communicator. The event signal generator detects the occurrence of an event on the basis of a physical quantity detected by the sensor. The event time determiner determines a detection time of the event. The communication time determiner determines a transmission time at the time of transmission to the time information processing device. The communicator transmits time information to the time information processing device. The time information processing device includes a reception time determiner and a time information processor.

Abstract: Proactively performing tasks based on estimating hardware reconfiguration times. A determination is made, prior to performing one or more reconfiguration actions to reconfigure a configuration of the computing environment, at least one estimated reconfiguration time to perform the one or more reconfiguration actions. At least one reconfiguration action of the one or more reconfiguration actions is performed, and one or more tasks are initiated prior to completing the one or more reconfiguration actions. The initiating is based on the at least one estimated reconfiguration time.

Abstract: A memory system containing: a nonvolatile memory device including a plurality of memory dies that each perform a plurality of command operations, and a controller configured to: store, in a preset internal space, profile information for changes in power consumption for each of a operation sections included in each of the command operations, check, from the profile information, the changes in power consumption for each operation section of a first and second command when sequentially propagating the first and second command to the memory dies, calculate, based on the checked changes in power consumption for each operation section, a maximum length of an overlap operation section between the first and second command in which peak power is maintained at or below a first reference power, and adjust, a difference between time points for performing the first and second command based on the calculated maximum length of the overlap operation section.

Abstract: An apparatus is described which includes a delay-line with reasonably matched delay cells and some logic to ascertain both a correct number of DC-DC converters and interleaving angles or phase offsets. The apparatus measures an operating frequency in real-time in multiples of the individual delay cells of the delay-line. The smaller the period, the higher the load coupled to the DC-DC converters and, therefore the greater the number of DC-DC converters are needed to service the load. The period determines the load and can be used to determine the number of DC-DC converters needed and thereby accomplishing autonomous phase enabling/shedding.

Abstract: A transferring chips method, including providing a plurality of chips on a first load-bearing structure; dividing the first load-bearing structure into a plurality of blocks, and each of the plurality of blocks including multiple chips of the plurality of chips; measuring a characteristic value of each of the plurality of chips; respectively calculating an average characteristic value of each of the plurality of blocks based on the characteristic values of the multiple chips of each of the plurality of blocks; and transferring the multiple chips of at least two blocks of the plurality of blocks with the average characteristic values within the same range to a second load-bearing structure.

Abstract: A computer device may include a memory configured to store instructions and a processor configured to execute the instructions to select a communication session associated with a wireless communication device; determine a service requirement for the selected communication session; determine an end-to-end latency for the selected communication session; and compute a repeat requests adjustment based on the determined service requirement and the determined end-to-end latency. The processor may be further configured to instruct a base station device associated with the communication session to adjust the maximum number of repeat requests transmissions based on the determined repeat requests adjustment.

Abstract: A memory interface circuit, a memory storage device and a configuration status checking method are provided. The memory interface circuit is configured to connect a plurality of volatile memory modules and a memory controller. The volatile memory modules include a first volatile memory module and a second volatile memory module. The memory interface circuit includes a first interface circuit and a second interface circuit. The first interface circuit is configured to receive a first signal from the first volatile memory module and transmit a second signal to the second interface circuit through an internal path of the memory interface circuit. The second interface circuit is configured to transmit a third signal to the second volatile memory module according to the second signal to evaluate a configuration status of the memory interface circuit by the third signal.

Abstract: A system includes a plurality of oscilloscopes, each oscilloscope having an output port and an input port, a cable connecting the output port of an initial oscilloscope of the plurality of oscilloscopes to the input port of a second oscilloscope of the plurality of oscilloscopes, the initial oscilloscope having a processing element to generate a master run clock, the second oscilloscope having a processing element including a phase-locked loop to lock a slave run clock to the master run clock, wherein the processing element of one of the oscilloscopes executes code to cause the processing element to manipulate one of the run clocks to pass trigger information to another of the plurality of oscilloscopes.

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

Abstract: A method and apparatus for performing memory calibration with endpoint replay is disclosed. A first calibration of a data strobe signal in a memory subsystem is performed. The first calibration includes determining initial values of first and second endpoints indicative of first and second delay values, respectively, applied to the data strobe signal. A second calibration of the data strobe signal is performed around these endpoints, within a range thereof that is less than a full range there between. Based on the second calibration, the endpoints are adjusted.

Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.

Abstract: A sequential circuit with timing event detection is disclosed. The sequential circuit has an input that is asserted to the output during the second clock phase of a two phase clock signal. A timing event detector is coupled to the sequential element input to assert a timing event signal if a transition occurs at the sequential element input during the second clock phase but not to assert during the first clock phase.

Abstract: A method for transmitting time-synchronized data from a controller of an automation system comprising a local time to at least one subscriber of the automation system, wherein the automation system comprises a server having a reference time.

Abstract: Devices, methods and systems are disclosed relating to RF signals. A device may comprise a clock input terminal, a variable delay circuit coupled to the clock input terminal and a test terminal as well as a reference signal generator coupled to the variable delay circuit.

Abstract: A processor includes a front end including circuitry to decode an instruction from an instruction stream and a core including circuitry to process the instruction. The core includes an execution pipeline, a dynamic core frequency logic unit, and a counter compensation logic unit. The execution pipeline includes circuitry to execute the instruction. The dynamic core frequency logic unit includes circuitry to squash a clock of the core to reduce a core frequency. The clock may not be visible to software. The counter compensation logic unit includes circuitry to adjust a performance counter increment associated with a performance counter based on at least the dynamic core frequency logic unit circuitry to squash a clock of the core to reduce a core frequency.

Abstract: A clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay.

Abstract: Disclosed is a clock recovery system of a display apparatus including a clock recovery unit which uses changeable option information used for recovering a clock signal and defining a duty, generates delayed clock signals having the duty corresponding to the option information in a clock training section, and outputs one of the delayed clock signals as the clock signal.

Abstract: A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.

Abstract: A memory interface includes a first output circuit to be connected to the memory device for communication therewith, a first input circuit to be connected to the memory device for communication therewith, a first write circuit configured to process write data, a read circuit configured to process read data and a read strobe, a first delay adjustment circuit, a first switching circuit which is connected in a signal path between the first write circuit and the first delay adjustment circuit, and in a signal path between the first input circuit and the first delay adjustment circuit, and a second switching circuit which is connected in a signal path between the first delay adjustment circuit and the first output circuit, and in a signal path between the first delay adjustment circuit and the read circuit.

Abstract: A dynamic random access memory (DRAM) includes a delay lock loop (DLL), a clock tree, an off-chip driver (OCD), a phase detector (PD) and a filter. The DLL receives a reference clock and updates a delay line, and then outputs a calibrated clock via the clock tree; the PD receives the calibrated clock via the clock tree and detects a phase difference between the calibrated clock and the reference clock; and the filter activates the DLL to update the delay line according the phase difference, wherein when a READ command is received, the filter increases the number of activations for the DLL to update the delay line, thereby shortening the access time of the DRAM.

Abstract: Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal are disclosed. An example apparatus includes a clock path configured to receive a clock signal and provide internal clock signals and a command path configured to receive a command and propagate the command through the command path responsive to the internal clock signals and provide an internal command having a timing that reflects a timing of the clock signal. The example apparatus further includes a data clock path configured to receive a data clock signal and provide multiphase clock signals based on the data clock signal and provide a delayed multiphase clock signal, and further includes a clock synchronization circuit configured to receive the delayed multiphase clock signal and latch a logic level of the delayed multiphase clock signal responsive to the internal command.

Abstract: An information processing apparatus includes a DRAM, a nonvolatile memory, and nonvolatile storage. A process execution unit executes, in response to a write instruction, a first writing process of writing write data to the DRAM and storing a write log of the write data in the nonvolatile storage or a second writing process of writing the write data to the nonvolatile memory. A page management unit moves, based on the number of times predetermined data stored in the DRAM or the nonvolatile memory is written or read in a predetermined time period, the processing speed of each of the DRAM and the nonvolatile memory, and the time needed to store the log in the nonvolatile storage executed by the process execution unit, the predetermined data between the DRAM and the nonvolatile memory.

Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.

Abstract: Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.

Abstract: An apparatus includes a processor and a memory configured to store design data used for disposition and wiring of a logic circuit on a programmable logic device, and store a table indicating a relationship between a power supply voltage value and a delay amount for each type of element in the logic circuit, the relationship having a nature to set the delay amount so as to increase in value as the power supply voltage value is smaller. The processor determines, as an optimum voltage value, a power supply voltage value at which the delay margin of a critical path indicates a desired value that is in the positive and is a minimum value. The processor outputs configuration information including the optimum voltage value and the design data so as to form the logic circuit on the programmable logic device supplied with a voltage determined by the optimum voltage value.

Abstract: Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

Abstract: A synchronization solution is described, which, in one aspect, allowed finer grained segmentation of clock domains on a chip. This solution incorporates computation into the synchronization overhead time and is called Gradual Synchronization. With Gradual Synchronization as a synchronization method, the design space of a chip could easily mix both asynchronous and synchronous blocks of logic, paving the way for wider use of asynchronous logic design.

Abstract: A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first phase clock signal and the second phase clock signal exhibiting non-overlapping logical high states; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to cause a difference between a first duration and a second duration within a clock cycle to be less than a predetermined tolerance.

Abstract: A measurement arrangement and method for providing at least one combined measurement dataset, said measurement arrangement comprising at least one measurement device configured to generate measurement data in a measurement session, and a mobile device configured to generate measurement session context data of said measurement session, said measurement device and said mobile device being connected via at least one wireless link for data transfer, wherein the measurement data generated by said measurement device and associated measurement session context data generated by said mobile device are linked to provide a combined measurement dataset.

Abstract: According to one embodiment, in a semiconductor integrated circuit of a DLL circuit, in a delay chain, a plurality of delay elements are connected. A first detection circuit detects a group corresponding to a certain delay amount among a plurality of groups obtained by dividing the delay chain. A second detection circuit detects a delay element corresponding to the certain delay amount among a plurality of delay elements included in the detected group. The semiconductor integrated circuit detects the number of delay elements corresponding to one cycle of a first clock. The control circuit includes a second delay chain. The second delay chain has a configuration equivalent to the delay chain in the semiconductor integrated circuit. The control circuit outputs a second clock obtained by delaying the first clock by using the second delay chain according to the number of delay elements detected by the semiconductor integrated circuit.

Abstract: Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-gm biasing to provide substantial immunity to process, temperature and voltage variations, for example.

Abstract: Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application and a framework model representing a software framework using which the software application is developed; and the application architecture model comprises a plurality of component models. One or more component models may be selected, based on a property to be checked, from the plurality of component models. The one or more component models may be analyzed to determine if the property is satisfied.

Abstract: Systems and methods for software verification. In some embodiments, an application architecture model is generated for a software application, wherein: the application architecture model is generated based on source code of the software application; and the application architecture model comprises a plurality of component models. A property model type may be selected, based on a property to be checked, from a plurality of property model types. One or more component models may be selected, based on the selected property model type, from the plurality of component models. The one or more selected component models may be used to construct at least one property model of the selected property model type. The at least one property model may be analyzed to determine if the property is satisfied with respect to the at least one property model.

Abstract: A circuit for measuring latency in an integrated circuit device is described. The circuit comprises a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a unit interval (UI) adjustment circuit; wherein the latency calculation circuit generates a latency value (LATENCY) based upon a latency count from the latency adjustment circuit and a UI adjustment from the UI adjustment circuit.