Abstract: A combined data/power coupling device includes a chassis having first and second powering device connectors and a powered device connector each coupled to a data/power coupling subsystem. The data/power coupling subsystem configures each of the first and second powering device connectors to receive power from at least one powering device, configures the first powering device connector to receive data from the at least one powering device, and provides data and power received via the first powering device connector to a powered device via the powered device connector. When the data/power coupling subsystem determines that data and power are not available via the first powering device connector, it configures the second powering device connector to receive data from the at least one powering device, and provides data and power received via the second powering device connector to the powered device via the powered device connector.

Abstract: A memory includes: a data receiving circuit suitable for receiving a data during a write operation; a data rotation circuit suitable for changing an order of the data transferred from the data receiving circuit and outputting the data whose order is changed in response to an address during the write operation; an error correction code generation circuit suitable for generating an error correction code based on the data output from the data rotation circuit during the write operation; and a memory core suitable for storing the data received by the data receiving circuit and the error correction code during the write operation.

Abstract: The disclosure provides a network equipment power supply and a heat dissipation system therefor. The heat dissipation system includes a liquid-cooling heat dissipation device and an air-cooling heat dissipation device. The liquid-cooling heat dissipation device includes a liquid inlet, a liquid outlet, and a liquid-cooling pipe between them, wherein liquid-cooling medium flows inside the liquid-cooling pipe and takes away heat generated by components arranged around the liquid-cooling pipe; The air-cooling heat dissipation device includes an air inlet, an air outlet, and an air-cooling channel between them, wherein airflow passes through the air-cooling channel and takes away heat generated by components arranged around the air-cooling channel.

Abstract: Provided are embodiments for performing encryption and decryption. Embodiments include generating a random key address, obtaining a pre-stored key using the random key address, and re-arranging portions of the pre-stored key using the random key address and a first enable signal. Embodiments also include selecting a dynamic logic operation based on the random key address and a second enable signal, receiving data for encryption, and combining portions of the received data for encryption with the re-arranged portions of the pre-stored key using the dynamic logic operation to produce encrypted data. Embodiments include re-arranging portions of the encrypted data based on the random key address and a third enable signal, and combining the re-arranged portions of the encrypted data with the random key address into an encrypted data packet for transmission. Also provided are embodiments for a transmitter and receiver for performing the encryption and decryption.

Abstract: Provided are embodiments for performing encryption and decryption in accordance with one or more embodiments. The embodiments include generating a random key address, obtaining a pre-stored key using the random key address, and re-arranging portions of the pre-stored key using the random key address. Embodiments also include selecting a dynamic logic operation based on the random key address, receiving data for encryption, and combining portions of the received data for encryption with the re-arranged portions of the pre-stored key using the dynamic logic operation to produce encrypted data. Embodiments include re-arranging portions of the encrypted data based on the random key address and combining the re-arranged portions of the encrypted data with the random key address into an encrypted data packet for transmission. Also provided are embodiments for a transmitter and receiver for performing the encryption and decryption.

Abstract: An image forming system includes a first image forming apparatus and a second image forming apparatus connected with the first image forming apparatus by a network line. When a second stacking portion of the second image forming apparatus is associated with a first stacking portion of the first image forming apparatus by a setting portion, an arithmetic portion acquires information related to the characteristic of a second recording medium stacked by the second stacking portion via the network line and obtains a degree of deterioration of a feeding rotatable member of the first image forming apparatus based on the acquired information related to the characteristic of the second recording medium.

Abstract: Disclosed herein is a battery charger for electric vehicle includes a motor configured to generate power for driving the electric vehicle, an inverter configured to provide the power to the motor, an AC power input terminal configured to be input at least one AC power of single phase AC power and polyphaser AC power from a slow charger, a power factor corrector configured to include a plurality of full bridge circuits through which the AC power is input through the AC power input terminal, a link capacitor configured to connect in parallel with the power factor corrector, a switch network configured to include a first switch SW A provided to connect any one of a plurality of AC power input lines and a neutral line constituting the AC power input terminal with the power factor corrector, and a second switch provided to transfer one of a direct current power input from a quick charger and an alternating current power input from a slow charger to a high voltage battery and a controller configured to control the

Abstract: A method is provided for calibrating a test system, including an RF source combined with a VNA connected to or embedded in a test instrument. The method includes connecting to a power meter at the test port; generating an RF signal at an RF source as an incident signal, and providing the incident signal to the power meter through the test port; measuring a forward power wave of the incident signal using a first receiver; measuring a reverse power wave of a reflected signal using a second receiver; measuring output power at the test port using the power meter; and calculating magnitude errors of the first receiver and the second receiver using the measured forward power wave, the measured reverse power wave, and the measured output power by the power meter, and determining magnitude error correction terms of the forward and reverse power waves to remove the magnitude errors.

Abstract: This invention introduces an electronic apparatus and an operative method thereof which are capable of triggering an initialization operation for the electronic apparatus correctly. The electronic apparatus includes a plurality of latches and a power power-on-reset generator. The plurality of latches are coupled to memory cells and are configured to monitor memory data of the memory cells. The power-on-reset generator is coupled to the plurality of latches and is configured to generate a power-on-reset pulse to reset the electronic apparatus in response to a data corruption on at least one of the memory cells. The data corruption is detected during an initialization operation of the electronic apparatus according to memory data of the memory cells and corresponding hardwired code data.

Abstract: An embodiment of a semiconductor package apparatus may include technology to store cache line spare information in a first memory, detect a first power state change for the first memory, and save the cache line spare information to a second memory based on the detected first power state change. Other embodiments are disclosed and claimed.

Abstract: A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes a sense amplifier and associated circuitry configured to detect a first threshold representative of a first external voltage ramping down during a power off of the memory device, and one or more switches triggered via the sense amplifier and associated circuitry to provide for a power off sequence for the memory bank based on using a second external voltage ramping down during the power off of the memory device.

Abstract: The present disclosure provides a functional safety module for industrial devices, the functional safety module being connected between the industrial devices to manage safety according to a state of the industrial devices. The functional safety module may include a first controller and a second controller each configured to execute a common predetermined operation command including operation commands. The first controller is configured to output digital signals, and sequentially convert the digital signals into analog voltages. The second controller is configured to receive the analog voltages, sequentially converts the analog voltages, and outputs the digital signals, and determine whether the first controller is normal.

Abstract: Methods and systems are disclosed for protecting a host device from one or more power surges transmitted from a sink device. When a sink device is detected as being connected to the host device, a limited level of power is provided to the sink device over a power transmission line and the sink device is authenticated. A normal level of power is provided to the sink device only if the authentication is successful, otherwise a reduced level of power is provided.

Abstract: An information handling system has power supply units (PSUs), each of which includes an input over current warning (OCW) setting that provides a reference for an amount of an input current drawn by a corresponding workload. Each of the PSUs sends an interrupt to a baseboard management controller (BMC) when the amount of the input current drawn by the corresponding workload exceeds the corresponding configured input OCW setting. In response to the received interrupt, the BMC requests an adjustment to the corresponding workload.

Abstract: A computing system having a power loss detector and memory components to store data associated with write commands received from a host system. The write commands are flushed from a protected write queue of the host system responsive to detecting an impending loss of power. The computing system further includes a processing device to receive the write commands over a memory interface. The processing device is further to, responsive to detecting the loss of power by the detector: disable the memory interface, and store the data associated with write commands that are received prior to disabling the memory interface. The data is stored in one or more of the memory components using power supplied by one or more capacitors.

Abstract: A memory device failure recovery system includes a memory device management engine that is coupled to a first memory device via a first memory device slot, and a memory device management database. The memory device management engine identifies that the first memory device has experienced a failure in a configuration region of the first memory device during a current boot operation and, in response, retrieves memory device component information and memory device configuration information that is stored in the memory device management database and that was retrieved as part of a prior boot operation from a memory device that was connected to the first memory device slot. During the current boot operation, the memory device management engine determines whether first memory device components on the first memory device correspond to the memory device component information and, if so, uses the memory device configuration information to configure the first memory device.

Abstract: Techniques are directed to failure recovery of a storage system. In accordance with certain techniques, in response to detecting that a disk group of a memory system failed, failure duration of the disk group is recorded. If the failure duration does not reach a predetermined ready time limit and the disk group is in a degraded state, the disk group is maintained in a degraded but not ready state. The predetermined ready time limit is shorter than a logic unit number debounce time limit to avoid a data unavailable event. With such techniques, the possibility of occurrence of a data loss event may be reduced significantly while avoiding a data unavailable event.

Abstract: A circuit assembly for monitoring the timing behavior of a microcontroller, including: a microcontroller to drive at least one watchdog voltage generating section for a temporally defined generation of at least one monitoring voltage and to detect and read in the generated monitoring voltage at a predetermined sampling point in time; in which the at least one watchdog voltage generating section is arranged to generate the monitoring voltage that is detectable at a predetermined sampling point in time by sampling by the microcontroller, in which a monitoring voltage that is detected at the sampling point in time and lies within a predetermined voltage tolerance range indicates a fault-free microcontroller state, and a monitoring voltage that is detected at the predetermined point in time and lies outside the predetermined voltage tolerance range indicates a faulty microcontroller state. Also described is a related method.

Abstract: A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.

Abstract: A storage apparatus includes, a determination circuit that determines a path between one of a plurality of backup power sources and one of a plurality of backup target circuits each of the plurality of backup power sources including a memory based on configuration information, state information of the storage apparatus, and setting information of performance request for the storage apparatus, a plurality of switches arranged between the plurality of backup target circuits and the plurality of backup power sources, and a control circuit that controls the switches to couple the backup target circuit to the backup power source via the path determined by the determination circuit.

Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a volatile second memory, a capacitor, and a memory controller. The nonvolatile first memory includes a storage region that includes a plurality of memory cells. The capacitor is configured to accumulate electric power. The memory controller writes first data stored in the volatile second memory to the storage region in a first mode, using a power supply from outside. The first mode is a mode in which one-bit data is written to each of the memory cells. The memory controller writes, upon stop of the power supply from the outside, the first data to the storage region in a second mode, using the electric power accumulated in the capacitor. The second mode is a mode in which one-bit data is written to each of the memory cells and is different from the first mode.

Abstract: The disclosed method may include (1) monitoring, while a computing device receives power from an external power supply, (A) the amount of power consumed by the computing device and (B) the amount of power provided to the computing device by the external power supply, (2) detecting that the amount of power provided to the computing device exceeds the amount of power consumed by the computing device by at least a certain threshold, (3) determining, based on the amount of power provided to the computing device exceeding the amount of power consumed by the computing device by the certain threshold, that the computing device is experiencing a malfunction, and then (4) mitigating potential damage to the computing device due to the malfunction by at least partially reducing the amount of power provided to the computing device from the external power supply. Various other apparatuses, systems, and methods are disclosed.

Abstract: An apparatus is provided comprising a system including one or more electronic components; a power input unit arranged to supply power to the system; and a power management module configured to: detect whether the system is in an abnormal state, and in response to detecting that the system is in the abnormal state, adjust at least one of (i) power supplied from a battery to the system, (ii) the power supplied from the power input unit to the system, and (iii) power supplied from the power input unit to the battery.

Abstract: Recovery of an in-memory state in a log-structured filesystem using fuzzy checkpoints is disclosed, including: determining a portion of a data structure to checkpoint to a storage unit, wherein the structure is associated with a set of references to locations in persistent storage at which metadata is stored, wherein the portion of the data structure is dynamically determined based at least in part on a size of the data structure and a predetermined number of storage units to be associated with a checkpoint window, wherein the number of storage units to be associated with the checkpoint window is fewer than a total number of storage units associated with the persistent storage; and checkpointing the portion of the data structure to the storage unit.

Abstract: In an embodiment of the invention, a method comprises: recording application-level heuristics and IO-level (input/output-level) heuristics; correlating and analyzing the application-level heuristics and IO-level heuristics; and based on an analysis and correlation of the application-level heuristics and IO-level heuristics, generating a policy for achieving optimal application performance. In another embodiment of the invention, an apparatus comprises: a system configured to record application-level heuristics and IO-level heuristics, to correlate and analyze the application-level heuristics and IO-level heuristics, and based on an analysis and correlation of the application-level heuristics and IO-level heuristics, to generate a policy for achieving optimal application performance.

Abstract: A computer device includes a microprocessor, a voltage converter circuit converting a first voltage of a system power into a second voltage, a control circuit controlling supply of the second voltage and a detection circuit detecting whether power abnormality at the peripheral device has occurred. When confirming that the system power is being supplied normally, the microprocessor generates a first enable signal to enable the voltage converter circuit. When confirming that the voltage converter circuit functions normally, the microprocessor generates a second enable signal to enable the detection circuit. The detection circuit generates a first detection signal according to detection result for the microprocessor to determine whether to supply the second voltage to the peripheral device. When the first detection signal indicates that power abnormality has not occurred, the microprocessor generates a third enable signal to enable the control circuit to supply the second voltage to the peripheral device.

Abstract: A computer device includes a power supply unit which includes an instantaneous power failure resistance capacitor and converts an alternating current into a direct current and outputs the direct current, and a main body which includes a main storage unit having a non-volatile storage area and a processor for executing programs, wherein the power supply unit includes a power failure detection unit which detects that a supply of the alternating current has been stopped, and wherein the main body includes a logical device which, when the detection is notified from the power failure detection unit, instructs the processor within a retention time of the instantaneous power failure resistance capacitor to perform transaction processing of converting data of a buffer in the processor into reusable data and transferring the reusable data to the main storage unit.

Abstract: A power supply control device for a communication network includes: a monitoring module (11) and N voltage-adjustable Direct Current/Direct Current (DC/DC) modules (121, 122 . . . 12N). The monitoring module is configured to detect circuit data of each of power supply circuits (1,2, . . . i), compare the circuit data with each other, calculate an average value, analyze required output circuit data of each of the power supply circuits, and transmit the required output circuit data of the power supply circuits to respective the voltage-adjustable DC/DC modules. The voltage-adjustable DC/DC modules are configured to receive the required output circuit data of the power supply circuits, and adjust output voltages of the power supply circuits according to the output circuit data. Output ends of all of the voltage-adjustable DC/DC modules are connected in parallel to supply power to a subordinate electro-load. Also disclosed is a power supply control method for the communication network.

Abstract: A system including a plurality of battery assemblies. Each battery assembly includes power storage and control electronics, and a communication device. Each battery assembly acts as a local hub for local direct current (DC) power demand monitoring and a local DC power supply for DC loads. Each battery assembly also charges the power storage. The plurality of battery assemblies are configured to be managed as a collective resource in aggregate via the communication device.

Abstract: An apparatus includes a communication interface, a controller, and a power section. The communication interface is configured to receive power from an external host to the apparatus. The controller is configured to limit a current drawn by the communication interface to a predetermined value when the apparatus is powered through the external host. The power section is configured to generate a first voltage from a portion of the limited current drawn by the communication interface. The first voltage powers a data storage circuitry. The power section is further configured to store electrical charges received from another portion of the limited current drawn by the communication interface. The power section is further configured to generate a second voltage from the stored electrical charges in response to a signal from the controller. The second voltage supplements the first voltage during high power events by the data storage circuitry.

Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.

Abstract: An apparatus includes a BLUETOOTH low energy (BLE) based emergency backup and recovery tool. The tool includes a backup power source that stores electric energy and outputs electric energy when a main power source is off. The tool includes a shared memory accessible by a processor and a BLE module. The shared memory stores information written by the processor, and operates using at least some of the electric energy output from the backup power source when the main power source is off. The tool includes the BLE module coupled to the backup power source. The BLE module operates using at least some of the electric energy output from the backup power source when the main power source is off, reads the information stored in the shared memory, and transmits the information to an external device through a wireless communication channel using a BLUETOOTH communication protocol.

Abstract: An information processing apparatus includes: a power-failure detector that detects a halt of power supply from a power source; a standby power supply that supplies, when the power supply from the power source is halted, standby power to a processor, a memory, and a storing device; and a disconnector that disconnects communication between the processor and a peripheral device. When the power-failure detector detects the halt of power supply from the power source, the disconnector disconnects the communication between the processor and the peripheral device and the processor carries out a memory backup process that reads data from the memory and stores the read data into the storing device. With this configuration, the memory backup process is surely carried out even in the event of power failure.

Abstract: Apparatuses, systems and methods for providing a remote user computing system with secure wireless diagnostic and programming access to an IED operatively coupled with electrical substation equipment are disclosed. An exemplary apparatus comprises a portable computer system comprising a processor and one or more non-transitory memory media storing executable instructions and a cellular modem in operative communication with one another. An antenna external to the portable computer system is adapted to be operatively coupled with the cellular modem and physically positionable independently from the portable computer system. A communication interface adapted to establish a physical electronic communication link between the portable computer system and the IED. The portable computer system, the antenna and the communication interface being provided in a human portable kit.

Abstract: In an embodiment of the invention, a method comprises: recording application-level heuristics and IO-level (input/output-level) heuristics; correlating and analyzing the application-level heuristics and IO-level heuristics; and based on an analysis and correlation of the application-level heuristics and IO-level heuristics, generating a policy for achieving optimal application performance. In another embodiment of the invention, an apparatus comprises: a system configured to record application-level heuristics and IO-level heuristics, to correlate and analyze the application-level heuristics and IO-level heuristics, and based on an analysis and correlation of the application-level heuristics and IO-level heuristics, to generate a policy for achieving optimal application performance.

Abstract: A method for protecting a computer system is performed by a smart connector is described. The smart connector tests an Internet connection provided by an Internet hub. The connector reboots the Internet hub if the testing detects a problem in the Internet connection. Then, the connector tests the Internet connection after rebooting the Internet hub. If the problem persists after rebooting the Internet hub, the connector sends a hub problem notification. The components of the smart connector are also described.

Abstract: Systems, methods, and non-transitory computer-readable storage media for smart power clamping of a redundant power supply. A system configured according to this disclosure can measure, at a baseboard management controller, a system power consumption which indicates total power being delivered by a first power supply unit and a second power supply unit. The system can determine that the system power consumption exceeds a system power consumption capacity and, in response to the determination, communicate a power clamping signal to a processor, resulting in a reduced system power consumption. The system can further identify that the reduced system power consumption exceeds the system power consumption capacity and initiate a hardware throttling of at least one of the first power supply unit and the second power supply unit.

Abstract: A computer-implemented method for managing display-related resources, the method comprising the steps of: receiving (101) an input sequence of images from a remote server; analyzing (102) the input sequence for presence of input activity at the remote server; in case of activity presence, configuring (103) the display-related resources not to invoke a resources saving action.

Abstract: Embodiments of the present disclosure disclose a method for detecting unresponsiveness of a process, wherein for each target process in a plurality of target processes, creating and activating a timer on a system kernel side, so as to time the target process; and when timing of the corresponding timer exceeds a predetermined time threshold, determining the target process to be unresponsive, and performing a predetermined associated action.

Abstract: A method includes identifying a plurality of power supplies connected for supplying power to a computer system, wherein the plurality of power supplies includes at least one redundant power supply in a standby mode. For each of the plurality of power supplies identified, the method determines a length of a power supply cable connected between the power supply and a power distribution unit for supplying power to the power supply. The method further includes placing one or more of the plurality of power supplies in an active mode in ascending order of the length of the cable connected to the power supply, and supplying power to the computer system using the one or more of the plurality of power supplies in the active mode.

Abstract: A control device in a high voltage direct current (HVDC) system is provided. The control device includes a communication unit performing communication with a component in the HVDC system; and a control unit enabling the communication unit to receive, from the component, data on an available state of the component, calculating availability of the HVDC system defined as a ratio of an actual operation time of the HVDC system to an operable time of the HVDC system based on data on the available state of the component, and then performing control of the HVDC system based on the data on the available state of the component and the availability of the HVDC system.

Abstract: The invention relates to a method of resetting a processor, the method comprising the receiving of a reset signal indicating that one or more parts of said processor need to be reset, and forwarding of said reset signal to said parts to be reset. The forwarding of the reset signal is delayed for a period of time for at least one of the parts to be reset. The clock frequency of at least one of the parts to be reset is gradually decreased during said period of time. In this way the total activity of the processor device is gradually decreased so as to avoid an on-chip voltage overshoot, which could cause a total reset of all the parts of the processor.

Abstract: The invention relates to a method for replacing a device in a network comprising a plurality of devices. The method includes a step of storing (132) replicated data of a first device in a storage means, a step of removing (352) the first device from the network, a step of connecting (354) a second device to the network, a step of providing (262) a replacement information comprising the first identifier and a step of providing (272) the replicated data of the first device from the storage means to the second device.

Abstract: In some embodiments, a PLC system includes a memory unit configured to back up user data stored in a MCU thereto when the power supply from the power module is interrupted, a capacitor configured to be charged by the power module and supply accumulated power to the memory unit when the power from the power module to the MCU is interrupted, a variable resistor unit configured to be coupled between the power module and the capacitor, and a switching unit configured to alternatively couple either the power module or the capacitor to the memory unit depending on a state of power being supplied from the power module. Some embodiments may provide advantages that a PLC system can supply much more power while reducing a charging period of time of an auxiliary power supply for supplying power with urgency when an abnormality occurs in a power module of the PLC system.

Abstract: The invention relates to a system and a corresponding method for communicating over N CAN buses comprising comprising N CAN listeners, wherein each of the CAN listeners is configured to be coupled to a respective CAN bus and to detect CAN activity on the CAN bus to which it is coupled; M CAN controllers, wherein 1?M<N; and a power controller, wherein each CAN listener is configured to generate a control signal in response to detecting CAN activity on the CAN bus to which it is coupled and send the control signal to the power controller which controls the activity state of at least one of the CAN controllers.

Abstract: An electronic device may include system and serial peripheral interface (SPI) clocks, and a host interface each switchable between active and inactive states, a serial controller coupled to the system clock, and a memory. A slave controller may generate a request active signal based upon a transaction request from a host and causing each of the system clock, SPI clock, and host interface into the active state, store request data in the memory, and switch the host interface to the inactive state based upon the request data being stored. The serial controller may process the request based upon the request active signal, and generate a request complete signal based upon the request being processed. The slave controller may switch the system clock to the inactive state based upon the request complete signal. The SPI clock may be switched to the inactive state based upon the request complete signal.

Abstract: One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a current efficiency of the at least one processor. The clock frequency controller is further configured to receive a request from the processor for a target number of processor instructions to be handled in a particular time period. The clock frequency controller is further configured to output a frequency control signal to the clock generator for controlling the clock frequency in dependence thereon.

Abstract: A method of backing up data from an electronic system is disclosed. The method may include detecting an operating mode of the battery subsystem that is a maintenance discharge cycle operating mode and in response, calculating, using a first algorithm, the available battery capacity relative to a minimum battery capacity. The method may also include detecting an operating mode of the battery subsystem that is a normal operating mode and in response, calculating, using a second algorithm, the available battery capacity relative to a maximum battery capacity. The method may also include comparing the available battery capacity to a battery capacity sufficient to complete a backup operation, detecting a backup trigger condition and in response to the backup trigger condition and the available battery capacity being sufficient to complete a backup operation, backing up, data from the electronic system.

Abstract: A method and apparatus for memory power and/or area reduction. An array of memory cells may be scanned to detect faulty memory cells, if any, in the array. A supply voltage Vmem applied to the array of memory cells may be controlled based on a result of the scan, and based on a sensitivity coefficient of one, or more, of the array of memory cells. The sensitivity coefficient may indicate an impact that the one, or more, of the array of memory cells being faulty may have on the performance of a device that reads and writes data to the memory array. Additionally or alternatively, the physical dimensions of the memory cells may be determined based on the sensitivity coefficient(s) and/or based on a number of faulty memory cells that can be tolerated in the array of memory cells.

Abstract: Power supply of ECUs connected to a communication network is optimally controlled so that power consumption is reduced. A transceiver/receiver converts a message of a differential signal received via a CAN bus into a digital signal. A select circuit determines whether the converted message is in a CAN format or a UART format. If it is in the UART format, the select circuit outputs a message to the UART circuit. A UART circuit determines whether the message matches a UART format. If matched, an ID determination circuit determines whether the input message is specifying a CAN ID of its own ECU. If it is the CAN ID of the ECU, the ID determination circuit outputs an enable signal to turn on a regulator and supply power to an MCU and an actuator.