Abstract: A method for testing an electronic memory while the memory is in use includes: (a) detecting an access to the electronic memory at a test address, (b) saving, in a register subsystem, write data written to the electronic memory at a location corresponding to the test address, (c) comparing the write data to data read from the electronic memory at the location corresponding to the test address to determine whether the memory has a fault, and (d) generating an error signal if the memory has a fault.

Abstract: A control server is electronically connected with a number of test servers via a number network interfaces. The control server records a network interface number and an IP address of a baseboard management controller (BMC) of each test server, sets an IP address of a network card of the control server, and generates a test command. The test command comprises information in relation to a number of times for powering on a test server, a number of times for powering off the test server, and a time interval between a power-on operation and a power-off operation. The test command is sent to each test server by the control server according to the network interface number and the IP address of the test server. After receiving the test command, the BMC of the test server performs power-on/power-off operations of the test server according to the test command.

Abstract: Testing a test component is disclosed. A real-time input communication that has been forked from an input communication intended for a deployed component is received at the test component. At least a portion of the received real-time input communication is processed. A result of the processing is used to at least in part determine a test result of the test component.

Abstract: In one or more embodiments, a hit test thread which is separate from the main thread, e.g. the user interface thread, is utilized for hit testing on web content. Using a separate thread for hit testing can allow targets to be quickly ascertained. In cases where the appropriate response is handled by a separate thread, such as a manipulation thread that can be used for touch manipulations such as panning and pinch zooming, manipulation can occur without blocking on the main thread. This results in the response time that is consistently quick even on low-end hardware over a variety of scenarios.

Abstract: A system-level testcase may be generated by performing system-level generation tasks by a system-level generator to produce an abstract testcase. Based upon the abstract testcase, one or more unit-level generators may generate the testcase. The testcase may be utilized in simulation of operation of a system-under-test (SUT). The testcase may be utilized for verification of the SUT. The SUT may comprise a plurality of units. The unit-level generator may be associated with units of the SUT and perform generation tasks associated with pertinent units.

Abstract: Systems and methods for modeling test space for verifying system behavior, using one or more auxiliary variables, are provided. The method comprises implementing a functional coverage model including: one or more attributes, wherein respective values for the attributes are assigned according to a test plan, and one or more constraints defining restrictions on value combinations assigned to the attributes, wherein the restrictions are Boolean expressions defining whether said value combinations are valid; determining a set of valid value combinations for the attributes that satisfy the restrictions to define the test space for verifying the system behavior; and determining relevant auxiliary variables and a corresponding function for said auxiliary variables to reduce the complexity associated with modeling the test space.

Abstract: A processor-implemented method for diagnostic testing using an expected result parameter is provided. The processor-implemented method may include establishing a known system environment associated with a function under test and setting the expected result parameter corresponding to the function under test and the known system environment. A call is issued by the processor to execute the function under test. Before returning to the caller, the function under test compares an expected result value to an actual result value. The function under test determines an error based on the actual result value being different from the expected result value and performs a low-level diagnostic based on the determined error. Then the processor receives a return value from the function under test based on the issued call.

Abstract: A method and a programmable logic controller (SPS) for verifying an application program in a failsafe programmable logic controller, wherein a signature (desired value) is generated using program modules or a complete application program when creating a program, and a copy of the signature is stored in the programmable logic controller and in an external component, respectively. Before the safety-oriented application program is started, the copy of the signature stored by the programmable logic controller is transmitted to the external component and is compared with the copy in the external component. In a further comparison, a signature (actual value) is generated using the content of the main memory of the programmable logic controller and using the actually loaded application program and is then compared with the local copy of the desired value of the signature. Starting of the actual application program is enabled only when both comparisons are positive.

Abstract: Methods, systems, and computer readable media for adjusting load at a device under test are disclosed. According to one method, the method occurs at a testing platform. The method includes determining whether a current operations rate associated with a device under test (DUT) is near a target operations rate, wherein the current operations rate is associated with one or more simulated users being simulated by the testing platform. The method also includes adjusting the current operations rate by increasing or decreasing the number of simulated users interacting with the DUT in response to determining that the current operations rate associated with the DUT is not near a target operations rate.

Abstract: A fault-spot locating method, comprising at a switching apparatus that includes an interface for connection to a master, which is a controlling object, and a plurality of ports for connection to a slave, which is a controlled object, providing another interface used to output information indicating an operation of the switching apparatus and received data, and causing the switching apparatus to transmit the information via the another interface, using a processor. And causing an apparatus that is capable of obtaining the information transmitted via the another interface to locate a spot where a fault has possibly occurred by using the information to check the received data and the operation of the switching apparatus caused by a command from the master, using the processor.

Abstract: A method, apparatus and product for explaining excluding a test from a test suite. In one embodiment, the method comprising: obtaining a reduced test suite covering test requirements, the reduced test suite excluding a test covering a subset of the test requirements; determining, by a processor, a subset of the reduced test suite covering the subset of the test requirements; and outputting an indication that the subset of the test requirements is covered by the subset of the reduced test suite.

Abstract: Systems and methods are disclosed for generating application layer test packets for testing packet communication networks. The disclosed embodiments utilize multi-stage application layer test packet generator to generate high volumes of network layer test packets in an efficient and cost effective manner. A first co-processor generates tokenized test packets that include non-application layer content and include token values representing desired application layer content. A second co-processor analyzes the token values and replaces the token values with stateful application layer content associated with the token values. Once devices-under-test (DUTs) have received and processed the application layer test packets, the DUTs generate return packets that include stateful application layer content. These return packets are then received and processed by the multi-stage application layer test packet generator.

Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.

Abstract: According to an embodiment of the present invention, a computer implemented method and system for automated test and retesting using an interactive interface provided by a computer processor comprising: a test case builder, comprising at least one processor, configured to automatically generate code for a test case; a test flow tool, comprising at least one processor, configured to generate a plurality of test flows for the test case; an execution engine, comprising at least one processor, configured to automatically execute the plurality of test flows on a system under test; and an output interface configured to receive output data from the system under test.

Abstract: A test system for a managed cloud computing environment may have a management system that may recruit devices in the cloud and outside the cloud to perform a test on a cloud based application. Each device may execute an agent that connects the device to several cloud services for messaging, data collection, and executable code storage. The management system may identify and gather the devices, then cause the devices to execute a test by sending commands through the messaging service. The devices may access executable code for the specific tasks of a test through the code storage service, and as the devices complete tasks for the test, the devices may publish results in the data collection service. The test system enables any type of scenario to be implemented, including operations that can only be performed inside and outside the managed cloud environment.

Abstract: System and method for generating an enhanced test case for a computer application is disclosed. The system provides a test preparation engine including an entity extracting module and an assembly extractor for collecting information about the computer application and corresponding database schema for generating a global report. The test case designing module designs one or more test cases by using the global report. The test case execution engine includes an input evaluation module and generates an actual result for each executed test case and an expected result for one or more database query. The report generating module includes a result storage device, a result comparator and a result analysis module and performs analysis of the actual test case result and the expected results.

Abstract: A method for performing tests using automated test equipment (ATE) is presented. The method comprises obtaining a protocol selection for programming a programmable tester module using a graphical user interface (GUI). Further, the method comprises configuring the programmable tester module with a communication protocol for application to at least one device under test (DUT), wherein the at least one DUT is communicatively coupled to the programmable tester module. Also the method comprises providing a menu of tests associated with the communication protocol using the GUI and obtaining a program flow using the GUI, wherein the program flow comprises a sequence of tests chosen from the menu of tests. Finally, the method comprises transmitting instructions to the programmable tester module for executing the program flow.

Abstract: Embodiments of the invention relate to the conversion and execution of functional tests. In one embodiment, a current test step of a manual functional test is executed. The test includes a set of test steps each including at least one action and one target of the action. The test is associated with an application that includes a plurality of objects to be tested. At least two of the objects are determined to be associated with the target of the test step. A user is prompted to provide a selection of one of the at least objects for association with the target of the test step. A new test step is generated. The new test step associates the object selected by the user with the target of the current test step. The new test step is designated for automatic execution in place of the current test step for subsequent executions thereof.

Abstract: Various example embodiments are directed to computer-implemented systems and methods for generating tests. A computer system may execute an application host and a browser. Messages originating from the application host and messages directed to the application host may be routed through the browser. The browser may be programmed to capture a plurality of application-level messages, which may comprise a plurality of requests originating from an application host and a plurality of responses directed to the application host. The computer system may generate a test scenario based on the plurality of application-level messages.

Abstract: In one embodiment, a digital asset testing system 200 may test a digital asset 202 before posting at a digital distribution store. A communication interface 180 may receive a digital asset 202. A processor 120 may execute testing of the digital asset 202 on a testing virtual machine 212 of a virtual machine set. The processor 120 may execute testing of the digital asset 202 simultaneous with testing executed on each virtual machine 212 of the virtual machine set. The processor 120 may delay testing of the digital asset 202 on the testing virtual machine 212 if a testing virtual machine configuration 214 is stale.

Abstract: Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.

Abstract: Customizing a test instrument. A plurality of pairs of code modules may be provided. Each pair of code modules may include a first code module having program instructions for execution by a processor of the test instrument and a second code module for implementation on a programmable hardware element of the test instrument. For each pair of code modules, the first code module and the second code module may collectively implement a function in the test instrument. User input may be received specifying modification of a second code module of at least one of the plurality of pairs of code modules. Accordingly, a hardware description may be generated for the programmable hardware element of the test instrument based on the modified second code module.

Abstract: In a data processing apparatus, when an instruction for starting validation is provided, or when definition information is updated, data input from a data source is collected, and a process for narrowing down of the collected data is executed. In the data narrowing process, by extracting records and items as process targets according to the definition information that defines the operation of the apparatus, the number of data items used for validation is reduced. Then, the operation is validated using the narrowed data. In the operation validation process, a virtual transfer destination of output of data is provided within the apparatus, and the data is output to the virtual transfer destination, for comparison with the output data, whereby the validation of the operation is performed.

Abstract: The incorporation of a simulation mode into existing manufacturing code test cases that communicate with a service processor. While in simulation mode, the test cases are able to run independently of system hardware or network connection. Test case code paths are exercised through the modification of simulated output, without change to the original code.

Abstract: A system and method for service aware virtualization is disclosed. The system comprises a plurality of virtual instances operating on virtualization software and a plurality of service manager modules operating on the virtualization software. Each service manager module is coupled to a separate virtual instance and configured to interface with an operation of guest software operating within the virtual instance on the virtualization software. A management interface coupled to the service manager modules interfaces with the plurality of virtual instances.

Abstract: When testing or validating a hardware system, a script file representing a portion of the firmware may be used to test the system instead of using the firmware code itself. For example, the script file may be plurality of register commands that perform the same initialization sequence as the firmware. Before connecting the hardware system to firmware drivers, the script file may be used to debug the initialization sequence. Instead of generating this script file manually, a firmware testing tool may be used. While executing the firmware, the tool may record the different register access commands performed during the initialization process. The script file is then generated programmatically using these recorded commands without requiring input from the system designer. The generated script file may then be tested on the hardware system to determine whether the command sequence in the script file forces the hardware system into the desired state.

Abstract: When testing or validating a hardware system, a script file representing a portion of the firmware may be used to test the system instead of using the firmware code itself. For example, the script file may be plurality of register commands that perform the same initialization sequence as the firmware. Before connecting the hardware system to firmware drivers, the script file may be used to debug the initialization sequence. Instead of generating this script file manually, a firmware testing tool may be used. While executing the firmware, the tool may record the different register access commands performed during the initialization process. The script file is then generated programmatically using these recorded commands without requiring input from the system designer. The generated script file may then be tested on the hardware system to determine whether the command sequence in the script file forces the hardware system into the desired state.

Abstract: The various embodiments of the present invention provide a method and system for providing random sequence coverage. The method comprising receiving a plurality of data packet packets carrying transaction data from a transaction database, specifying transactions in a configuration file along with the transaction data, identifying one or more fields in the packets received from the transaction database, generating an automatic random sequence based on the identification of at least one of a field among the one or more fields in the data packets, generating a coverage report for the random sequence generated automatically and determining uncovered sequences based on the coverage report generated.

Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.

Abstract: A device receives code generated via a technical computing environment (TCE), the code including a value to be tested, and receives a value modifier, a test case, and a constraint. The value modifier customizes a manner in which the value of the code is presented to the constraint for verification. The device also generates a test based on the value modifier, the test case, and the constraint, performs the test on the value of the code to generate a result, and outputs or stores the result.

Abstract: Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.

Abstract: The present disclosure generally relates to the testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Prior to generating the set of test cases from the grammar, the testing framework processes the grammar to identify attributes of the test cases to be derived from the grammar and facilitates the modification of the grammar.

Abstract: Environments for testing are deployed. A library of different topology groupings is provided. An interface is presented to a user for receiving environment definitions. Elements from the library of different topology groupings are automatically provided to the user for creating a test environment according to the received environment definitions. The platform delivers fully configured instantaneous topology deployments of all flavors for product development and testing efforts. The topology deployment service platform is used to create reliable topologies of varying layers of complexity, varying machine providers, different roles, different product builds, integration with partners and varying product configurations. The ability to launch and create multiple test and development environments trivially in an automated reliable fashion allows complicated customer scenarios and configurations to be deployed.

Abstract: The operator terminal 150 receives input in relation to a setting status check item being a setting item desired to be checked in the diagnostic code generation terminal, and generates a status check code, so that the status check code indicates the setting status check item received in the input. Then, the diagnostic code generation terminal 10 acquires the setting status of the diagnostic code generation terminal 10 in response to receiving the input of the status check code, the setting status corresponding to the setting status check item, and generates a diagnostic code indicating the setting status based on the acquired setting status. Then, the setting status of the diagnostic code generation terminal 10 is reproduced by inputting the diagnostic code to an operator terminal 150.

Abstract: Embodiments of the invention enable error simulation for system validation. Errors can be simulated by modifying data presented to the processor as well as generating interrupts consistent with the modified data in the ASIC hardware. Modify logic may be added to the ASIC so when the microprocessor attempts to read a specific address, the modify logic may mask one or more of the data bits returned by the requested address. Address, bit mask, and force value data may be stored in registers to determine which address may be modified, the bit location to be modified, and the value that bit location should be changed to. Selection logic may then determine whether data from the modify logic or the unmodified value from an attached device should be sent to the ASIC interface and on to the microprocessor. A timer may also be used to decouple the setup from the test.

Abstract: The disclosure relates to a computerized method and system for automatically updating a device management application with meter retrieval logic that is customized to the device mix in a managed environment. The management application would interrogate the environment and make intelligent decisions on what meter logic to implement. The management application would self adapt and retrieve the correct meter logic as the environment changes. This adaptation is not tied to product names or other identification methods, rather using rules associated with queries and responses the meter read logic is altered to the device mix. The method would first try submitting small test jobs and seeing if the known meter read logics produced the correct meter increment. If this does not confirm, the system then interprets the query of the private portion of the MIB or the web server to determine where the correct increment is located.

Abstract: The technology disclosed relates to implementing a novel architecture of a finite state machine (abbreviated FSM) that can be used for testing. In particular, it can be used for testing communications devices and communication protocol behaviors.

Abstract: In a method and system for cloud testing and remote monitoring of an IC component during validation of a computerized system connected to a cloud server via a wide area network, upon determining that a unique system code of a system platform and a unique component code of the IC component transmitted from the computerized system in response to execution of an identification operating system (OS) program and a driver from the cloud server match identification data, the cloud server transmits a corresponding test OS and a corresponding test program to the computerized system such that the computerized system produces test data corresponding to the corresponding test program in response to execution of the corresponding test OS and test program.

Abstract: A method for verifying an operation of a processor, the method includes executing, by a software simulator, a test instruction used for verifying a model dependent operation of the processor, obtaining an expectation value from a result of the executed test instruction, obtaining a result value of the test instruction executed by the processor, and comparing, by a verification processor, the obtained expectation value with the obtained result value to determine a match or mismatch between the expectation value and the result value.

Abstract: A dynamic cue signal generator and method for processing one or more input and output signals to synchronize the operation of one or more associated machines and includes processes for creating a signal delay between receiving an input signal and issuing an output signal, for conditioning an input signal to produce an output signal with required parameters, for producing a plurality of outputs signals, for filling in undetected cues in an input signal to create a filled-in output signal, for filtering noise from an input signal to generate a noiseless output signal, and for generating an error output signal to indicate that an unusual event occurs in an input signal.

Abstract: Aspects of the invention relate to techniques for fault diagnosis based on circuit design partitioning. According to various implementations of the invention, a circuit design of a failing die is first partitioned into a plurality of sub-circuits. The sub-circuits may be formed based on fan-in cones of observation points. Shared gate ratios may be used as a metric for adding fan-in cones of observation points into a sub-circuit. Based on test patterns and the sub-circuits, sub-circuit test patterns are determined. Fault diagnosis is then performed on the sub-circuits. The sub-circuit fault diagnosis comprises extracting sub-circuit failure information from the failure information for the failing die. The sub-circuit fault diagnosis may employ fault-free values for boundary gates in the sub-circuits.

Abstract: A method and apparatus for determining one or more compression parameters suitable to compress a class of signals, may include inputting a test data set, being representative of a data set to be compressed, characterizing the test data, selecting a compression algorithm, calculating a distortion level to be used in determining the compression ratio (or a compression ratio to be used in determining the distortion level), generating a computer implemented model for the test data, selecting a recommended operating point based on a computer implemented model, and determining compression parameters corresponding to the operating point. The compression parameters may subsequently be applied for configuration of compression applied to one or more production data sets that are similar to the test data. This abstract does not limit the scope of the invention as described in the claims.

Abstract: The present disclosure involves systems, software, and computer implemented methods for identifying test cases. One example process includes operations for identifying a mobile application to perform testing upon. A test environment and at least one risk situation associated with the mobile application are identified. For each of the at least one identified risk situations, at least one risk situation-relevant context parameter is identified. A standard operations path is created, as is at least one operations path-variant for each of the at least one identified risk situation-relevant context parameters. The corresponding operations path-variant is analyzed to identify a set of test cases for the context parameter, for each of the at least one identified context parameters.

Abstract: Accessing a problem report data store including customer problem reports. Each customer problem report includes configuration and platform data. Calculating a number of instances each platform is stored, and identifying platforms that satisfy a platform threshold. Calculating a number of instances each configuration is stored, and identifying configurations that satisfy a configuration threshold. Calculating a number of instances each platform is associated with each configuration, and generating a data structure with a plurality of nodes and edges. Each of the nodes identifies one of the platforms and configurations. The weight of the edge connecting a platform to a configuration indicates a number of instances that the platform is associated with the configuration in the data store. Identifying a weighted edge that satisfies a weight threshold, where the weighted edge connects a first platform to a first configuration and, in response, generating a test case for development of a software product.

Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing and using PSMI using at-speed scan capture. For example, in one embodiment, such a system includes an input signal capture device to capture input signals input to a silicon processor under test; a scan capture device to capture a scan snapshot representing a known state of a plurality of digital elements integrated within the silicon processor under test, each having state data for the silicon processor under test; a scan read-out device to communicate the captured scan snapshot to a storage point physically external from the silicon processor under test; and a model of the silicon processor under test to replay a subset of a test sequence for the silicon processor under test based at least in part on the captured input signals and the captured scan snapshot.

Abstract: A health check mechanism for an overlay network may employ tunneling technology. A health check packet may be sent between endpoints. The health check packet may be recognized in the network and may initiate a health check process on receipt. In some embodiments, the health check packet may include a signature recognized by the network. A destination endpoint, upon receipt of the health check packet, may provide health check statistics to a source endpoint.

Abstract: System and method for construction, fault isolation, and recovery of cabling topology in a storage area network (SAN) is disclosed. In one embodiment, in a method for construction, fault isolation, and recovery of cabling topology in a SAN, subsystem information associated with each subsystem in the SAN is obtained. Then, an IP port and zoning information associated with connections of each subsystem is obtained. Component information associated with each component is also obtained. Any other relevant information associated with each subsystem and each component is obtained from users. The obtained subsystem information, IP port and zoning information, component information, and any other relevant information are compiled. Test packets are then sent from end-to-end in SAN using compiled information. The sent test packets are tracked via each component in each subsystem in the SAN. The cabling topology of the SAN is then outputted based on the outcome of the tracking.

Abstract: Testing a test component is disclosed. A real-time input communication that has been forked from an input communication intended for a deployed component is received at the test component. At least a portion of the received real-time input communication is processed. A result of the processing is used to at least in part determine a test result of the test component.

Abstract: A system, apparatus, method, and computer program product for dynamically loading IT products and scaling those loads in a predictive manner are disclosed. Dynamic loading and scaling is performed by generating a load on a computing product with one or more first load generators, increasing the load over time until the first load generators reach their capacity for generating load, monitoring the capacity of the first load generators as the load is increased, provisioning one or more second load generators to generate additional load as any of the first load generators approaches its capacity, increasing the load generated by the second load generators over time until the one or more second load generators reach their capacity for generating load or the computing product reaches a performance goal, and continuing to provision second load generators until the computing product reaches the performance goal.

Abstract: During execution of a unit test, receiving from the unit test a first request referencing a mock object. An instance of the mock object and initial cached mock object data is returned to the test unit, wherein the initial cached mock object data includes first data for a real object represented by the mock object. Second data for the real object represented by the mock object is collected. The second data for the real object is compared to the initial cached mock object data. Responsive to determining that at least one aspect of the second data for the real object does not correspond to the initial cached mock object data, the cached mock object data is updated with the second data for the real object. An indication can be provided to the unit test that the initial cached mock object data returned to the unit test is unreliable.