Derived From Analysis (e.g., Of A Specification Or By Stimulation) Patents (Class 714/33)
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Patent number: 8819492Abstract: System and method for generating an enhanced test case for a computer application is disclosed. The system provides a test preparation engine including an entity extracting module and an assembly extractor for collecting information about the computer application and corresponding database schema for generating a global report. The test case designing module designs one or more test cases by using the global report. The test case execution engine includes an input evaluation module and generates an actual result for each executed test case and an expected result for one or more database query. The report generating module includes a result storage device, a result comparator and a result analysis module and performs analysis of the actual test case result and the expected results.Type: GrantFiled: December 14, 2011Date of Patent: August 26, 2014Assignee: Tata Consultancy Services LimitedInventors: Madhu Dande, RameshKumar Perumal
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Patent number: 8819493Abstract: Test configurations are generated based on information regarding hardware or software. A desired test configuration is selected. Test elements are automatically generated based on the desired test configuration, the test elements for testing at least one of the hardware or software. A plurality of test vectors is generated to test the hardware or software for the desired test configuration. The desired test configuration is converted to a script file. At least one of the hardware or software is automatically tested using the script file. Automatically testing the at least one of the hardware or the software includes using a first set of one or more test vectors from the plurality of test vectors to perform a plurality of test iterations of one or more of the actions of one or more generated test elements, and includes using at least a second set of one or more test vectors from the plurality of test vectors to determine the number of test iterations. A result of the testing is produced.Type: GrantFiled: December 3, 2012Date of Patent: August 26, 2014Assignee: The MathWorks, Inc.Inventors: Thomas Gaudette, Michelle T. Hirsh, Christian A. Portal
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Patent number: 8819497Abstract: Disclosed are various in various embodiments are systems and methods providing for storage of mass data such as metrics. A plurality of data models are generated in the server from a stream of metrics describing a state of a system. Each of the metrics is associated with one of a plurality of consecutive periods of time, and each data model represents the metrics associated with a corresponding one of the consecutive periods of time. The data models are stored in a data store and each of the metrics is discarded after use in generating at least one of the data models.Type: GrantFiled: February 18, 2013Date of Patent: August 26, 2014Assignee: Amazon Technologies, Inc.Inventors: Daniel L. Osiecki, Prashant L. Sarma, Monty Vanderbilt, David R. Azari, Caitlyn R. Schmidt
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Patent number: 8805636Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.Type: GrantFiled: October 30, 2008Date of Patent: August 12, 2014Assignee: Teradyne, Inc.Inventor: George W. Conner
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Patent number: 8806401Abstract: A system and methods for reasonable formal verification provides a user with coverage information that is used for verification signoff. The coverage is calculated based on formal analysis techniques and is provided to the user in terms of design-centric metrics rather than formal-centric metrics. Design-centric metrics include the likes of a number of reads from or writes to memories and a number of bit changes for counters, among many others. Accordingly, a setup for failure (SFF) function and a trigger the failure (TTF) function take place. During SFF formal analysis is applied in an attempt to reach a set of states close enough to suspected failure states. During TTF formal analysis is applied, starting from the SFF states, to search for a state violating a predetermined property. If results are inconclusive the user is provided with a design-centric coverage metric that can be used in signoff.Type: GrantFiled: March 27, 2013Date of Patent: August 12, 2014Assignee: Atrenta, Inc.Inventors: Mohamad Shaker Sarwary, Maher Mneimneh
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Publication number: 20140223237Abstract: A system and method for dynamically modifying scheduling of scan operations for a system under test includes a processing module configured to apply input test data to the system under test based on the scan operations via a test access port and a scheduler adapted to provide the processing module with scheduling for the plurality of scan operations. The scheduler includes a circuit model of the system under test. The circuit model includes at least one attribute providing enhancing information for at least a portion of the system under test. The scheduler is adapted to schedule the scan operations based on the circuit model and to modify the schedule based on the at least one attribute. The processing module is configured to receive the modified scheduled scan operations and to apply the input test data to the system under test based on the modified scheduled scan operations.Type: ApplicationFiled: February 4, 2013Publication date: August 7, 2014Applicants: Alcatel-Lucent, Alcatel-Lucent USAInventors: Michele Portolan, Bradford G. Van Treuren, Suresh Goyal
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Patent number: 8799703Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.Type: GrantFiled: September 16, 2013Date of Patent: August 5, 2014Assignee: Infineon Technologies AGInventors: Simon Brewerton, Patrick Leteinturier, Oreste Bernardi, Antonio Vilela, Klaus Scheibert, Jens Barrenscheen
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Patent number: 8793535Abstract: In one embodiment, a digital asset testing system 200 may test a digital asset 202 before posting at a digital distribution store. A communication interface 180 may receive a digital asset 202. A processor 120 may execute testing of the digital asset 202 on a testing virtual machine 212 of a virtual machine set. The processor 120 may execute testing of the digital asset 202 simultaneous with testing executed on each virtual machine 212 of the virtual machine set. The processor 120 may delay testing of the digital asset 202 on the testing virtual machine 212 if a testing virtual machine configuration 214 is stale.Type: GrantFiled: July 21, 2011Date of Patent: July 29, 2014Assignee: Microsoft CorporationInventors: Ghassan Salloum, Deepak Kumar, Gaurav Bhandari, Brian Anger
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Publication number: 20140195853Abstract: Embodiments are directed to establishing a model for testing cloud components and to preventing cascading failures in cloud components. In one scenario, a computer system models identified cloud components (including cloud hardware components and/or cloud software components) as health entities. Each health entity is configured to provide state information about the cloud component. The computer system establishes declarative safety conditions which declaratively describe cloud computing conditions that are to be maintained at the identified cloud components. The computer system then tests against the declarative safety conditions to determine which cloud components are or are becoming problematic. Upon determining that an error has occurred, the computer system notifies users of the error and the component at which the error occurred. Guarded interfaces are established to ensure that actions taken to fix the error do not cause further failures.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: MICROSOFT CORPORATIONInventors: Abhishek Singh, Srikanth Raghavan, Ajay Mani, Saad Syed
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Publication number: 20140195852Abstract: A method includes reading, at a memory controller, data from a first dynamic random-access memory (DRAM) die layer of a DRAM stack. The method also includes writing the data to a second DRAM die layer of the DRAM stack. The method further includes sending a request to a test engine to test the first DRAM die layer after writing the data to the second DRAM die layer.Type: ApplicationFiled: January 9, 2013Publication date: July 10, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc A. Gollub, Girisankar Paulraj, Diyanesh B. Vidyapoornachary, Kenneth L. Wright
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Patent number: 8776228Abstract: Systems and methods are provided for intrusion detection. The systems and methods may include receiving transaction information related to one or more current transactions between a client entity and a resource server, accessing a database storing a plurality of transaction groups, analyzing the received transaction information with respect to information related to at least one of the plurality of transaction groups, and based on said analyzing, determining a possibility of an occurrence of an intrusion act at the resource server. The transaction groups may be formed based on a plurality of past transactions between a plurality of client entities and the resource server. Identity information of a user associated with the one or more current transactions may also be received along with the transaction information. The user may be associated with at least one of the plurality of transaction groups.Type: GrantFiled: November 22, 2011Date of Patent: July 8, 2014Assignee: CA, Inc.Inventors: Ramesh Natarajan, Timothy Gordon Brown, Carrie Elaine Gates
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Patent number: 8769340Abstract: Techniques are described herein that are capable of automatically allocating clients for testing a software program. For instance, a number of the clients that are to be allocated for the testing may be determined based on a workload that is to be imposed by the clients during execution of the testing. For example, the number of the clients may be a minimum number of the clients that is capable of accommodating the workload. In accordance with this example, the minimum number of the clients may be allocated in a targeted environment so that the test may be performed on those clients. Additional clients may be allocated along with the minimum number of the clients in the targeted environment to accommodate excess workload.Type: GrantFiled: September 8, 2011Date of Patent: July 1, 2014Assignee: Microsoft CorporationInventors: Chunjia Li, Bowen Chen
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Publication number: 20140177084Abstract: Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability.Type: ApplicationFiled: December 20, 2012Publication date: June 26, 2014Applicant: LSI CorporationInventors: Jefferson Singleton, Shaohua Yang
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Publication number: 20140164835Abstract: A method for error simulation in a data storage subsystem providing abstractions of one or more storage devices. The method includes dividing the data storage subsystem into two or more hierarchically organized subsystems, wherein the subsystems interact using IO Request Packets (IORPs), such that relatively higher level subsystems create and populate IORPs and pass them to relatively lower level subsystems for corresponding processing. The method further includes defining an IORP modifier configured to attach to matching IORPs based on one or more attributes of the IORP modifier and to modify at least one of the processing and one or more attributes of the IORP in order to simulate errors in the data storage subsystem.Type: ApplicationFiled: December 6, 2012Publication date: June 12, 2014Applicant: Compellent TechnologiesInventors: Anthony J. Floeder, Lawrence A. Dean
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Patent number: 8751870Abstract: The various embodiments of the present invention provide a method and system for providing random sequence coverage. The method comprising receiving a plurality of data packet packets carrying transaction data from a transaction database, specifying transactions in a configuration file along with the transaction data, identifying one or more fields in the packets received from the transaction database, generating an automatic random sequence based on the identification of at least one of a field among the one or more fields in the data packets, generating a coverage report for the random sequence generated automatically and determining uncovered sequences based on the coverage report generated.Type: GrantFiled: September 13, 2011Date of Patent: June 10, 2014Assignee: Whizchip Design Technologies Pvt. Ltd.Inventors: Ravishankar Rajarao, Chinthana Ednad, Deepthi Gopalakrishna Kavalur
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Publication number: 20140157055Abstract: A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.Type: ApplicationFiled: December 5, 2012Publication date: June 5, 2014Inventors: CHRISTOPHER P. MOZAK, Thoedore Z. Schoenborn, James M. Shehadi, David G. Ellis, Tomer Levy, Zvika Greenfield
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Publication number: 20140157054Abstract: A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.Inventors: Doe Hyun Yoon, Jichuan Chang, Naveen Muralimanohar
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Publication number: 20140143599Abstract: A system and method are provided for test program generation using key enumeration and string replacement. A system includes a test program generator and a tester. The tester receives a test program from the test program generator and tests one or more products according to the test program. The test program generator receives a seed file from a seed file database and a configuration file from a configuration file database. The test program generator iterates over enumeration keys in the configuration file and, for each key, apply to the seed file one or more rules in the configuration file keyed to the enumeration key. Applying a rule includes replacing in the seed file one or more occurrences of a predicate value of the rule with a transformation value of the rule. The test program generator also outputs to the tester the modified first seed file as the test program.Type: ApplicationFiled: November 16, 2012Publication date: May 22, 2014Applicant: NVIDIA CORPORATIONInventors: Frederick Trisjono, Sravanthi Ningampally
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Publication number: 20140136897Abstract: A data verification application receives a test configuration data, the test configuration data comprising a seed value and a parameter. The data verification application generates a pseudo-random test data stream comprising a plurality of words, wherein a value of each of the plurality of words is based on the seed value, the parameter and an offset of each word within the pseudo-random test data stream.Type: ApplicationFiled: November 8, 2013Publication date: May 15, 2014Applicant: Load DynamiX, Inc.Inventor: Ivan Selivanov
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Patent number: 8719636Abstract: Performance information which is a possible generation cause of a fault is extracted accurately. A fault cause extraction apparatus 10 includes a storage unit 12 and a correlation-destruction-propagation detecting unit 25. Here, the storage unit 12 stores a correlation model including one or more correlation functions, each of which is generated based on a time series of performance information including a plurality of types of performance values in a system and transforms a performance value for one of the types being an input to a performance value for another one of the types being an output.Type: GrantFiled: January 14, 2011Date of Patent: May 6, 2014Assignee: NEC CorporationInventor: Kentarou Yabuki
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Publication number: 20140115396Abstract: A method, apparatus and product to be used in verification. The method comprising: based on a test generation input that defines a plurality of requirements automatically determining a mutated test generation input, wherein the mutated test generation input defining a mutated requirement which is absent from the test generation input, wherein the mutated requirement is based on a requirement of the plurality of requirements and contradicts, at least in part, the plurality of requirements; and generating one or more test-cases based on the mutated test generation input, whereby the one or more test-cases violate at least one requirement of the test generation input.Type: ApplicationFiled: October 24, 2012Publication date: April 24, 2014Inventors: Laurent Fournier, Anatoly Koyfman, Michal Rimon, Avi Ziv
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Patent number: 8707100Abstract: Methods and test systems for testing a network. A test system may emulate a plurality of users, each emulated user executing a user activity. Each emulated user activity may include one or more commands. At least some emulated user activities may include a command randomly selected from a predefined command pool in accordance with an associated probability distribution. The test system may report a result of emulating the plurality of users.Type: GrantFiled: December 13, 2011Date of Patent: April 22, 2014Assignee: IxiaInventors: Soumyajit Saha, Rudrarup Naskar, Luis Cazacu
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Patent number: 8707221Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analyses to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.Type: GrantFiled: October 19, 2012Date of Patent: April 22, 2014Assignee: Flextronics AP, LLCInventor: Michael Anthony Durkan
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Patent number: 8707101Abstract: Verification of a system-under-test (SUT) supporting the functionality of operating a self modifying code is disclosed. A generator may generate a self modifying code. In response to identification that a simulator is about to simulate code generated by the self modifying code, the simulator may simulate the execution in a “rollover mode”. The code may include instruction codes having variable byte size, branching instructions, loops or the like. The simulator may further simulate execution of an invalid instruction. The simulator may perform rollback the simulation of the rollover mode in certain cases and avoid entering the rollover mode. The simulator may perform rollback in response to identifying a termination condition, as to insure avoiding endless loops. The simulator may perform rollback in response to reading an initialized value that is indefinite.Type: GrantFiled: November 9, 2010Date of Patent: April 22, 2014Assignee: International Business Machines CorporationInventors: Eli Almog, Oz Dov Hershkovitz, Christopher Krygowski
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Patent number: 8707102Abstract: A method for verifying an operation of a processor, the method includes executing, by a software simulator, a test instruction used for verifying a model dependent operation of the processor, obtaining an expectation value from a result of the executed test instruction, obtaining a result value of the test instruction executed by the processor, and comparing, by a verification processor, the obtained expectation value with the obtained result value to determine a match or mismatch between the expectation value and the result value.Type: GrantFiled: September 6, 2011Date of Patent: April 22, 2014Assignee: Fujitsu LimitedInventor: Hiroshi Takao
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Patent number: 8700958Abstract: Network survivability is quantified in such a way that failure cases can be compared and ranked against each other in terms of the severity of their impact on the various performance measures associated with the network. The degradation in network performance caused by each failure is quantified based on user-defined sets of thresholds of degradation severity for each performance measure. Each failure is simulated using a model of the network, and a degradation vector is determined for each simulated failure. A comparison function is defined to map the degradation vectors into an ordered set, and this ordered set is used to create an ordered list of network failures, in order of the network degradation caused by each failure.Type: GrantFiled: March 6, 2012Date of Patent: April 15, 2014Assignee: Riverbed Technology, Inc.Inventors: Vanko Vankov, Vinod Jeyachandran, Pradeep K. Singh, Alain J. Cohen, Shobana Narayanaswamy
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Publication number: 20140101486Abstract: Multiple safety related participants are arranged along a bus line in such a way that both a forward test signal path and a return test signal path run through the same safety related participants and the safety related participants are adapted in such a way that the occurrence of a non-secure state of their protective device brings about an interruption of the test signal path. A termination element connects the forward test signal path to the return test signal path. The safety unit is configured to transmit an output signal at its output and the termination element is configured to receive the output signal from the forward test signal path and to output a test signal to the return test signal path. The test signal is changed with respect to the received output signal in dependence on the received output signal.Type: ApplicationFiled: October 2, 2013Publication date: April 10, 2014Applicant: SICK AGInventors: Stephan HENNEBERGER, Frederik BEHRE
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Publication number: 20140095935Abstract: In order to reduce computation time and cost involved with detecting and diagnosing a fault in a system, simplified representations of components of the system are used to estimate valid intervals for state variables at the components. Generic failure rules are configured to compare the estimated valid intervals to related intervals for the same state variables, from either observations or propagations, for overlap. Failure output vectors are generated based on the comparison, and the failure output vectors are compared to diagnostic matrices to determine a source of the fault.Type: ApplicationFiled: May 23, 2012Publication date: April 3, 2014Inventors: Gerhard Zimmermann, Yan Lu, George Lo
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Patent number: 8689053Abstract: A software engine has a base system in communication with service subsystems and test subsystems. The base system, the service subsystems, and the test subsystems are software applications that exchange data with one another while operating within the software engine. In one exemplary mode of operation, the base system receives outputs from the service subsystems. In another exemplary mode of operation, the base system receives outputs from the test subsystems that simulate the outputs generated by the service subsystems. An exemplary method of testing the software engine is also provided. Specifically, the illustrative method includes receiving an output during a service mode, switching from the service mode to a testing mode, and receiving the simulated output during the testing mode. The method steps may be performed by a computer executing instructions stored on a computer-readable medium.Type: GrantFiled: December 19, 2007Date of Patent: April 1, 2014Assignee: Verizon Patent and Licensing Inc.Inventors: Balaji Kumar, Yogesh Sawhney, Anne L. Miller
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Publication number: 20140082420Abstract: Automated program testing is facilitated. Test results generated based on performance of one or more tests by a program are obtained, where a test passes or fails based on output obtained based on performance of the test by the program. A failure output of the test results is identified, the failure output being of a failing test that includes at least one command, and the failure output being obtained based on performing the at least one command. A modified test is automatically generated based on the failing test, where the modified test is provided for performance thereof by the program to facilitate testing of the program. The modified test includes the at least one command of the failing test, and the modified test passes based on obtaining the identified failure output of the failing test.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Timothy D. Greer
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Patent number: 8667333Abstract: A computer implemented system for testing electronic equipment where a plurality of types of systems can be tested using a single test specification.Type: GrantFiled: May 31, 2011Date of Patent: March 4, 2014Assignee: The United States of America as represented by the Secretary of the NavyInventor: David T. Hill
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Publication number: 20140059385Abstract: A technique tests whether an integrated computing system having server, network and storage components complies with a configuration benchmark expressed as rules in first markup-language statements such as XML. The rules are parsed to obtain test definition identifiers identifying test definitions in a second set of markup-language statements, each test definition including a test value and an attribute identifier of system component attribute. A management database is organized as an integrated object model of all system components. An interpreter invoked with the test definition identifier from each rule process each test definition to (a) access the management database using the attribute identifier obtain the actual value for the corresponding attribute, and (b) compare the actual value to the test value of the test definition to generate a comparison result value that can be stored or communicated as a compliance indicator to a human or machine user.Type: ApplicationFiled: December 28, 2012Publication date: February 27, 2014Applicant: VCE Company, LLCInventors: Todd Dolinsky, Jonathan P. Streete, Nicholas Hansen, Xuning Vincent Shan
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Publication number: 20140059387Abstract: Described are an apparatus and method for managing test artifacts. A test plan is selected for a product having a plurality of test artifacts comprising one selected from a group consisting of an execution record and a product requirement. One of the test artifacts is selected for a snapshot at a current time. The snapshot includes a storage record that includes information associated with the selected test artifact and its relationship with other test artifacts at the current time. The snapshot of the selected test artifact is acquired. A current state of the selected test artifact is stored as an element of the snapshot. A current state of relationships of the selected test artifact to the other test artifacts is stored. A current state of the other test artifacts having a relationship with the selected test artifact is stored.Type: ApplicationFiled: November 5, 2013Publication date: February 27, 2014Applicant: International Business Machines CorporationInventors: Paul F. McMahan, Sachin P. Patel, John P. Whitfield, David Colasurdo
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Publication number: 20140059386Abstract: A method of testing a device is disclosed. Test data is obtained for a device testing program that tests the device. An adaptation command for testing the device is determined at an adaptive testing engine using obtained test data. The adaptation command is sent from the adaptive testing engine to a tool control application. The tool control application uses the adaptation command to control an operation related to the testing of the device.Type: ApplicationFiled: February 26, 2013Publication date: February 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David E. Atkinson, Matthew S. Grady, Donald L. LaCroix, David B. Lutton, II, Bradley D. Pepper, Randolph P. Steel
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Patent number: 8661293Abstract: A method, data processing system, and computer program product for testing a computer system. A sequencer tests the computer system using test modules arranged in a first sequence, wherein each of the test modules is for testing at least a portion of the computer system. The sequencer determines if an operator is available, in response to an interrupt generated by a test module. If an operator is available, the sequencer arranges the test modules into a second sequence based on a first policy. If an operator is unavailable, the sequencer arranges the test modules into a third sequence based on a second policy.Type: GrantFiled: June 30, 2011Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Francis E. del Rosario, Jie Li, Antoine G. Sater, Hong Ye
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Publication number: 20140032969Abstract: Method, system and product for post silicon validation using a partial reference model. The method performed by a device having registers, the method comprising: first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register; second executing, by the device when operating in non-trace mode, the test-case; and in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.Type: ApplicationFiled: July 29, 2012Publication date: January 30, 2014Applicant: International Business Machines CorporationInventors: Shimon Landa, Amir Nahir
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Patent number: 8639978Abstract: An automation process verifies that a test bed includes a set of devices specified by at least one script which are to be executed by the automation process on the test bed. The test bed is locked and the set of devices is allocated to the automation process. Performance data collection and logging for the set of devices is started and the at least one script is executed on the set of devices. After executing the at least one script, the set of devices is de-allocated and the test bed is unlocked. A notification is generated indicating that the at least one script has been executed.Type: GrantFiled: May 4, 2011Date of Patent: January 28, 2014Assignee: Aruba Networks, Inc.Inventors: Mohan Verma, Ajay Singh, Ishaan Gokhale, Pavel Semernin, Prabhat Regmi, Abhinethra T. Maras, Pragadesh Rajasekar, Sreenivasulu Lekkala
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Patent number: 8639982Abstract: An apparatus, system, and method are disclosed for probing a computer process. A probe parameter module determines a process identifier, a probe interval, and a probe action. The process identifier uniquely identifies a computer process. A start timer module starts a timer with a timer interval in response to the computer process entering an executing state on a processor core. The timer interval is based on the probe interval and on an amount of time elapsed between a probe start time and the computer process entering the executing state on the processor core. An action module executes the probe action in response to the timer satisfying the timer interval while the computer process is in the executing state on the processor core.Type: GrantFiled: June 20, 2011Date of Patent: January 28, 2014Assignee: International Business Machines CorporationInventors: Kavana N. Bhat, Muthulakshmi P. Srinivasan
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Publication number: 20140025994Abstract: The present disclosure generally relates to the testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Prior to generating the set of test cases from the grammar, the testing framework processes the grammar to identify attributes of the test cases to be derived from the grammar and facilitates the modification of the grammar.Type: ApplicationFiled: July 12, 2013Publication date: January 23, 2014Inventors: Nathan John Walter Kube, Daniel Hoffman, Kevin Yoo
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Publication number: 20140025983Abstract: A controller that obtains data from an object device in obedience to an obtaining request from the processor includes an error setter that sets, when a pseudo failure mode that spuriously generates a failure is active, an error associated with a failure type of a pseudo failure to be generated in the data obtained from the object device in obedience to the obtaining request; and an error processor that notifies, when detecting an error in the data under a state where the pseudo failure mode is active, the processor of the failure response corresponding to the failure type associated with the detected error.Type: ApplicationFiled: September 20, 2013Publication date: January 23, 2014Applicant: FUJITSU LIMITEDInventors: Noriko USUI, Katsuyuki SUZUKI
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Publication number: 20140019806Abstract: Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.Type: ApplicationFiled: July 13, 2012Publication date: January 16, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Brian C. Kahne
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Publication number: 20140013162Abstract: A transmission device has a first input unit that inputs data, a second input unit that inputs data, a first information processing unit that outputs data resulting from information processing of data input by the first input unit or data input by the second input unit, a first holding unit that holds data output by the first information processing unit, a second holding unit that holds data output by the first information processing unit, a control information holding unit that holds control information, a first selection unit that selects, on the basis of the control information, either the data held by the first holding unit or the data held by the second holding unit, and a first output unit that returns data selected by the first selection unit to the first input unit, on the basis of the control information.Type: ApplicationFiled: September 10, 2013Publication date: January 9, 2014Applicant: FUJITSU LIMITEDInventor: Masahiro MISHIMA
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Patent number: 8627146Abstract: A method includes receiving a first processing request for an application program under test. The method includes generating a second processing request for a model of the application program, wherein the second processing request is equivalent to said first processing request. The method includes communicating said first and second requests to said application program under test and said model of the application program respectively. The method includes receiving a first response data set from the application program under test and a second response data set from the model of the application program. The method includes comparing said first and second response data sets and generating a success indication if said comparing said first and second response data sets does not identify a difference. The method includes generating an error indication if said comparing said first and second response data sets identifies a difference between the first and second data sets.Type: GrantFiled: July 20, 2012Date of Patent: January 7, 2014Assignee: International Business Machines CorporationInventors: Thomas J. G. Bailey, John W. Duffell, Mark S. Taylor
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Publication number: 20140006867Abstract: Test executive system and method of use. The system includes a test executive engine, configured to execute at least one test executive sequence to test at least one unit under test (UUT), a process model that specifies one or more function sequences for pre-test or post-test functionality for the test executive sequences, and a plug-in framework, configured to selectively incorporate one or more process model plug-in instances in the process model. Each process model plug-in instance specifies at least one respective function sequence for pre-test or post-test functionality for the test executive sequences.Type: ApplicationFiled: June 28, 2013Publication date: January 2, 2014Inventor: James A. Grey
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Publication number: 20140006868Abstract: Test executive system and method of use. The system includes a test executive engine, configured to execute at least one test executive sequence to test at least one unit under test (UUT), a process model that specifies one or more function sequences for pre-test or post-test functionality for the test executive sequences, and a plug-in framework, configured to selectively incorporate one or more process model plug-in instances in the process model. Each process model plug-in instance specifies at least one respective function sequence for pre-test or post-test functionality for the test executive sequences.Type: ApplicationFiled: August 28, 2013Publication date: January 2, 2014Inventors: James A. Grey, David A. Rohacek
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Patent number: 8621280Abstract: A failure reproducing apparatus according to the present invention includes a log analyzing unit that determines processes that have caused a failure when the failure has occurred in a server system, a target-value calculating unit that calculates a target value on the basis of execution time of each process, and a time-lag calculating unit that calculates a time lag. An execution control unit adjusts timing of outputting an execution command of each process to the server system on the basis of the target value and the time lag and executes a reproduction test.Type: GrantFiled: August 23, 2011Date of Patent: December 31, 2013Assignee: Fujitsu LimitedInventor: Yoshiteru Tanaka
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Patent number: 8615682Abstract: Measurement agents in a network failure detecting system each configure a group together with other measurement agents that receive a service from the same provision server, and form a link to create a tree structure with a predetermined measurement agent in the group at its top. The measurement agent then receives measurement results from the other measurement agents in the group, and narrows down candidates of a failure location based on the received measurement results. The measurement agent transmits the narrowed candidates of the failure location to a surveillance server or one of the other measurement agents. The surveillance server then receives the transmitted candidates of the failure location, and specifies the failure location based on the received candidates of the failure location.Type: GrantFiled: December 22, 2009Date of Patent: December 24, 2013Assignee: Fujitsu LimitedInventors: Hiroshi Yamamoto, Shunsuke Kikuchi
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Patent number: 8615724Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analysis to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.Type: GrantFiled: October 19, 2012Date of Patent: December 24, 2013Assignee: Flextronics AP LLCInventor: Michael Anthony Durkan
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Patent number: 8612026Abstract: A method and a device for planning an industrial automation arrangement, where an object model is generated from data objects, which represent automation components, and from relationships between these objects, a sequence of control actions by a user is used to select the objects from an object library and to relate them to one another. A plurality of sequences of control actions and their respective effects on the object model are stored as respective entity control trees with control steps, where at least two of the entity control trees are selected and used to generate a generalized type control tree using a first comparison, and the type of control tree is used to automatically plan the industrial automation arrangement.Type: GrantFiled: January 25, 2011Date of Patent: December 17, 2013Assignee: Siemens AktiengessellschaftInventors: Thomas Banik, Sven Kerschbaum, Ronald Lange, Thomas Talanis, Frank Volkmann
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Patent number: 8606538Abstract: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.Type: GrantFiled: July 11, 2008Date of Patent: December 10, 2013Assignee: EurocopterInventors: Gilles Cahon, Christian Gaurel