Abstract: In a computer-implemented method for running a test, the test to test a system under test is generated. At least a portion of the test is designated to be run as a distributed test. The designated test portion is selected to be run in one of a synchronous execution mode or an asynchronous execution mode. Tasks of the generated test are distributed to a plurality of workers. The distributed tasks are run with the plurality of workers according to the execution mode selection.

Abstract: There is described a method for monitoring the functionality of an automation system of a plant comprising at least one main processor, parts of the plant being monitored and controlled using a user software, which is constructed of a number of program modules and which is run on the main processor. A co-processor is assigned to the main processor, and a message is transmitted from the main processor to the co-processor. When received, this message is used by the co-processor to start a monitoring time. When a subsequent message is received, this monitoring time is reset before said monitoring time has elapsed, otherwise a fault is identified once the monitoring time has elapsed.

Abstract: A method, apparatus, and computer instructions for identifying unsafe synthetic transactions and modifying parameters for automated playback. Bytecode instrumentation is used to dynamically observe the behavior of application code directly and identify each universal resource locator traversed and parameters passed in a transaction. The bytecode instrumentation may determine, based on the parameters passed, that a parameter in the current transaction is an unsafe parameter, and that the unsafe parameter is associated with a test parameter in a previously overridden transaction. If the unsafe parameter has an associated test parameter, the bytecode instrumentation may dynamically override the unsafe parameter in the current transaction with the test parameter in order to make the transaction safe for synthetic playback.

Abstract: A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction are only invoked/executed the first time the shared memory lines are accessed within a transaction. Hardware support, such as a transaction field/transaction bits, are provided to determine if an access is the first access to a shared memory line during a pendancy of a transaction. Additionally, in an aggressive operational mode version numbers representing versions of elements stored in shared memory lines are not stored and validated upon commitment to save on validation costs. Moreover, even in a cautious mode, that stores version numbers to enable validation, validation costs may not be incurred, if eviction of accessed shared memory lines do not occur during execution of the transaction.

Abstract: Provided are a method, system, and article of manufacture for checkpointing and restoring user space data structures used by an application accessing a data structure maintained by an operating system for an executing application. Information in the accessed data structure is saved with checkpoint information for the application. An operation to restore the application from the checkpoint information is initialized. A restored data structure is generated to include the saved information in the accessed data structure saved in the checkpoint information in response to restoring the application. An initialization routine of the application is modified to bypass initializing the data structure as part of the application initialization routine to restore the application.

Abstract: A data processing system is provided comprising at least one processing unit (PU) for data processing and a debugger means (DM) for debugging the processing of the at least one processing unit (PU) based on a plurality of breakpoints. The debugger means (DM) comprises a first register (BAR) for storing a base address for one of the plurality of breakpoints, wherein the debugging means (DM) initiates the debugging of the processing of the at least one processing units (PU) based on the base address stored in the first breakpoint register, i.e. the base address register. A second breakpoint register (OR) is provided for storing an offset for obtaining subsequent breakpoints. A logic arithmetic unit (LAU) is provided for repetitively calculating a breakpoint condition based on the base address stored in the first breakpoint register and the offset stored in the second breakpoint register and for updating the base address stored in the first breakpoint register.

Abstract: A method is described and represented for testing a control apparatus with a test device, where the control apparatus has at least one state variable and at least one actual functionality that contains a time dependency, and the control apparatus and the test device are connected to each other via a signal interface. The problem of the present invention is to prevent—at least partially—the disadvantages known from the state of the art, and, particularly, to provide a method for testing a control apparatus, which allows as simple and flexible an acquisition of the target functionality of a control apparatus is possible, and which takes into account the time dependency of the target functionality as comprehensively as possible during the test case generation.

Abstract: A technique is disclosed for distributed runtime diagnostics in hierarchical parallel environments. In one embodiment, a user is allowed to configure, during runtime, a processing element on which to perform diagnostics, an algorithm for the processing element to execute, a data set for the algorithm to execute against, a diagnostic function for the processing element to execute, a condition for executing the diagnostic function, and visualization parameters for memory local to the processing element. As a result, runtime diagnostics can be performed with sufficient degree of control and customization to aid debugging in a hierarchical parallel environment.

Abstract: A method of analyzing runtime memory access errors in a computer program can include instrumenting the computer program with runtime analysis code and detecting a runtime memory access error of the instrumented computer program. The method further can include, responsive to detecting the runtime memory access error, dynamically setting a watch point.

Abstract: The invention concerns an automatic method to secure an electronic calculation assembly against attacks by error introduction or by radiation. The following are used: 1) Static information generated by the automatic process; 2) A dynamic part of the memory of the electronic system allocated by the automatic process; 3) Beacons and check points to mark out the code, introduced by the automatic process; 4) Beacon functions storing information in the dynamic memory; 5) History verification functions using the static information and the dynamic memory to check that no errors have been introduced.

Abstract: A programmable processor calculates a hash value of a memory region, then monitors program operation to detect a security monitoring system initialization. The hash value is added to extend a security measurement sequence if the security monitoring system initialization clears a security state. Processors that implement similar methods, and systems using such processors, are also described and claimed.

Abstract: A debugger alters the execution flow of a child computer program of the debugger at runtime by inserting jump statements determined by the insertion of breakpoint instructions. Breakpoints are used to force the child computer program to throw exceptions at specified locations. One or more instructions of the computer program are replaced by jump instructions. The jump destination addresses associated with the break instructions can be specified by input from a user. The debugger changes the instruction pointer of the child program to achieve the desired change in execution flow. No instructions are lost in the child program.

Abstract: A diagnostic system in an aspect-oriented data processing environment is provided. The environment comprises a data processing system having an operating system for executing an application, wherein the application comprises an object class. The environment also comprises means for loading the object class at runtime and storage means for storing a diagnostic aspect. An aspect implements concerns (e.g. logging, security) that cross-cut the application. The object class of the application is loaded at runtime and the diagnostic aspect is read from the storage means. The means for loading now combines the object class with the diagnostic aspect, so that for example, diagnostics can be captured and repairs on the application can be carried out.

Abstract: Methods for handling zero-length allocations are disclosed. An example of such a method may include returning a self-describing/diagnosing dynamic address that has all the properties required for a secure implementation. Another example may include returning a series of different addresses (instead of a single address per process) to improve supportability. Yet another example may include maintaining diagnostic information about the original allocation for ease of problem resolution.

Abstract: A method of validating a probability of detection (POD) testing system using directed design of experiments (DOE) includes recording an input data set of observed hit and miss or analog data for sample components as a function of size of a flaw in the components. The method also includes processing the input data set to generate an output data set having an optimal class width, assigning a case number to the output data set, and generating validation instructions based on the assigned case number. An apparatus includes a host machine for receiving the input data set from the testing system and an algorithm for executing DOE to validate the test system. The algorithm applies DOE to the input data set to determine a data set having an optimal class width, assigns a case number to that data set, and generates validation instructions based on the case number.

Abstract: Aspects of configurable logic for hardware bug workaround in integrated circuits may comprise detecting within a chip at least one condition that would likely result in an occurrence of a hardware bug prior to the hardware bug occurring. Upon the detection of the condition, at least one trigger event may be generated within the chip via at least one debug signal, and the trigger event may be utilized to execute workaround code that may prevent the occurrence of the hardware bug. The debug signal may be generated inside the chip and/or outside the chip. The trigger event may be generated by combining a plurality of debug signals within the chip with at least one input or output signal of the chip.

Abstract: A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip area and lower the cost by means of an instruction decoder and a built-in self-test controller. The present invention also provides some peripheral control circuits of a memory. The control circuits occupies less area and enables the memory to be tested more flexibly. The present invention further provides a clock switching circuit enabling a chip to be correctly tested under different clock speeds, which benefits to advance the testability and the analyzability of the memory embedded in a chip and thereby increase fault coverage.

Abstract: A test apparatus for testing a portable communication unit. The test apparatus comprises a test unit adapted to supply test input data to the portable communication unit and retrieve test output data at least from the portable communication unit in accordance with a test schedule. The test apparatus further comprises a wireless interface unit adapted to provide a communication link between the test apparatus and a server located remotely from the test apparatus. The test unit is adapted to retrieve, from the server, at least part of the test input data. Moreover, the test unit is adapted to forward, to the server, at least part of the test output data. A method of testing the portable communication unit is also disclosed.

Abstract: A new system service table is dynamically generated to allow dynamic insertion of code between the caller of a native operating system function, in user or kernel mode, and the operating system's implementation of the native operating system function. The dynamically inserted code has full access to the function parameters, such as arguments. The new system service table has encoded values that are relative to the base address of the new system service table and which include the function addresses of the native operating system functions corresponding to original system service table entries in the original system service table.

Abstract: A processing apparatus includes: first and second register files, the latter holding a part of data in the former; an operation unit to operate on data in the second register file and to output data; an instruction unit to issue a write instruction to write, to both register files, the output data and an error detection code for it, and first and second occurrence instructions; a first control unit to issue a first generation instruction when receiving the write instruction and the first occurrence instructions; and a first generation unit to generate a first simulated fault data to output it to the first register file when receiving the first generation instruction, and to output the output data and the error detection code to the first register file in absence of the first generation instruction. Similar second control and generation units are also provided mutatis mutandis.

Abstract: A computer implemented method, computer program product, and computer usable program code for preventing execution of program components having errors. First, a software application is executed. The software application interacts with a number of programs. Next, an error message is received. The error message indicates an error has occurred in a first program within the number of programs. The first program is then isolated such that the first program no longer interacts with the software application.

Abstract: In a multitask execution environment, a debugging device performs debugging setting for rewriting part of original recording content in a memory area shared by at least two tasks, and debugging cancellation for restoring rewritten recording content back to original recording content. The debugging device stores a memory area used by each task, and address information specifying each debugging target task and a respective address. When task switching occurs, if a next task is not a debugging target, recording content at a physical address specified by address information other than that of the next task and within the physical address space range used by the next task is put into a post-debugging cancellation state. If the next task is a debugging target task, in addition to the above processing, recording content at the physical address specified by the address information of the next task is put into a post-debugging setting state.

Abstract: Techniques that may be utilized in a multiprocessor system are described. In one embodiment, one or more signals are generated to indicate that a breakpoint instruction is executed by one of the plurality of processors in the multiprocessor system. For example, a signal may be generated to indicate whether a processor is to be halted once it receives the a signal that indicates the breakpoint instruction. Other embodiments are also disclosed.

Abstract: A method includes providing a debug instruction and providing a debug control register field, where if the debug control register field has a first value, the debug instruction executes a debug operation and where if the debug control register field has a second value, the debug instruction is to be executed as a no-operation (NOP) instruction. A data processing system includes instruction fetch circuitry for receiving a debug instruction, a debug control register field, and debug execution control circuitry for controlling execution of the debug instruction in a first manner if the debug control register field has a first value and in a second manner if the debug control register field has a second value, where in the first manner a debug operation is performed and in the second manner no debug operation is performed.

Abstract: A method for debugging a multitask program executed by a processor includes interrupting the processor during the execution of a task of the program, and activating a debugging mode of the processor, wherein the instructions executed by the processor are supplied by an external emulator. The method comprises steps during which: the processor sends an activation message to the external emulator every time the debugging mode is activated, and upon receiving the activation message, the external emulator sends an acknowledgement message to the processor containing at least one portion of the activation message received.

Abstract: A test system 100 that can accept a plurality of plug-in electronic cards in Xi Slots 126 or PXI slots 134 is described. The test or source measure switching system 100 includes a sequencer or sequence engine 130 which is fully capable of executing opcode instructions having potentially indefinite completion times and monitoring multiple asynchronous inputs simultaneously without interrupts. The sequencer 130 is sequential and deterministic to approximately ten microsecond resolution.

Abstract: According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.

Abstract: A compiler for incorporating error detection into executable code generates conventional assembler language object code from a source code file. The compiler identifies an error detection segment (EDS) in the assembler code, where the EDS includes a subset of basic blocks in the assembler code. The compiler also identifies register and memory references in the EDS and inserts a set of instructions into the EDS. The inserted instructions record an entry state and an exit state of the referenced registers and memory locations. The state information is stored in a checkpoint portion of system memory. The compiler may generate shadow EDS code including instructions mirroring the instructions in the main EDS and verifying instructions that compare results produced by the mirroring instructions with results produced by the main EDS. The shadow EDS initiates an error recovery process if results produced by the shadow EDS and the main EDS differ.

Abstract: An electronic device is connected to a loop transmission line via a bypass circuit and detects being bypassed from the loop transmission line. Each electronic device connected to a looped transmission line via each bypass circuit receives a positioning map in which an own address is registered, and judges whether the own address is still registered. The electronic device can judge whether this electronic device is being bypassed from the loop transmission line by the bypass circuit using a conventional sequence.

Abstract: Break and optional hold preserves a state of a computing environment on which a software program has failed. Being able to examine the status of the environment existing upon the occurrence of the failure, including the condition of various processes and values facilitates resolution of the cause of the failure. Upon occurrence of a failure during the execution of a first software program in a first computing environment, execution of the first software program breaks. A first state of the first computing environment existing upon the breaking in execution of the first software program is then held. A failure notification is generated to signal the failure to a monitoring system. The monitoring system accesses hold information to determine whether the first computing environment should hold its current state and whether one or more other computing environments interacting with the first computing environment should also hold their states.

Abstract: A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.

Abstract: The same testing equipment can be used to test devices operating under different protocols. Where the testing protocol is slower than the native serial protocol of the high-speed serial link connecting the device processor to the component to be tested, the link may be adapted to carry the lower speed testing protocol. This may be accomplished by adding low-speed buffers to the circuits of the serial link, or the serial link may have a native low-speed protocol in addition to its high-speed protocol connections may be made to the pathways for the native low-speed protocol, or the testing protocol may be impressed on top of native low-speed protocol. Where the driver of the device being tested has limited number of pins, the test mode can be controlled by applying power to different power supply input pins.

Abstract: A software testing system operative to test a software application comprising a plurality of software components, at least some of which are highly coupled hence unable to support a dependency injection, each software component operative to perform a function, the system comprising apparatus for at least partially isolating, from within the software application, at least one highly coupled software component which performs a given function, and apparatus for testing at least the at least partially isolated highly coupled software component.

Abstract: There is provided a test apparatus for testing a device under test. The test apparatus includes an instruction storing section that stores thereon a test instruction sequence, a pattern generating section that sequentially reads and executes an instruction from the test instruction sequence, and outputs a test pattern associated with the executed instruction, a test signal output section that generates a test signal in accordance with the test pattern, and supplies the generated test signal to the device under test, and a result register that stores thereon a value having a predetermined number of bits.

Abstract: A test system for testing various functions of electronic devices includes a master device and a simulation control device. The master device is connected to an input device and the electronic devices through the simulation control device. The master device records input signals of the input device and generate simulation signals according to the input signals. The simulation control device simulates the input signals of the input device according to the simulation signals to test the electronic devices.

Abstract: A method is provided for controlling RAM variables embedded in a microprocessor software executable without modifications to the underlying source code. The method includes: presenting an software program having a plurality of machine instructions of a finite number of fixed lengths in an executable form; searching through the machine instructions of the executable and finding at least one appropriate instruction to replace; defining a replacement instruction for identified machine instructions in the software program; and replacing identified machine instructions in the executable form of the software program with the replacement instruction. The replacement instruction may be further defined as a branch instruction that references an address outside an address space for the software program.

Abstract: There is provided a test apparatus that tests a device under test. The test apparatus includes a pattern memory that stores a test instruction stream determining a test sequence for testing the device under test, an interval register that stores a repeated interval in response to the fact that the repeated interval showing at least one instruction to be repeatedly executed in the test instruction stream has been specified, an instruction cache that caches the test instruction stream read from the pattern memory, a memory control section that reads the test instruction stream from the pattern memory and writes the read stream into the instruction cache, a pattern generating section that sequentially reads and executes instructions included in the test instruction stream from the instruction cache and generates a test pattern corresponding to the executed instruction, and a signal output section that generates a test signal based on the test pattern and supplies the generated signal to the device under test.

Abstract: A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit.

Abstract: Transactional programming promises to substantially simplify the development and maintenance of correct, scalable, and efficient concurrent programs. Designs for supporting transactional programming using transactional memory implemented in hardware, software, and a mixture of the two have emerged recently. However, certain features and capabilities that would be desirable for debugging programs executed using transactional memory are absent from conventional debuggers. Breakpointing is one example of a capability not well supported when conventional debugging technology is applied to transactional memory. We describe techniques by which a debugger may instrument code (or by which a TM library may provide functionality) to direct execution of an atomic block to a code path that facilitates breakpoint handling.

Abstract: A status transition table generation portion generates a status transition table containing combination information cells provided in the form of a matrix for describing information corresponding to combinations of internal status and event. In a status transition table design support portion, a test path generation portion generates a test path including a series of test cases to be executed as a status transition test, based on information accepted by an operation specification information input acceptance portion. In a test support portion, a test cell highlight portion highlights a combination information cell associated with the next test case to be executed, during execution of the status transition test, and a test result history, an error replication procedure, and test progress are displayed on a display portion.

Abstract: A finalizer may include a notification that no tolerance for failure or corruption is expected. Any potential failure point, which may be induced by a runtime execution environment routine or subroutine that is associated with the finalizer may then be prepared apart from the finalizer.

Abstract: A hardware health evaluation module is associated with a hardware module or device and employs a linked list of error records to continually evaluate the state of the hardware module to determine whether or not it is currently operating with or without errors. In the event that the health evaluation module determines that the hardware module is not operating in an error free manner, it detects and stores, for a specified period of time, an indication of the error and associates this detected error or errors with one or more of the error records. The error records are designed to provide assistance in diagnosing the cause of a hardware error.

Abstract: A method comprising the steps of (A) generating a code, (B) applying one or more constraint constructs to the code, (C) generating a coverage code and a second code in response to applying the constraint constructs to the code, (D) generating a third code in response to the code, and (E) generating one or more assembly language tests in response to the second code.

Abstract: A method for performing kernel-level diagnostics. The method includes obtaining a hardware trap associated with an attempt by a kernel-level instruction stream to access a memory address, wherein the memory address is referenced by a hardware watchpoint facility, forwarding the hardware trap to a software breakpoint handler, executing a diagnostic instruction defined by the software breakpoint handler to obtain diagnostic data, transmitting the diagnostic data to a user, and returning execution flow to the kernel-level instruction stream.

Abstract: A method and system for determining code coverage of one or more software modules is disclosed. The disclosed method and system uses an enumeration module, a code coverage module and an analysis module. The enumeration module is used to identify portions of the code in the software module for which code coverage data is desired. The code coverage module collects code coverage data when the software module is loaded. The analysis module summarizes and reports results of the collected code coverage data.

Abstract: A method and system for debugging an executing service on a pipelined CPU architecture are described. In one embodiment, a breakpoint within an executing service is set and a minimum state of the executing service is saved. In addition, a program counter of the executing service is altered. The program counter is restored and the state of the executing service is restored.

Abstract: Compiled breakpoint analysis includes a debugger user interface that is displayed for defining breakpoint properties. Responsive to a predefined user selection, a conditional breakpoint and condition are exported to be compiled for debug. When a source module is compiled for debug, the conditional breakpoint is inserted into the program executable for a user-selected line. When debugging the program executable, the compiled conditional breakpoint is identified. A compiled breakpoint table is used to set a conditional breakpoint on the user-selected line and to identify statement numbers for the true and false legs of a compiled condition.

Abstract: A method and apparatus to insert special instruction. At least one of the illustrative embodiments is a method comprising converting a first representation of a computer program to a second representation, and inserting into the second representation a special instruction not needed to implement functionality in the first representation. The special instruction gives duplicate copies of the computer program executed in different processors an opportunity to service external asynchronous interrupts.

Abstract: A method, apparatus and computer program product are provided for implementing automatic reapportionment of graphical screen subwindows based upon sensed, dynamic changes. Predefined dynamic change information is monitored for selected subwindows. The monitored predefined dynamic change information is compared with user selected configuration values to determine a reapportionment for the selected subwindows.

Abstract: Some aspects provide determination of a debug event, selection of a controller context based on the determined debug event, and execution of the selected controller context. The debug event may be associated with a microprocessor, and the controller context may be selected based on predetermined associations between a plurality of debug events and a plurality of controller contexts.