Abstract: A method and program product for gathering information about a system. A user logs on to the system, and in response, computer programming automatically identifies application instances executing in the system, determines whether the system is configured for high availability, determines whether each of the identified application instances is configured for high availability, determines if the system is a node of a cluster of systems, and compiles and displays a unified report of the resulting information. The foregoing type of information is automatically compiled and displayed for other systems as well, in different respective sessions.

Abstract: Detecting a race condition is disclosed. An indication of a store operation to a memory address is received. An identifier of the memory address is stored. The identifier is used to detect an occurrence of a memory operation that is not associated with a previous ordering operation.

Abstract: Interleaving improves noise rejection in digital communication and storage systems. According a known scheme, the interleaving/deinterleaving is achieved by storing symbols in a temporary memory table of R rows×C columns in a row by row order, and reading them in a column by column order, or vice versa, so obtaining a rearranged order. Methods and devices for interleaving and deinterleaving are proposed which accomplish the same interleaving/deinterleaving operation with a reduced size of the temporary memory table. The rearrangement of the symbols according to the rearranged order is accomplished by using a table with a reduced memory size, in combination with the order with which the symbols are fetched from or stored in a further memory. The invention further relates to ICs and apparatuses for interleaving and/or deinterleaving.

Abstract: A transmission-reception apparatus does not configure ARQ control information from only sequence number, but the transmission-reception apparatus configures the ARQ control information such that the ARQ control information is comprised of one sequence number containing first occurrence of a corresponding packet's error, and bit information representing existence of retransmission requirements about sequence numbers followed on the heels of such the one sequence number.

Abstract: A system and associated method for determining a recovery time for a resource in a heterogeneous computing environment comprising interdependent resources. A graph for the resource representing all sequence dependencies and all group relations are created. The recovery time may be a cumulative startup time or a cumulative shutdown time of the resource considering interdependencies of the resource to other resources. The recovery time for all support resources having sequence dependencies with the resource is calculated and each node representing the support resources are removed from the graph. Then the recovery time for all member resources left in the graph that have group relations with the resource is calculated per a group type of the resource. The recovery time for the resource is a sum of the recovery time of all support resources, the recovery time of all member resources, and a unit recovery time of the resource.

Abstract: With fast notification of changes to a clustered computing system, through which a number of events are published for system state changes, applications can quickly recover and sessions can quickly be rebalanced. When a resource associated with a service experiences a change in status, such as a termination or a start/restart, a notification event is immediately published. Notification events contain information to enable subscribers to identify, based on matching a session signature, the particular sessions that are affected by the change in status, and to respond accordingly. This allows sessions to be quickly aborted and ongoing processing to be quickly terminated when a resource fails, and allows fast rebalancing of work when a resource is restarted.

Abstract: A test circuit for testing a command signal at a package level in a semiconductor device includes: a logic level determining unit for determining logic levels of a plurality of command flag signals in response to a plurality of internal command signals in a test mode; a storage unit for storing the plurality of command flag signals in response to a store control signal and outputting the plurality of command flag signals in series in response to an output control signal; and an output unit for driving an output signal of the storage unit to a data pad.

Abstract: A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly.

Abstract: Systems for detecting unexpected program flow may include a hardware program flow monitor to generate an interrupt signal if a software program flow value does not match an incrementally updated hardware value when a processor executes a program flow check instruction. In some examples, a program of instructions may include a number of program flow check instructions. When a program flow check instruction is executed, the processor may send the software value to be compared to the hardware register value. In an illustrative example, program execution causes the hardware value to be incremented in a hardware register. Upon execution of a program flow check instruction, the hardware value is compared to a software value associated with the program flow check instruction to determine if the program instructions have been executed in an expected sequence (e.g., according to an expected program flow).

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A time correcting apparatus includes a data input section which inputs all event trace data generated for each event executed on computing devices and outputs the event trace data in order of occurrence time of the event data. An inter-machine communication-time-table generating section extracts transmission and reception events from the output event trace data and generates a communication time table indicating communication times between computing devices based on the differences in occurrence time between the corresponding transmission and reception events. A time-offset deriving section generates a time offset table indicating a time offset value for each computing device based on the communication time table. A time correcting section corrects the event occurrence times of all event data based on the time offset table. A data integrating section inputs all event data whose occurrence times have been corrected and outputs the event data in order of corrected occurrence time.

Abstract: An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the first deserializer and interprets the test instructions and data using the first format. A frame capture module receives test results according to the interpreted test instructions and data. A first control module communicates with the frame capture module and generates first format control data. The frame capture module packages the test results and the first format control data into frames. A first serializer serializes the frames.

Abstract: A packet transmission system is provided which successively sends source data from a sender unit after dividing the data into packets and sends a receipt acknowledgment in response to each packet sent from a receiver unit that has received the receive packet to the sender unit. The receiver unit has: a data position storage unit storing the data position of the received, already received packet on the source data; a data position comparison unit comparing the data position on the source data stored in the data position storage unit and the data position of the receive packet on the source data; and a receipt acknowledgment creation unit creating the receipt acknowledgment in a case where the data position comparison unit determined that the data position of the receive packet on the source data is behind the data position on the source data stored in the data position storage unit.

Abstract: Described are techniques for obtaining configuration information and conditionally executing a system call in accordance with a specified configuration state. A host issues a request for configuration information from a data storage system. The data storage system maintains a separate table of configuration information representing a configuration state of the data storage system. The host receives a response including a custom value indicating the current configuration state. The host may issue a request to the data storage system to conditionally execute a call if the data storage system is in a configuration state corresponding to the custom value.

Abstract: A method and system of signal noise reduction used for digital chips to prevent errors when signal noise occurs includes checking whether a recent received signal is logically consistent. If the recent signal is consistent, then the consistent signal is adopted. If the recent signal is not consistent, then a previous confirmed signal is adopted.

Abstract: A scheme for monitoring links in a point-to-point architecture computer system is discussed. The scheme monitors labels for transactions to determine if they have been reissued within a user selected time window. A corresponding position in a register is updated to reflect the value of the transaction identifier. Subsequently, after the expiration of a counter, the corresponding position in the registers is compared to other predetermined positions in other registers to determine if the transaction identifier has been used (reissued). Otherwise, a possible hang condition might have occurred.

Abstract: Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.

Abstract: An exemplary automatic hi-pot test apparatus (20) includes a high voltage supply (21), a transmission device configured for transmitting an electronic device (26) to be tested, a connecting device electrically connected to the high voltage supply and configured for moving and electrically connecting with or electrically disconnecting from the electronic device, a controller (28) for controlling the connecting device and the transmission device, and a detector (27) for detecting the presence of the electronic device. When the detector detects the presence of the electronic device, the detector sends a corresponding detecting signal to the controller, such that the controller stops the electronic device and drives the connecting device to electrically connect with the electronic device whereby a hi-pot test can be performed.

Abstract: An efficient technique for performing remote asynchronous mirroring includes receiving a stream of command requests, performing the requested commands, relaying the requested commands to a target while embedding an explicitly-defined or implied task precedence graph in the relayed commands to enable increased concurrency in tasks performed by the target.

Abstract: This invention provides a storage apparatus which can avoid a data lost even when a short-circuit fault occurs in a power source line which is not made redundant for a plurality of hard disk drives. In the storage apparatus, a storage control unit comprises a host interface control unit, a disk interface control unit, a cache memory, and a data transfer unit, and a storage unit includes poly switches provided for each of the power source lines to a plurality of hard disk drives and a power source line monitor circuit for monitoring the voltage of the power source line. When the voltage abnormality due to a voltage drop of the power source line is detected by the power source line monitor circuit, a data line connecting the disk interface control unit and the plurality of hard disk drives is cut off.

Abstract: A method and program product for gathering information about a system. A user logs on to the system, and in response, computer programming automatically identifies application instances executing in the system, determines whether the system is configured for high availability, determines whether each of the identified application instances is configured for high availability, determines if the system is a node of a cluster of systems, and compiles and displays a unified report of the resulting information. The foregoing type of information is automatically compiled and displayed for other systems as well, in different respective sessions.

Abstract: A method of performing diagnosis comprises receiving in a computer system executable program instructions that, when executed, cause the computer system to perform a first user-developed automated diagnostic procedure that either fails or passes depending on at least one condition in the computer system. The computer system has stored therein a program 1) that, when executed, performs a plurality of preconfigured automated diagnostic procedures and 2) that is configured to accept user-developed automated diagnostic procedures. The program is executed in the computer system and in so doing the plurality of preconfigured automated diagnostic procedures and the first user-developed automated diagnostic procedure are performed.

Abstract: A network appliance for monitoring, diagnosing and documenting problems among a plurality of devices and processes (objects) coupled to a computer network utilizes periodic polling and collection of object-generated trap data to monitor the status of objects on the computer network. The status of a multitude of objects is maintained in memory utilizing virtual state machines which contain a small amount of persistent data but which are modeled after one of a plurality of finite state machines. The memory further maintains dependency data related to each object which identifies parent/child relationships with other objects at the same or different layers of the OSI network protocol model. A decision engine verifies through on-demand polling that a device is down. A root cause analysis module utilizes status and dependency data to locate the highest object in the parent/child relationship tree that is affected to determine the root cause of a problem.

Abstract: Each processor in a multi-processor system is periodically interrupted for preempting the current thread for servicing of a watchdog thread during normal operation. Upon failing to service the watchdog thread over a grace period, a system watchdog initiates an orderly shutdown and reboot of the system. In order to prevent spinlocks from causing fake panics, if the current thread is holding one or more spinlocks when the interrupt occurs, then preemption is deferred until the thread releases the spinlocks. For diagnostic purposes, a count is kept of the number of times that preemption is deferred for each processor during each watchdog grace period.

Abstract: An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: A set of peripheral chips for realizing hardware functions of a control device has at least two electronic units, which allow partitioning for the purpose of providing at least one basic functionality for a control device. This first and/or second electronic unit(s) may typically be configured as application-specific electronic switching circuit (ASIC).

Abstract: Integrated circuit bus integrity may be verified without specialized test equipment. In a diagnostic mode, the integrated circuit may output a series of predetermined activation patterns onto the data bus to verify integrity of the data bus. Further bus verification may be provided by an address capture mode where address bus contents are reflected onto the data bus. A microprocessor may control diagnostic mode operation.

Abstract: A system and associate method handle out-of-order data supplied by a real-time feed, and ingests the real-time feed fast enough to keep up with the feed rate while storing the data in a database in a time-ordered or other sequential manner without discarding any data. The present system adds a second unordered list for out-of-order data received from the feed or from a replay feed. A data element received from the feed, which has a time stamp earlier than the last data element placed in the ordered list, is placed in the unordered list. If replay data is received, the replay data elements are placed in the unordered list without verifying the time stamp. The data is then flushed from these memory lists to a database. Both the ordered list and the unordered list are inputted into the database. The database handles the ordering and merging of these two lists on insertion.

Abstract: A method, system and apparatus for diagnosing network protocol errors using an XML document are provided. Data packet exchanges are captured and used to generate an XML document. In one embodiment, the XML document is passed through a parser to diagnose the errors. In another embodiment, the network protocol errors are diagnosed by visually inspecting the XML document.

Abstract: A computer software tool for aiding in the design of combinatorial logic and sequential state machines comprising, according to the preferred embodiment, an apparatus and methods for representing and displaying a mathematical transform between a binary output variable and a set of binary input variables. The apparatus includes a computer software program which performs a method having the steps of separating input variables of a transform into successive fields, providing field combination maps having cells representative of binary combinations of field variables, assigning field combination maps of successive fields to each preceding field cell, and assigning binary values to field cell chains formed thereby. The computer software program also enables the visual display, on the display of a computer monitor, of the combination maps and the relationship between combination maps of preceding and successive fields.

Abstract: To provide a system for monitoring data transmitted between parts of an electronic machine. The system includes a mirror memory circuit that is subjected to writing and reading of data in the same manner as a memory circuit based on first data to be supplied from a memory controller to a memory circuit, and a signal sampling circuit that stores in a sampling memory circuit the first data as well as second data read out of the mirror memory circuit. The sampling memory circuit stores exact copies of the first data supplied from the memory controller to the memory circuit and exact copies of the second data supplied from the memory circuit to the memory controller. Therefore, it is possible to monitor the data transmitted between the memory controller and the memory circuit.

Abstract: Methods and Systems for generating a status report from source code is described. Data that describes the status of one or more tasks associated with a source code file is received. The data is maintained as a part of the source code file. A status report is generated based on the data.

Abstract: An early clock fault detection method and circuit for detecting clock faults in a multiprocessing system provides an error system that can be used to shutdown the multiprocessing system or a processor before errors caused by loss of synchronization between multiple processors can propagate from the processor causing storage or other systems to be corrupted. The detection circuit counts cycles of a high-frequency internal processor clock generated by multiplying an external master clock signal and detects whether or not a predetermined number of clock cycles have elapsed between transitions of the external master clock signal. The detection circuit provides a clock fault output within less than a master clock cycle, which can be used to shut down the processor, system or interconnect between processors, preventing loss or corruption of data before the high-frequency clock can drift enough to cause errors.

Abstract: A system and associate method handle out-of-order data supplied by a real-time feed, and ingests the real-time feed fast enough to keep up with the feed rate while storing the data in a database in a time-ordered or other sequential manner without discarding any data. The present system adds a second unordered list for out-of-order data received from the feed or from a replay feed. A data element received from the feed, which has a time stamp earlier than the last data element placed in the ordered list, is placed in the unordered list. If replay data is received, the replay data elements are placed in the unordered list without verifying the time stamp. The data is then flushed from these memory lists to a database. Both the ordered list and the unordered list are inputted into the database. The database handles the ordering and merging of these two lists on insertion.

Abstract: A fault tolerant availability meter includes agents for stand-alone computers and each node of a cluster. The agents monitor availability with timestamps and report uptime and downtime events to a server. Additionally, agents on nodes of a cluster monitor cluster, node and package availability and cluster configuration changes and report these event to the server. Events are stored locally on the stand-alone computers and nodes, and additionally, on the server. Events are tracked with a sequence numbers. If the server receives an out-of-sequence event, an agent-server recovery procedure is initiated to restore the missing events from either the agents or the server. The server may generate availability reports for all monitored entities, including one or more stand-alone computers and one or more clusters of computers. Availability is distinguished by planned and unplanned downtime. Furthermore, unavailable and unreachable systems are identified.

Abstract: A method of detecting illegal execution of code sequences includes the steps of: setting an active identifier to a first sequence identifier of a first code sequence, executing at least part of the first code sequence, calling, from the first code sequence, a second code sequence having a second sequence identifier, providing (20) a caller sequence identifier and a callee sequence identifier, checking (21) whether the callee sequence identifier is the same as the second sequence identifier, checking (23) whether the caller sequence identifier is the same as the active identifier, and generating (27) an alarm signal if either of the checks provide incorrect results.

Abstract: A method of validating a procedure allows several processes to be involved in the validation of a single event. The method involves defining relationships between FSMs which describe the entities, selecting the processes which fulfill certain criteria, and processing the event in all of the selected processes.

Abstract: In computer system comprising a computer (10) and a peripheral (such as a radio transceiver card 18), the computer is operable to run a device driver (28a) for the peripheral and an application (30a), and the computer is operable to produce a command (CON) in dependence upon the application and device driver and to make the command available to the peripheral to control the peripheral. In order to enable the peripheral to have low intelligence, not requiring its own microprocessor, but prevent inappropriate commands being actioned by the peripheral, the. peripheral is operable in response to receipt of such a command to compute a challenge (CHN) and to make the challenge available to the computer. The computer is then operable in dependence upon the device driver to compute a response (RN) which is a first predetermined function, at least in part, of the challenge and to make the response available to the peripheral.

Abstract: The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified. The external event is asserted when there is a match between the target instruction address and a pipeline instruction pointer corresponding to a second pipeline stage. The second pipeline stage is earlier than the first pipeline stage in the pipeline chain. The external event is unmasked via a delivery path between a signal representing the asserted external event and the first pipeline stage.

Abstract: A system, method and article of manufacture are provided for recording exception handling requirements for maintaining a consistent error handling approach. An exception response table is provided in which an exception is recorded. The context of the exception is entered in the exception response table and a response for the exception is listed in the exception response table. The response is subsequently outputted upon the exception occurring in the context.

Abstract: A method analyzes memory transaction processed by memories of a computer system. The method selects a set of addresses of the memories. State information from a plurality of consecutive predetermined memory transactions to the selected addresses are recorded while the selected transactions are processed by the memories. The selecting and the recording steps are repeated until a termination condition is reached. Then, the recorded state information is statistically analyzed to estimate statistics of properties of the memory interactions among contexts in the computer system.

Abstract: A method and system for detecting and correcting error conditions on sequential devices in a private loop direct access fiber channel network respectively include the steps and instructions for determining the state of an exchange using an initiator and initiating an appropriate sequence level recovery using the initiator. The invention further includes determining whether a target response is overdue using a timer in conjunction with internal driver state information for indicating that packet information may have been lost. The invention further requests exchange and sequence state information from the target for determining the need for corrective action and takes the needed corrective action, such as resending sequence information, requesting that the target resend sequence information, or providing early indication to the ULP that an error has occurred.

Abstract: A sound controller has a signal pin for externally outputting the contents of bit 1 of a control register for controlling its operation mode as a power down signal POWERDOWN# for controlling a power supply to analog audio amplifiers. The power down signal POWERDOWN# output from the signal pin is sent to a power supply controller. The power supply controller switches supply/stop of a power supply voltage VCC2 to the analog audio amplifiers in response to the signal POWERDOWN#. With this control, the power down control of the analog audio amplifiers can be realized in accordance with the state of the sound controller.

Abstract: An arrangement for providing command responses in a sequence that is independent of the sequence that commands are initiated by an initiating bus to a target bus. A first memory array stores commands from the initiating bus in a first sequence, and provides the commands to the target bus in a first sequence. Multiple delayed completion registers are provided, each to receive and store one of the commands entered into the first memory array. The delayed completion registers re-enter its corresponding stored command into the first memory array when a request is received to reissue the command. A second memory array stores command responses in a second sequence that relates to the order that their corresponding commands were successfully completed on the target bus.

Abstract: A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge system. A method for improving partial cache line writes from I/O devices to the central processing units incorporates cache coherency protocol and an enhanced invalidation scheme to ensure atomicity while minimizing the bus utilization. In addition, a method for allowing peer-to-peer communication between I/O devices coupled to the system bus via different I/O bridges includes a command and address space configuration that allows for communication without the involvement of any central processing device. Interrupt performance is improved through the storage of an interrupt data structure in main memory. The I/O bridges maintain the data structure, and when the CPU is available the interrupts can be accessed by a fast memory read, thereby reducing the requirement of I/O reads for interrupt handling.