Abstract: An electronic control unit for a car in which a control portion operates in accordance with signals given from a plurality of input portions including a car ignition switch to thereby perform drive control of a predetermined output portion, the control portion having a sleep function by which the control portion stops when the control portion in not required to operate, comprises a watchdog circuit for watching the operation of the control portion; and a conditioning circuit for defining a condition for starting the watchdog circuit; the conditioning circuit being constituted by an OR circuit for performing the logical sum OR among at least two signal inputs from the input portions and a signal input indicating the fact that the control portion is operating.

Abstract: A processor (21) monitors a data network (10) to proactively detect customer connectivity troubles by actively monitoring each router (181 and 182) to determine new and missing route destinations, Border Gateway Protocol (BGP) sessions and Open Shortest Path First (OSPF) adjacencies, by execution of three sub-routines rtchk(22), bgpchk (24) and ospfchk (26), respectively. Upon detecting a new or missing route destination, BGP session or OSPF adjacency, the processor alerts those responsible for maintaining the network of such an error.

Abstract: A method and apparatus are provided for detecting virtual address parity error for a translation lookaside buffer in a computer system. The computer system includes a processor unit, a cache coupled to the processor unit, a main memory, and a storage control unit including a translation lookaside buffer (TLB) and a segment lookaside buffer (SLB). A virtual address parity (VAP) is generated for each entry written in the segment lookaside buffer (SLB). A virtual address parity (VAP) is generated for each virtual address entry written in the translation lookaside buffer (TLB). The SLB virtual address parity (VAP) and the TLB virtual address parity (VAP) are utilized for identifying a translation miss condition.

Abstract: A selectively called radio receiver is arranged by a receiving unit for receiving a radio selection signal, an operation unit for accepting an operation, a storage unit for storing a control program, and a processing unit for processing the reception information derived from the receiving unit and the operation information outputted from the operation unit in accordance with the control program stored in the storage unit. This selectively called radio receiver is further arranged by a notifying unit for producing notification information based on the processing information outputted from the processing unit, and a monitoring unit for monitoring an access condition by the processing unit to the storage unit. Even when the processing unit is erroneously operated, increasing of power consumption can be suppressed, and the reliability of this selectively called radio receiver can be improved.

Abstract: A memory system constructed in accordance with the invention receives data blocks and associated host LBAs from a host processor. The memory subsystem initially associates a check value with each received data block, each check value dependent upon a host LBA that is associated with the respectively received data block. The memory subsystem stores each received data block and associated check value as an "extended" data block. Thereafter, the memory subsystem, in response to a host processor request to access data corresponding to the associated host LBA, recovers the stored extended data block and determines from the check value stored therewith, if the address of the corresponding data and that provided by the host processor correspond. If the addresses correspond, the data block is transmitted to the host processor. If not, an error message is generated.

Abstract: A shared memory controller prevents a memory area in a shared memory from becoming unusable even if an error occurs in an address for performing read/write operations. Under the control of a write control unit, each time N units of data and an address indicative of a storage location next to this data is written into the shared memory, one of the written addresses is stored in a second memory provided separately from the shared memory. Each time N addresses are read from the shared memory, an address stored in the second memory is read to detect in a detector whether or not the address is erroneous. If an error is detected, the erroneous address is discarded.

Abstract: A register access controller prevents the occurrence of a live-lock condition when an electronic device specifies a register for access from a plurality of registers. The register access controller uses a partial spectrum address decoder instead of a full spectrum address decoder for decoding a register address specifying an implemented register to utilize the advantages of a smaller and simpler decoding circuitry and a faster response of a partial spectrum address decoder. The register access controller also monitors when the specified register address does not correspond to any of the implemented registers to provide a proper response to the electronic device in order to prevent a live-lock condition.

Abstract: A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.

Abstract: A new method and apparatus are used to check for segment limit violations during memory access. When a segment descriptor is retrieved during the initialization of a segment, the segment limit from the segment descriptor is used to create five limits. The five limits are the last possible address within the segment for each size of memory access. During a subsequent memory access, the limit corresponding to the segment being accessed and the length of memory access is selected. The selected limit is compared against the address of the memory access to determine if a limit violation has occurred. If a limit violation has occurred, a flag is set that, when read, will cause an exception.

Abstract: A method, apparatus, and computer program product are provided for processing an invalid address request in a computer system. A processor in the computer system receives an address requested from software and compares a real address requested with a real address range available. An invalid address request is a real address requested outside the real address range available. Responsive to identifying an invalid address, the processor issues an interrupt to supervising software. Then an address exception is posted to the user software, if appropriate.

Abstract: The invention modifies an executing instance (target process) of an arbitrary computer program by replacing the heap manager in the target process. All functions in the process that manipulate dynamic memory are patched with replacement functions that implement improved heap management. The invention is applicable to any computer program that makes use of dynamic (heap) memory. In a second aspect of the invention, the improved heap implementation performs heap error checking in addition to managing heap storage. Alternative embodiments use the invention to improve performance (speed) using fast allocation algorithms, improve space efficiency of the program, or implement tracing of heap activity for debugging purposes.

Abstract: A method of data transfer in a data processing system having at least one source buffer and at least one destination buffer. The source buffer includes a plurality of data blocks, each data block having an address and being for storage of data including an identifier uniquely identifying that data block. The destination buffer includes a plurality of data blocks corresponding to the data blocks of the source buffer, each destination block having an address and being for storage of data. Each source block identifier is a function of a corresponding destination block address.

Abstract: A method and a device for determining that digital information written into a memory is correctly readable before such read information, in the form of a number of coordinated bit positions, is used to control one or several functions, where the functions can be activated by a computer unit. A selected address position or positions within the memory corresponding to the stored digital information points out a first set of bits, required to control and/or initiate the functions, and a second set of bits serving as a control sum. The second set of bits is calculated taking into consideration the current set of bits corresponding to the first set of bits and a third set of bits, corresponding to the address position currently selected for readout.

Abstract: An addressable memory having: a buffer memory adapted for coupling to a bus; a random access memory coupled to the buffer memory; an internal clock; and, a logic network, coupled to the bus and configured to transferring data among the buffer memory, the random access memory and the bus in response to clock signals produced by the internal clock and clock pulses provided on the bus. In a preferred embodiment, the buffer memory includes a first-in/first out (FIFO). A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes: a bus; a controller; and, an addressable memory. The controller and addressable memories are interconnected through the bus. The addressable memory includes a master memory unit and a slave memory unit.

Abstract: A diagnostic subsystem is used in a digital device in a digital computer system includes a diagnostic register, a device output control circuit and a diagnostic register reset circuit. The diagnostic register includes a plurality of stages each of which is associated with one of the types of transfers over the bus. Each stage is selectively conditionable by the digital computer system's processor. The device output control circuit controls transfers by the digital device over the bus. The device output control circuit enables the digital device, when it is to engage in a transfer, to transfer information correctly when the associated stage is set and to transfer information incorrectly when the stage has the set condition. For transfers in which the one device is to transmit information over the bus, the incorrectly transmitted information causes error checking circuitry in other devices in the system to generate error indications, which are provided to the processor.