Abstract: In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.

Abstract: A fuse disposing circuit executes a same test as in a state before a fuse is cut, even in case the fuse is cut. For this, the fuse disposing circuit in accordance with the invention includes a test mode enable confirmation section for informing whether a test mode is enabled; and a fuse set for providing a constant signal by using the output from the test mode enable confirmation section in case of the test mode, regardless of elimination or non-elimination of a fuse.

Abstract: Automatic test equipment including a digital test instrument that may test for and respond to over-voltage conditions. Information on over-voltage conditions may be used in detecting or diagnosing fault conditions within a system under test. Over-voltage conditions may be monitored as part of a test to determine the time and the channels on which they occur. A test may fail if an over-voltage condition is detected and the results of the test may indicate when and where the over-voltage condition occurred. Alternatively, indications of over-voltage conditions may be used to alter the test environment. In response to an over-voltage condition, units under test may be disconnected from the test environment to avoid exposing circuitry within those units to voltage levels that may damage or stress components. Alternatively, indications of an over-voltage condition may be used to disconnect from the test environment equipment that may be generating the over-voltage conditions.

Abstract: An automatic safety test system, which comprises a control interface of a control unit for controlling the switching of a switch in a server unit and automatically switching to a specified testing point of an electronic product, and connects a bus interface of the control unit to a plurality of testing instruments for sending the values measured by the testing instrument at the specified testing point to a communication interface record of the control unit through the bus interface. Therefore, the automatic safety test system of the invention can automatically test every specific safety testing item at each testing point of the electronic product, and thus further achieves the objectives of saving time, manpower and resources.

Abstract: The invention relates to a protective system for an installation, in particular for a gas-turbine installation, in which all the fail-safe protective circuits with reaction time requirements of greater than 50 milliseconds are routed via a more fail-safe programmable logic automation system. For all the other protective circuits with reaction time requirements of less than 50 milliseconds, fail-safe control relays are connected in a configuration which is tolerant to single faults, in which the automation system can check the operation of the control relay circuit cyclically during operation of the installation.

Abstract: Provided is a CAN system that can generate an error signal without requiring hardware for generating an error signal to be connected to a bus. A protocol processing part within a CAN controller incorporates error data into receive data or send data, based on error data information stored in a register.

Abstract: Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are simultaneously read from the first and second regular cell arrays. A main parity generation circuit generates according to sub parity data parity data in common to the regular cell arrays, is not disposed in a distributed manner but disposed corresponding to the parity cell array. Thus, the layout design, layout verification, and so forth of a semiconductor memory can be prevented from being complexed. As a result, the parity generation circuit can be optimally laid out, decreasing the development time and defect analysis time for the semiconductor memory can be decreased.

Abstract: A circuit design program product to cause a computer to execute a circuit design process based on a test point insertion, includes: a step for making reference to a netlist to extract a plurality of equivalent faults fj; a step for searching a number n(fj) of test point required for a number of the equivalent fault keeping equivalent relation with a search object equivalent fault fj with each of a plurality of equivalent faults as the search object equivalent fault to become a predetermined number and a insertion position G(fj); a step for calculating probability p(fj) of a single stuck-at fault being included in a set of equivalent faults including at least a search object equivalent fault fj at an occasion when the relevant stuck-at fault takes place in the circuit; a step for calculating a parameter e(fj) derived by an equation: e(fj)=p(fj)/n(fj) on each pattern of an insertion position G(fj); and a step for determining the insertion position G(fmax) giving the maximum value among the calculated parameters

Abstract: A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test. The receiver capable of executing control so as to make a phase of the input data coincide with that of a recovery clock.

Abstract: A skew adjustment circuit employs a novel algorithm enabling a reduction in scale of the circuit of a receiver for a Transition Minimized Differential Signaling (T.M.D.S.) link in accordance with the Digital Visual Interface (DVI) standard. The skew adjustment circuit includes a sampling point selection section that performs comparison processing on oversampled data, assumes transition points of serial data, and outputs a sampling point selection signal; and a data recovery section that outputs oversampled data at the sampling point selected by the selection signal, as sample data for the serial data. Comparison processing is performed on the oversampled data in 4-bit segment units of the serial data, transition point detection signals are held, and the transition points of the serial data are assumed based on those transition point detection signals, when transition point detection signals for at least two segments, which are among the held transition point detection signals, indicate the same result.

Abstract: During a first data compression test mode which disables an error correction function, first test data are written to a first regular memory block. Second test data are written to not only a second regular memory block, but a parity memory block. By changing the number of bits distributed to the first and second test data (compression rate of data), a data compression test for a parity memory block can be performed without need to increase the number of test terminals. As a result, the test time can be decreased and the test cost can be decreased.

Abstract: A method and apparatus for automatically debugging and optimizing an in-circuit test that is used to test a device under test on an automated tester is presented. The novel test debug and optimization technique extracts expert knowledge contained in a knowledge framework and automates the formulation of a valid stable, and preferably optimized, test for execution on an integrated circuit tester.

Abstract: Methods and apparatus are provided to insert errors into digital data. The errors can be inserted into the data itself, or into the corresponding error correcting code bits. The invention comprises a register, whose contents are combined with data using exclusive-OR circuitry. By varying the contents of that register, an error can be inserted into a specific bit in a particular data word, or into multiple bits in the same word.

Abstract: Systems and methods configured to guide and manage laboratory analytical process control operations. A Biometric quality control (QC) process application is configured to monitor bias and imprecision for each test, characterize patient population data distributions and compare, contrast, and correlate changes in patient data distributions to any change in QC data populations. The Biometric QC process monitors the analytical process using data collected from repetitive testing of quality control materials and patient data (test results). The QC process identifies the optimal combination of, for example, frequency of QC testing, number of QCs tested, and QC rules applied in order to minimize the expected number of unacceptable patient results produced due to any out-of-control error condition that might occur.

Abstract: Methods, apparatuses, and systems for encoding information symbols comprising loading information symbols into a data array with n(1) rows and n(2) columns, wherein each column has ki(1) information symbols, and wherein k(1) is an array that has at least two different values, encoding each column with a code Ci(1) from a family of nested codes C(1), wherein C(1) includes two different nested codes, and encoding each row with a code C(2).

Abstract: A method of generating a test data pattern for testing a CRC algorithm, the CRC algorithm configured to generate CRC values based on a generator polynomial, the method including identifying a desired pattern of intermediate CRC values. The method includes generating a test data pattern based on the desired pattern of intermediate CRC values and the generator polynomial, wherein the test data pattern is configured to cause the CRC algorithm to generate the desired pattern of intermediate CRC values.

Abstract: Errors in data retrieved from a storage medium are corrected by retrieving a plurality of data blocks and a plurality of redundancy blocks associated with the plurality of data blocks from the storage medium. One or more data blocks retrieved from the storage medium having errors are identified and removed. When the number of data blocks identified as having errors is less than the number of retrieved redundancy blocks, one or more excess redundancy blocks are removed, and one or more retained redundancy blocks are kept from the retrieved redundancy blocks. One or more new redundancy blocks are generated based on the retrieved data blocks. One or more residual blocks are generated based on the one or more new redundancy blocks and the one or more retained redundancy blocks. One or more data blocks identified as having errors are corrected using the generated one or more residual blocks.

Abstract: A test-device for testing an electric circuit comprises a data stream generator for generating a first data stream to be fed to an electric circuit which generates a second data stream in response to the first data stream and a comparison-device for comparing two data streams. The test-device comprises further a self-test device configured to generate a third data stream used to test the comparison-device. The test-device is further configured to operate in a first operation mode and in a second operation mode. The comparison-device is configured to compare the first data stream with the second data stream during the first operation mode and is configured to compare the first data stream with the third data stream during the second operation mode.

Abstract: In one embodiment, an apparatus is provided with a system circuit, a scanout circuit and an error detecting circuit. The system circuit is adapted to generate a first output signal in response to a data input signal and a system clock signal. The scanout circuit is adapted to generate a second output signal in response the data input signal and the system clock signal. The error detecting circuit, coupled to the system circuit and the scanout circuit, is adapted to generate an error signal in response to a relative condition between the first output signal and the second output signal.

Abstract: Generating a protected content stream from a data stream provides enhanced security in short-range wireless communications networks. This protected content stream is transmitted across a first short-range communications link. In addition, information for converting the protected content stream into the data stream is transmitted across a second link. The first link may be an ultra wideband (UWB) link, while the second link may be a Bluetooth link.

Abstract: A semiconductor device in which at least one bit of data bits configuring data read out from a memory is supplied to a pseudo error generating circuit in a test mode to generate a pseudo error bit which is supplied to an ECC (error connection code) circuit together with remainder bits of the data bits to obtain an error-corrected data which is then supplied to a BIST (Built-In-Self-Test) circuit for testing the error-corrected data obtained from the ECC circuit.

Abstract: A test circuit for a content addressable memory (CAM) match detection circuit that permits testing of the margin of the match detection circuit. By applying various loads to the matchline and/or the discharge line, the match detection circuit demonstrates whether it can overcome the applied loads.

Abstract: A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other storage device for storing data blocks, wherein the memory or storage device is adapted to output a plurality of data blocks in parallel. A data bus provides a data path wide enough to accommodate the parallel data blocks and is further coupled to a plurality of CRC cores coupled to the data bus, wherein CRC values are calculated for every combination of data blocks on the data bus. A multiplexer coupled to the CRC cores selects the output of one of the CRC cores based on the number of valid data blocks on the data bus. Once the correct CRC value has been calculated, it is appended to a data segment, comprised of a group of data blocks, for transmission to another device.

Abstract: A microchip system comprises a self check subsystem operable to perform a self test of at least one subsystem of the microchip system, and/or on the interoperability of subsystems. An antenna and a communications subsystem wirelessly transmit self check information from the microchip system. The communications subsystem may also receive information, data or instructions from an off-chip system or device. Self check tests may occur during manufacture of the microchip system and/or during operation. The microchip system may comprise a passive power subsystem coupled to an antenna to receive power in the form of an electromagnetic field, and which provides electrical power derived therefrom to at least one other subsystem of the microchip system.

Abstract: A technique is provided for designing and evaluating service models for components, functions, subsystems and field replaceable units in a complex machine system. At a component or item level, each model identifies various items, failure modes, and so forth which may be the root cause of anticipated serviceable events or faults. The design tools permit numerous interfaces to be used in the design of service models, and in the evaluation of the degree to which the models address detectability and isolation capabilities for the root causes of serviceable events and faults.

Abstract: The performance of a serial data transceiver in a programmable logic device may be determined by applying a stress sequence of sequential data to a receiver of the transceiver, comparing the received data to reference data and determining the number of errors.

Abstract: A decoding method and an apparatus operate by performing error correction on code words of an error correcting code block in one direction selected from a row direction and a column direction, indicating in error flags the remaining code words except at least some code words from code words having uncorrectable errors, and performing error correction on code words in the other direction based on the error flags. Accordingly, errors that have been conventionally considered as being uncorrectable may now be corrected.

Abstract: A high-speed parallel interface for communicating data between integrated circuits is disclosed. In one embodiment, the transmitter controller accepts 40-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 40-bit wide data every 167 Mhz clock cycle, and the interconnect bus transmits 10-bit wide data at every transition of a 333 Mhz clock cycle. In another embodiment, the transmitter controller accepts 32-bit wide data every 167 Mhz clock cycle, the receiver controller delivers 32-bit wide data every 167 Mhz clock cycle, and the interconnect bus of this embodiment transmits 8-bit wide data at every transition of a 333 Mhz clock cycle. Output pins of the transmitter interface can be connected to any input pins of the receiver interface. Furthermore, the high-speed parallel interface does not require a fixed phase relationship between the receiver's internal clock(s) and the bus clock signal.

Abstract: Test circuitry for supporting real-time testing of data exception software may be included on an integrated circuit. The circuitry supports the identification of a data unit or data group other than a next data unit or data group to be transferred in a data sequence and the generation of an erroneous data verification parameter that does not verify the data content of the identified data unit or data group. The identified data unit or group is later transmitted with the erroneous data verification parameter in real-time following the transmission of other data units and/or data groups having valid data verification parameters. In this manner, a data receiver may be tested to verify the detection of a data content error in real-time and the execution of the software or firmware for processing an exception may be verified. Circuitry for implementing the method of the present invention may be included on the substrate of an integrated circuit.

Abstract: A multithread auto test method is disclosed for the test process of computer hardware. According to the exclusion relation among the unique IDs of the test items, a multithread executable logic is automatically generated. An appropriate parallel method is employed to find procedures for test items that do not have conflictions. Therefore, multithreads of test procedures are performed to increase the test efficiency and quality. The method includes the steps of: determining a unique ID of a test item; automatically generating a test logic table according to the exclusion relation among the unique IDs; and performing multithread test procedure according to the test logic given in the test logic table.

Abstract: The present invention relates to a method and system for testing error detection programs dedicated for detecting hardware failures in a computer system, in which error case patterns comprising stimuli values are generated and response patterns to the hardware are evaluated. In order to develop and debug such error detection programs already at an early phase during hardware development it is proposed to feed a simulation model (26) of said hardware with said error patterns, and after running said model, evaluating (12) the model response patterns generated by the simulation model and comparing the response patterns with those expected as a result of the error detection program.

Abstract: A first unit successively transmits data blocks destined for a second unit. For at least some of the transmissions of blocks, the second unit returns an acknowledgement signal indicating whether the data block transmitted has been correctly received. The first unit transmits a redundancy block with regard to a block previously transmitted for which the acknowledgement signal received indicates incorrect reception. Each block transmitted is accompanied by an identification signal indicating whether it is a redundancy block. The first unit associates each acknowledgement signal received with a block transmitted in a temporal relation determined with the reception of this acknowledgement signal. In response to the reception of an identification signal inconsistent with an acknowledgement signal previously returned, the second unit returns to the first unit a restart command signal for the transmission of the blocks.

Abstract: The invention comprises, in various embodiments, a method for monitoring an internal test on a remote computer. The method includes reading a line from the remote computer with a processing unit. The line is capable of sending at least one result signal for the test. The method includes sending a fail signal from the processing unit to a reporting device when none of the new result signals are read during any time period of a preselected length.

Abstract: A method of generating a truncated scan test pattern for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) estimating a number of transition delay fault test patterns and a corresponding number of top-off stuck-at fault patterns to achieve maximum stuck-at fault and transition delay fault coverage; (c) truncating the estimated number of transition delay fault patterns to generate a truncated set of transition delay fault patterns so that the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns achieve maximum stuck-at fault and transition delay fault coverage within a selected scan memory limit; and (d) generating as output the truncated set of transition delay fault patterns and the corresponding number of top-off stuck-at fault patterns.

Abstract: An electronic test system that distinguishes erroneous and marginal results. The test system includes a memory and an electronic processor for controlling the execution of the test, obtaining test results and generating test results. The test results include a determination of whether the condition of the test datapoints is pass, fail, error or marginal, where pass indicates that the DUT has met a specification, fail indicates that the DUT has not met the specification, error indicates that the test system or interface to the DUT has failed, and marginal indicates that the system is marginally within specification. The test results are displayed on a graphical user interface. The test system provides the ability to control the progress of the test system based on the results. For example, the system can be programmed to stop on erroneous results, marginal results, failed results, combinations of the forgoing, or stop after each measurement.

Abstract: An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.

Abstract: System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.

Abstract: A method of testing error correction/detection logic may involve providing each of a set of n data bit combinations to the error correction/detection logic. Each data bit combination has n bits, and the n data bit combinations may be created by creating an initial data bit combination whose data bits have the same logical value and then shifting a bit having the opposite value across the initial data bit combination. In response to being provided with the n data bit combinations, the error correction/detection logic generates a set of check bits for each of the n data bit combinations. The set of check bits generated by the error correction/detection logic for each of the n data bit combinations may then be verified.

Abstract: A test-program generator capable of implementing a methodology, based on a formal language, for scheduling system-level transactions in generated test programs. A system to be tested may be composed of multiple processors, busses, bus-bridges, shared memories, etc. The scheduling methodology is based on an exploration of scheduling abilities in a hardware system and features a Hierarchical Scheduling Language for specifying transactions and their ordering. Through a grouping hierarchy, which may also be expressed in the form of an equivalent tree, the Hierarchical Scheduling Language combines the ability to stress related logical areas of the system with the possibility of applying high-level scheduling requests. A method for generating testcases based on request-files written in the Hierarchical Scheduling Language is also presented.

Abstract: The present invention provides an access control device and a testing method that can simplify the software operations in an access control operation such as a JTAG control operation, and enable the hardware to perform a high-speed control operation. The access control device conducts a test or diagnosis on an object by accessing a serial interface based on a command and data that specify a testing or diagnosing route. Under the control of a processor, a control circuit in the access control device executes an access sequence in accordance with a command string and an input data string stored in a memory, and stores the data outputted from the object to be tested or diagnosed in the memory as an output data string. The control circuit sets a state transition route for each objective state in advance, so that a transition route can be readily determined for an objective state specified by the command string.

Abstract: A semiconductor apparatus is composed of a signal providing circuit and a data analyzer. The signal providing circuit provides an input signal set including at least one input signal. The data analyzer outputs a digital result signal in synchronization with a clock signal. The data analyzer inverts the digital result signal at a timing indicated by the clock signal while the input signal set is in a predetermined state, and does not invert the digital result signal while the input signal set is not in the predetermined state.

Abstract: A system for validating error detection logic in a system. The system includes a plurality of information paths, each one of such paths having associated therewith an error detection logic, each one of the paths having a plurality of information bits. A test word buffer is provided for receiving a test word, such test word indicating a particular one of the plurality of information bits in a particular one of the information paths to be corrupted. The system includes a plurality of fault injectors responsive to the test word received by the buffer. Each one of the fault injectors is disposed in a corresponding one of the information paths prior to the associated the error detection logic. Each one of such fault injectors corrupts a selected one of the information bits in the corresponding one of the information paths in response to the test word received by the buffer to test whether the associated error detection logic detects such injected fault.

Abstract: A method and system for checking the Cyclic Redundancy Cycle (CRC) of DATA, such DATA comprising a series of data words terminating in a CRC portion. The method includes: checking the CRC of the data words while delaying the DATA from passing to an output; and corrupting the delayed DATA if such checking determines a CRC error, such corruption of the DATA being performed prior to the data words pass to said output. The corrupting comprises corrupting a parity byte of such data words.

Abstract: A method evaluates and optimizes an error-correcting code to be transmitted through a noisy channel and to be decoded by an iterative message-passing decoder. The error-correcting code is represented by a parity check matrix which is modeled as a bipartite graph having variable nodes and check nodes. A set of message passing rules is provided for the decoder. The decoder is analyzed to obtain a set of density evolution rules including operators and operands which are then transformed to projective operators and projected operands to generate a set of projective message passing rules. The projective message passing rules are applied iteratively to the error-correcting code modeled by the bipartite graph until a termination condition is reached. Error rates of selected bits of the error-correcting code are then determined by evaluating the corresponding operands. The error rates can be passed to an optimizer to optimize the error-correcting code.

Abstract: In one embodiment, the present invention is directed to a method for inserting errors into data to facilitate validation of an error detection algorithm. The method comprises: receiving a data corruption command for a plurality of bits; determining, from the data corruption command, a plurality of bit fields within the plurality of bits for data corruption; determining a minimum and maximum number of errors for each of the plurality of bit fields; determining a total number of errors to be inserted; inserting the minimum number of errors into each of the plurality of bit fields at random locations; and randomly inserting additional errors into the plurality of bit fields subject to the maximum number of errors until the total number of errors are inserted.

Abstract: A system and method for testing and maintaining a predetermined bit rate on a line connection between a transmission assembly and at least one terminal, where initiation of a drop below the predetermined bit rate triggers at least one corrective measure for increasing the bit rate.

Abstract: A method and an apparatus verifies the correctness of the error correcting code algorithm and the correctness of the error correcting code implementation. An error injection module is used to inject random errors into an ECC circuit between an encoder and a decoder. The encoder encodes data bits with check bits to produce an encoded signal. A decoder decodes the encoded signal, after modification by the error injection module. The output of the decoder may be a zero error signal, a signal error signal, a multiple error signal, and an error location signal. The output signal is compared to expected values to determine if an error exists in the ECC or the ECC circuit.

Abstract: A system for testing middleware of applications in the N-tiered model. The test system contains test code generators, test engines to execute multiple copies of the test code and a data analyzer to analyze and present the results to a human user. The system is able to automatically generate test code to exercise components of the middleware using information about these components that would otherwise be available to the application under test. Multiple copies of the test code are executed in a synchronized fashion. Execution times of multiple events are recorded and then presented in one of several formats. With the system, an application developer can identify components that represent performance bottlenecks or can gather information on deployment properties of individual components that can be used to enhance the performance of the application under test.

Abstract: A method and apparatus for generating a CRC/parity error in network environment. A SCSI bus expander such as an Ultra320 bus expander or the like is added between a sending device and a receiving device. The sending device-receiving device pair may execute a training session to determine the skew compensation. During the training session, the SCSI bus expander may figure out timing differences due to skew and adjusts the timing of each data signal to compensate for skew. For each data signal, a compensated time may be obtained. The compensated time may then be modified through a JTAG port of the SCSI bus expander. The compensated times may be adjusted such that a CRC/parity error is generated on every I/O or just some I/Os to the receiving device. By intentionally generating a CRC/parity error, the response of the devices in the SCSI environment to a CRC/parity error may be evaluated during an input/output (I/O) test.

Abstract: A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter (11), a carrier of the counter (11) stores outputs from a PN data generator (21) in a shift register (22), outputs from a PN comparison circuit (3) when stored data agree with count values of the counter (11) are recognized as error pulses, a bit selector (40) randomly selects, on receiving error pulses and based on outputs from a PN data generator (41), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit (5) for outputting to thereby add errors.