Error Count Or Rate Patents (Class 714/704)
  • Patent number: 11523186
    Abstract: According to one implementation, an automated audio mapping system includes a computing platform having a hardware processor and a system memory storing an audio mapping software code including an artificial neural network (ANN) trained to identify multiple different audio content types. The hardware processor is configured to execute the audio mapping software code to receive content including multiple audio tracks, and to identify, without using the ANN, a first music track and a second music track of the multiple audio tracks. The hardware processor is further configured to execute the audio mapping software code to identify, using the ANN, the audio content type of each of the multiple audio tracks except the first music track and the second music track, and to output a mapped content file including the multiple audio tracks each assigned to a respective one predetermined audio channel based on its identified audio content type.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: December 6, 2022
    Assignee: Disney Enterprises, Inc.
    Inventors: Miquel Angel Farre Guiu, Marc Junyent Martin, Albert Aparicio Isarn, Avner Swerdlow, Anthony M. Accardo, Bradley Drew Anderson
  • Patent number: 11516725
    Abstract: To speed up a firmware update process, a gateway performs an expedited topological discovery of networked nodes. The gateway maintains a list of unlinked network nodes that are not known to share good edges with other nodes. The gateway transmits a topology query to a selected unlinked node, which the node retransmits to its neighboring nodes. Each neighboring node responds to the gateway with a link status of the edge between the queried node and the neighbor. The queried node and each neighboring node with an edge of sufficient link quality are removed from the list of unlinked nodes. The process is repeated until no networked nodes remain in the list of unlinked nodes. The gateway then sends a firmware update to nodes that will in turn retransmit the update over identified good edges.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: November 29, 2022
    Assignee: Synapse Wireless, Inc.
    Inventor: Jon Martin
  • Patent number: 11500742
    Abstract: An electronic apparatus is provided.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hodong Lee, Kwanghyun Koh, Kiyoung Yang
  • Patent number: 11494258
    Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Programmable thresholds may be configured for a memory device based on a type of data or a location of stored data, among other aspects. For example, a host device may configure a threshold quantity of errors for data at a memory device. When retrieving the data, the memory device may track or count errors in the data and determine whether the threshold has been satisfied. The memory device may transmit (e.g., to the host device) an indication whether the threshold has been satisfied, and the system may perform functions to correct the errors and/or prevent further errors. The memory device may also identify errors in received commands or may identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Michael Dieter Richter, Thomas Hein, Wolfgang Anton Spirkl, Martin Brox, Peter Mayer
  • Patent number: 11495296
    Abstract: A storage apparatus includes non-volatile memory cells formed on a memory die, each memory cell configured to hold bits of data, and a control circuit. The control circuit is configured to calculate parity data for data to be stored in the memory cells and program the memory cells to first distributions. The control circuit is also configured to read memory cells in the first distributions, recover the data from results of reading the memory cells in the first distributions combined with the parity data, and further program the memory cells from the first distributions to second distributions to store the data. To improve the accuracy of recovering the encoded foggy phase data, techniques are presented to calibrate the voltage levels used in sensing the foggy state distributions.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: November 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Idan Alrod, Eran Sharon, Sergey Anatolievich Gorobets, Jack Frayer, Tien-Chien Kuo, Alexander Bazarsky
  • Patent number: 11494261
    Abstract: A method of temperature compensation to read a flash memory device includes determining a state of the flash memory device. An action is selected with a maximum Q-value from a Q-table for the current state during exploitation. A read operation of a code word from the flash memory device is conducted using one or more parameters according to the selected action. The code word is decoded with an error correction code (ECC) process.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: November 8, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Stella Achtenberg, Ran Zamir, Ofir Pele, Omer Fainzilber
  • Patent number: 11483472
    Abstract: A computer-implemented method, a computer system and a computer program product enhance multimedia quality. The method includes receiving a plurality of sequential frames of a scene in a video. The method also includes generating dataframes for current frames and for a reference frame of the video. The method further includes comparing the dataframes for the reference and current frames. In addition, the method includes determining a quality metric of the current frames based on the comparison of the dataframes for the reference and current frames. The method also includes determining if the quality metric can be improved by altering the video in response to determining that the quality metric of one of the current frames is below a threshold. Finally, the method includes inserting expansion frames into the video in response to determining that the quality metric can be improved by altering the video.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: October 25, 2022
    Assignee: International Business Machines Corporation
    Inventors: Paul R. Bastide, Robert E. Loredo, Matthew E. Broomhall
  • Patent number: 11475008
    Abstract: Disclosed are systems and methods for monitoring user-defined metrics. A method may include: receiving, from a user device, a metric definition usable to generate queries to obtain data for a metric to be monitored; receiving, from the user device, a monitoring configuration indicative of a manner in which a metric monitoring process associated with the metric definition is to be repeatedly performed; storing the metric definition in a metric definition database; and repeatedly performing the metric monitoring process in accordance with the monitoring configuration. The metric monitoring process may include: retrieving the metric definition from the metric definition database; generating a database query based on the metric definition, the database query including one or more executable database statements defined by the metric definition; executing the database query to obtain query result data, the query result data being data for the metric; and storing the query result data.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: October 18, 2022
    Assignee: Capital One Services, LLC
    Inventors: Koon Heng Ivan Teo, Qingyi Sui, Mohammad Shami, Yoonseong Kim, Fernando San Martin Jorquera, Francisco Perez Leon
  • Patent number: 11461171
    Abstract: The present technology relates to an electronic device. A memory system for increasing reliability of data includes a memory device including a plurality of pages, and a memory controller configured to correct an error in read data obtained by reading a selected page among the plurality of pages, and determine whether to perform a refresh operation on the selected page based on a number of error bits included in the read data. The memory controller comprises a normal read operation controller configured to control a read operation on the selected page and determine the number of error bits in the read data, an error correction performance component configured to correct the read data, and a data recovery controller configured to control the refresh operation on the selected page based on the number of error bits in the read data when the error in the read data is corrected.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: October 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Won Jae Choi, Se Chun Park
  • Patent number: 11454663
    Abstract: A signal processing method is provided. The signal processing method is used in a Gigabit Ethernet system including a device under test (DUT) and a link partner (LP), and includes the following steps. Firstly, an interference detector is configured to detect whether the Gigabit Ethernet system is interfered by other signal sources. Next, a physical layer (PHY) of the DUT or a PHY of the LP is used to, in response to the Gigabit Ethernet system being interfered by the other signal sources, set a request signal indicating whether or not the physical layer enters a low power idle (LPI) mode as FALSE. Which PHY of the DUT and the LP is used to set the request signal indicating whether or not the PHY enters the LPI mode as FALSE depends upon which one of the DUT and the LP is provided with the interference detector.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: September 27, 2022
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Chia-Min Li, Liang-Wei Huang
  • Patent number: 11437119
    Abstract: An apparatus includes an error read flow component resident on a memory sub-system. The error read flow component can cause performance of a plurality of read recovery operations on a group of memory cells that are programmed or read together, or both. The error read flow component can determine whether a particular read recovery operation invoking the group of memory cells was successful. The error read flow component can further cause a counter corresponding to each of the plurality of read recovery operations to be incremented in response to a determination that the particular read recovery operation invoking the group of memory cells was successful.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: September 6, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Seungjune Jeon
  • Patent number: 11415481
    Abstract: A line monitoring system may include a laser source to launch a probe signal over a first bandwidth, a polarization maintaining tap to receive and split the probe signal, into a first portion and a second portion, a polarization rotator to receive the first portion and send the first portion to a transmission system, a return tap to receive the second portion and to receive a return signal from the transmission system, wherein the return signal being derived from the first portion, a photodetector coupled to receive an interference signal from the return tap, wherein the interference signal is generated by a mixing the return signal and the second portion, where the photodetector is arranged to output a power signal based upon the interference signal, and a power measurement system to measure the power signal at a given measurement frequency over a second bandwidth, comparable to the first bandwidth.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 16, 2022
    Assignee: SUBCOM, LLC
    Inventor: Maxim A. Bolshtyansky
  • Patent number: 11398281
    Abstract: A semiconductor memory device, and a method of operating the same, includes a memory cell array and a peripheral circuit. The memory cell array includes memory cells, each storing N bits of data. The peripheral circuit performs a program operation on a physical page including selected memory cells. The peripheral circuit is configured to receive pieces of data of N logical pages and program the pieces of data of the N logical pages to the physical page based on a logic code. The logic code is determined to equalize numbers of sensing operations required to read the pieces of data of the N logical pages. Weak read levels are assigned, using the logic code, to read data of a logical page for which the number of sensing operations is smallest.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: July 26, 2022
    Assignee: SK hynix Inc.
    Inventor: Hee Youl Lee
  • Patent number: 11394753
    Abstract: Methods and computing systems for dynamic rate adaption during real-time Long Term Evolution (LTE) communication are described. A real-time LTE communication session with another mobile device is established over an LTE connection. The real-time LTE communication session is established with codec rate. A monitor component receives data indicating a performance of the real-time LTE communication session, and causes the real-time LTE communication component to perform, during the real-time LTE communication session, a renegotiation of the codec rate based at least on the performance of the real-time LTE communication session.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 19, 2022
    Assignee: T-Mobile USA, Inc.
    Inventors: Yasmin Karimli, Dinesh Arcot Kumar
  • Patent number: 11394489
    Abstract: Systems and methods are described herein that allow information carrying bits of a transmission block to be placed at higher-reliability positions prior to transmission. An exemplary method includes generating a set of payload bits to be encoded for transmission, wherein the set of payload bits includes at least one known bit, interleaving the set of payload bits to generate an interleaved set of payload bits, wherein the interleaved set includes the at least one known bit in a predetermined position in the interleaved set, providing the interleaved set to a cyclic redundancy check (CRC) encoder to generate CRC-interleaved set of payload bits, wherein the CRC-interleaved set includes the at least one known bit in a predetermined position within the CRC-interleaved set, and encoding the CRC-interleaved set for transmission to a wireless device. Associated network nodes and wireless devices are included.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: July 19, 2022
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Anders Wesslén, Dennis Hui, Yufei Blankenship
  • Patent number: 11379331
    Abstract: An error rate measuring apparatus includes an operation unit that sets one Codeword length and one FEC Symbol length of FEC according to a communication standard of a device under test W, a storage unit that stores symbol string data obtained by receiving and converting a signal from the device under test W, data division means for dividing the stored symbol string data into MSB data and LSB data, a data comparison unit that compares each of the divided MSB data and LSB data with error data to detect each of MSB errors and LSB errors of each one Codeword length, and detects FEC Symbol Errors of each of the MSB data and the LSB data at one FEC Symbol interval, and error counting means for counting the detected MSB errors, LSB errors, and FEC Symbol Errors.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: July 5, 2022
    Assignee: ANRITSU CORPORATION
    Inventor: Hiroyuki Onuma
  • Patent number: 11368504
    Abstract: A method for selecting a data stream for distribution to a plurality of broadcasting sites. The method includes: receiving a main data stream and a back-up data stream respectively, generated by a main broadcast gateway and a secondary broadcast gateway respectively, from source data, called a main stream and a secondary stream respectively; receiving at least one packet including a piece of information representative of a quality of service associated with the main stream and the secondary stream respectively, at one instant at least or over one given period at least, the at least one packet, called a main current packet and a secondary current packet respectively, being generated by the main broadcast gateway and secondary broadcast gateway respectively; and selecting in real time the main stream or the secondary stream respectively in taking account of the main current packet and secondary current packet, delivering the data stream for distribution.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: June 21, 2022
    Assignee: ENENSYS TECHNOLOGIES
    Inventors: Jean-Baptiste Marie, Benoit Bui Do, Alexis Gautier
  • Patent number: 11356351
    Abstract: A method and a coordinating node for providing at least one current analysis result relating to a link are disclosed. The coordinating node obtains a set of previous analysis results relating to at least one segment of the link. The coordinating node identifies a set of unreliable segments based on the set of previous analysis results and based on a condition for defining any segment as unreliable. The coordinating node performs a respective analysis of each unreliable segment of the set of unreliable segments to obtain a respective current analysis result for said each unreliable segment. Furthermore, the coordinating node sends, to the first node, the respective current analysis result. A corresponding computer program and a computer program carrier are also disclosed.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: June 7, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Athanasios Karapantelakis, Lackis Eleftheriadis, Rafia Inam
  • Patent number: 11347415
    Abstract: A selection device includes a multiplexer component, an input channel configured to couple at least the multiplexer to the memory sub-system controller, and a set of output channels coupled to the multiplexer component. Each of the set of output channels is further coupled to a respective memory device of a set of memory devices. Each of the set of output channels is configured to transmit data between the multiplexer component and the respective memory device. The selection device further includes a decoder component that is coupled to the input channel and each of the set of memory devices. The decoder component is configured to receive, from the memory sub-system controller via the input channel, a signal including a first signal portion configured to enable the decoder component and a second signal portion configured to identify a particular output channel of the set of output channels that is to transmit the data between the multiplexer component and the corresponding memory device.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Suresh Rajgopal, Henrico L. Yahja, Steven Eskildsen, Dustin J. Carter
  • Patent number: 11335425
    Abstract: A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system health threshold. Formulating the comparison to these metrics can include determining an area between a baseline frequency and a curve specified by the CDF-based data. In some implementations, this area can further be defined by a lowest frequency bound and/or can be compared as a ratio to an area of a rectangle that contains the CDF curve.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: May 17, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Bruce A. Liikanen, Gerald L. Cadloni, David Miller
  • Patent number: 11314580
    Abstract: An apparatus comprises a processing device configured to identify faults associated with a logical address space in a fault domain of a storage system, the faults specifying fault reason codes and metadata types for logical pages in the logical address space associated with the faults. The processing device is also configured to determine a fault summary characterizing impact of the faults in the fault domain of the storage system, the fault summary being based on aggregating fault scores assigned to the fault reason codes and the metadata types specified in the faults. The processing device is further configured to generate a recommendation on whether to initiate recovery of the fault domain of the storage system based on the fault summary, and to initiate recovery of the fault domain of the storage system based on the generated recommendation.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 26, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Rohit K. Chawla, Dixitkumar Vishnubhai Patel
  • Patent number: 11316771
    Abstract: Provided is a computer-readable storage medium storing a program causing a first information processing device connected to a second information processing device to execute a process, the process including receiving requests having timestamps added by the second information processing device, storing, as a first time, a first latency for which a cumulative frequency in a first frequency distribution, which is obtained by counting the requests for each latency, is equal to a threshold value, processing the requests received within the first time, discarding the request having a latency greater than the first time, and changing the first time to a second latency for which a cumulative frequency in a second frequency distribution different from the first frequency distribution is equal to the threshold value depending on whether a ratio of discarded requests is greater than a target value calculated by subtracting the threshold value from 1.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: April 26, 2022
    Assignee: FUJITSU LIMITED
    Inventor: Satoshi Iwata
  • Patent number: 11316715
    Abstract: A method for automatically identifying an impairment of a communication medium includes (1) obtaining a spectrum response of communication signals traveling through the communication medium, (2) converting the spectrum response from a frequency domain to a time domain, to generate an impulse response, and (3) identifying the impairment of the communication medium at least partially based on one or more characteristics of the impulse response.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: April 26, 2022
    Assignee: Cable Television Laboratories, Inc.
    Inventors: Jason W. Rupe, Thomas Holtzman Williams, Lin Cheng, Jingjie Zhu
  • Patent number: 11293983
    Abstract: Provided is a technique for achieving improvement of usability in setting parameters. An error rate measuring apparatus includes a display unit that displays input boxes for inputting one Codeword length and one FEC Symbol length of FEC on a setting screen, and an operation unit that inputs the one Codeword length and the one FEC Symbol length to the corresponding input boxes according to a communication standard of a device under test. A graphic of one Codeword, a graphic of one FEC Symbol, and a graphic of one Codeword including an error for identifying a configuration relationship of an FEC Symbol to a Codeword of the FEC and a correspondence relationship of an FEC Symbol Error to the Codeword are displayed on the setting screen corresponding to the input box of each of the one Codeword length and the one FEC Symbol length of the FEC.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: April 5, 2022
    Assignee: ANRITSU CORPORATION
    Inventor: Hiroyuki Onuma
  • Patent number: 11232464
    Abstract: Systems, apparatus, and methods for determining unique contacts from a collection or pool of merchant data are discussed herein. Some embodiments may provide for an apparatus including circuitry configured to determine programmatic match results indicating whether different instances of merchant data match (e.g., describe the same contact). The circuitry may further determine probabilities of precision or recall errors with the programmatic match results. Programmatic match results having a high probability of error may be annotated by a user to generate user match results. The user match results may be used to generate a more reliable contacts database including unique contacts, as well as to train and/or update the match scoring algorithm. As such, the accuracy of machine-implemented binary classification is improved.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: January 25, 2022
    Assignee: GROUPON, INC.
    Inventors: David Alan Johnston, Matthew Deland, Shawn Ryan Jeffrey, Taylor Raack
  • Patent number: 11216349
    Abstract: A variety of applications can include apparatus and/or methods to preemptively detect detect one memory blocks in a memory device and handle these memory blocks before they fail and trigger a data loss event. Metrics based on memory operations can be used to facilitate the examination of the memory blocks. One or more metrics associated with a memory operation on a block of memory can be tracked and a Z-score for each metric can be generated. In response to a comparison of a Z-score for a metric to a Z-score threshold for the metric, operations can be performed to control possible retirement of the memory block beginning with the comparison. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Harish Reddy Singidi, Vamsi Pavan Rayaprolu, Kishore Kumar Muchherla, Jianmin Huang, Xiangang Luo, Ashutosh Malshe
  • Patent number: 11216325
    Abstract: Embodiments of the present disclosure provide a method and apparatus for reducing cross talk among pins in a connector. The apparatus may detect a bit error rate (BER) for each of a plurality of pins in a connector and compare the BER for each pin to a threshold BER. Responsive to determining that a set of pins among the plurality of pins each have a BER that is above the threshold BER, the apparatus may decrease the BER for each pin in the set of pins by selecting a subset of pins among the plurality of pins and adjusting operational characteristics of one or more of the subset of pins. The operational characteristics include a transmit power of the pin.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 4, 2022
    Assignee: Arista Networks, Inc.
    Inventors: Ankush Dhar, Harold Wang, Prasad Venugopal, Arul Ramalingam
  • Patent number: 11209998
    Abstract: Embodiments of the present disclosure generally relate to storage devices, such as SSDs. A data storage device comprises an encrypted interface, one or more flash memory devices, and a controller configured to receive one or more workloads of data through the encrypted interface. Upon a threshold being met, the controller performs a diagnosis of one or more operating parameters of the one or more workloads of data. Based on the diagnosis, the data storage device is optimized by recalibrating one or more of: a partitioning of bits per cell of the one or more flash memory devices, one or more flash management parameters of the data storage device, and a programming rate of the storage device.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: December 28, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yuval Bahar, Avichay Haim Hodes, Alex Bazarsky
  • Patent number: 11200120
    Abstract: A system and method for configuring fault tolerance in nonvolatile memory (NVM) are operative to set a first threshold value, declare one or more portions of NVM invalid based on an error criterion, track the number of declared invalid NVM portions, determine if the tracked number exceeds the first threshold value, and if the tracked number exceeds the first threshold value, perform one or more remediation actions, such as issue a warning or prevent backup of volatile memory data in a hybrid memory system. In the event of backup failure, an extent of the backup can still be assessed by determining the amount of erased NVM that has remained erased after the backup, or by comparing a predicted backup end point with an actual endpoint.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 14, 2021
    Assignee: Netlist, Inc.
    Inventors: Scott H. Milton, Jeffrey C. Solomon, Kenneth S. Post
  • Patent number: 11182231
    Abstract: A memory system suitable for counting the number of errors occurring in each memory location, and a host system suitable for detecting a defective memory location based on the number of the errors occurring in each memory location and controlling a repair operation for the defective memory location based on a current amount of data being processed between the host system and the memory system, wherein the memory system repairs the defective memory location using the redundant memory area.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Eung-Bo Shim, Sung-Ki Choi
  • Patent number: 11157211
    Abstract: A memory system includes a memory device and a controller suitable for controlling the memory device based on read counts for a plurality of pages of the memory device, wherein the controller counts at least one of the read counts in response to a read request, determines whether there is a page whose read count is initialized at every check-pointing period to generate a determination result, and controls the memory device to update the read counts based on the determination result.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 26, 2021
    Assignee: SK hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 11150970
    Abstract: Techniques involve: in response to a number of errors of an error type in a storage disk increasing, determining an adjustment rate for a health value of the storage disk based on a total usage time length of the storage disk, where a longer total usage time length corresponds to a higher adjustment rate, and the health value indicates a health condition of the storage disk with respect to the error type. The techniques further involve increasing the adjustment rate based on a total input/output (I/O) number of the storage disk, where a greater total number of I/Os corresponds to a greater increment. The techniques further involve adjusting the health value with the adjustment rate. Such techniques can improve the accuracy of evaluating the health condition of the storage disk.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: October 19, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Chun Ma, Geng Han, Hongpo Gao, Jianbin Kang, Lifeng Yang
  • Patent number: 11150715
    Abstract: A parallel processor includes one or a plurality of digital signal processing (DSP) arithmetic unit(s) and one or a plurality of DSP appropriateness checking unit(s) corresponding to the DSP arithmetic unit(s). The DSP appropriateness checking unit includes a register and a determining unit. The register repeatedly receives an arithmetic result from the DSP arithmetic unit. The determining unit determines, when an arithmetic result has the same calculation value, that an arithmetic operation performed by the DSP arithmetic unit is completed and outputs the calculation value as a determinate arithmetic result.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: October 19, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Hitoshi Matsumori
  • Patent number: 11151240
    Abstract: A method of monitoring access requests to one or more access controls of an access control system is provided. The method comprising: receiving a first access request from a key card to a first access control, the key card being encoded with a credential and an access code; determining that the credential is not authorized to access the first access control; checking a first value of the access code; and rewriting the first value of the access code to a second value of the access code if the first value of the access code does not equal a desired value of failed access request attempts.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 19, 2021
    Assignee: CARRIER CORPORATION
    Inventor: Sumanth Kumar Mukundala
  • Patent number: 11138039
    Abstract: A memory system includes: a memory device that includes a plurality of ranks; and a memory controller suitable for deciding selection signals each of which selects one command set corresponding to each of combinations of the ranks and at least one program executed in the memory device among a plurality of command sets, and executing a program including the selected command set in the memory device.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Woong-Rae Kim
  • Patent number: 11138064
    Abstract: Methods, systems, and devices for error detection, error correction, and error management by memory devices are described. Error thresholds for a memory device are configurable based on parameters such as a type of data or a location of stored data. When retrieving the data, the memory device tracks or counts errors in the data and determines whether the error threshold has been satisfied. The memory device transmits (e.g., to a host device) an indication of whether the error threshold has been satisfied, and the system is configured to perform functions to correct the errors and/or prevent further errors. The memory device is also configured to identify errors in received commands or to identify errors introduced in data after the data was received (e.g., using an error detecting code associated with a command or bus).
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Michael Dieter Richter, Thomas Hein, Wolfgang Anton Spirkl, Martin Brox, Peter Mayer
  • Patent number: 11132244
    Abstract: A method includes determining a portion of a block of a storage device to read after programming, and reading the portion of the block and determining a maximum error count for the portion of the block. The maximum error count is compared to a threshold. When the maximum error count exceeds the threshold, a code rate of an error correction coding used to program the block is adjusted, or a code rate test is performed on the entire block.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: September 28, 2021
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Shuhei Tanakamaru, Scott McClure, Erich Franz Haratsch
  • Patent number: 11134456
    Abstract: A computer-implemented method for synchronizing wireless testing devices includes (a) in a protocol analyzer located in an RF-isolated test chamber, capturing first network packets transmitted to or from a wireless device-under-test (DUT) to generate protocol test data, (b) in the protocol analyzer, determining if any of the first network packets satisfy a trigger rule, (c) in the protocol analyzer, generating a trigger output signal when the trigger rule is satisfied, (d) sending the trigger output signal from the protocol analyzer to an RF analyzer in electrical communication with the DUT, (e) capturing second network packets with the RF analyzer based on the trigger output signal to generate RF test data, the second network packets transmitted to or from the DUT, and (f) in the protocol analyzer, time-aligning the first and second network packets in the protocol test data and the RF test data, respectively.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: September 28, 2021
    Assignee: Octoscope Inc.
    Inventors: Michael Haley, Andrew Stephen McGarry, Ron Cook
  • Patent number: 11133080
    Abstract: The present technology includes a memory device and a method of operating the same. The memory device in which an interface circuit and a semiconductor memory are packaged together includes a centrally located region in a ball mapping region of a memory device in which data input/output pins for an operation of the interface circuit and the semiconductor memory are disposed, and a test pin region in which test pins for a test operation of the interface circuit are disposed.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Kyun Park, Young Sik Koh, Seung Jin Park, Dong Hyun Lee
  • Patent number: 11122526
    Abstract: A method includes: obtaining, by a terminal, configuration information, wherein the configuration information comprises a maximum quantity of signal transmitting attempts corresponding to each coverage enhancement level; determining, by the terminal according to the obtained configuration information, a transmit power used for transmitting the signal at a coverage enhancement level currently used by the terminal; and transmitting the signal using the determined transmit power.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: September 14, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xiangdong Zhang, Jinhuan Xia
  • Patent number: 11100972
    Abstract: Methods, systems, and devices for refresh rate control for a memory device are described. For example, a memory array of a memory device may be refreshed according to a first set of refresh parameters, such as a refresh rate. The memory device may detect an event at the memory device associated with a reduction in data integrity. In some cases, the event may be associated with a temperature of the memory device, a voltage level detected at the memory device, an error event at the memory device, or the like. As a result of detecting the event, the memory device may adapt one or more of the set of refresh parameters, such as increasing the refresh rate for the memory array. In some cases, the memory device may adapt the set of refresh parameters by increasing a quantity of rows of the memory array that are refreshed during a refresh operation, decreasing a periodicity between refresh operations, or both.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: August 24, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Schaefer, Aaron P. Boehm
  • Patent number: 11101886
    Abstract: An optical network device with abnormal light emission detection includes an optical transceiver circuit and a control circuit. The optical transceiver circuit receives a transmission signal. The control circuit enables the optical transceiver circuit according to the transmission signal, so that the optical transceiver circuit outputs an optical signal. The optical transceiver circuit outputs a status signal according to whether or not the optical transceiver circuit outputs the optical signal. The status signal triggers an interrupt system of the control circuit. The interrupt system is provided with a counter to count a light emission duration of the optical transceiver circuit. When the light emission duration is greater than a preset value, the control circuit stops the optical transceiver circuit from outputting the optical signal.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: August 24, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Juan Liu, Lian Cheng, Hua-Zhen Tian, Jun Mao
  • Patent number: 11082741
    Abstract: In some embodiments, a method receives one or more segments for content from a first content delivery network during a playback session for the content. The content includes a number of segments. The method evaluates buffer occupancy of a buffer configured to store segments of the content for playback and evaluates a number of times of a failure to download a segment for the content. The buffer occupancy is compared to a first threshold and the number of times of the failure to a second threshold. The method determines a switch from the first content delivery network to a second content delivery network during the playback session based on the comparing.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 3, 2021
    Assignee: HULU, LLC
    Inventors: Lan Xie, Shenglan Huang, Wenhao Zhang, Deliang Fu, Shun Ni, Qiang She, Yanping Zhou, Yicheng Liu, Yuting Gui
  • Patent number: 11079952
    Abstract: A data storage device may include a storage including a plurality of memory blocks each composed of a plurality of pages and divided into a first region including some of the plurality of memory blocks and a second region including remaining memory blocks of the plurality of memory blocks; and a controller configured to control data input and output of the storage in response to a request of a host, determine whether to move data stored in a memory block of the first region by performing a first scan operation on the memory block of the first region, and determine whether to move data stored in at least one memory block of the second region by performing a second scan operation on the at least one memory block of the second region after the first scan operation is completed.
    Type: Grant
    Filed: October 3, 2019
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae Yeon Jang
  • Patent number: 11074126
    Abstract: An apparatus comprising a memory array including a plurality of memory cells arranged in a plurality of columns and a plurality of rows is provided. The apparatus further comprises circuitry configured to perform an error detection operation on the memory array to determine a raw count of detected errors, to compare the raw count of detected errors to a threshold value to determine an over-threshold amount, to scale the over-threshold amount according to a scaling algorithm to determine a scaled error count, and to store the scaled error count in a user-accessible storage location.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew A. Prather, Randall J. Rooney
  • Patent number: 11057051
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment may construct, for adjusted fractally enhanced kernel (FRANK) polar coding, encoding code for encoding data of an ultra-reliable low latency (URLLC) communication, wherein an information bit assignment to an information bit set associated with the encoding code is performed based at least in part on an adjusted dimensionality factor, wherein the encoding code is all-stage FRANK polar code or partial-stage FRANK polar code, and wherein the encoding code is constructed for code block shortening or code block puncturing. In some aspects, the user equipment may transmit the URLLC communication encoded using the encoding code based at least in part on the information bit assignment to the information bit set. Numerous other aspects are provided.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: July 6, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Ying Wang, Jing Jiang, Wei Yang, Gabi Sarkis, Jing Lei, Seyong Park
  • Patent number: 11016843
    Abstract: Methods, systems, and devices for operating memory cell(s) using a direct-input column redundancy scheme are described. A device that has read data from data planes may replace data from one of the planes with redundancy data from a data plane storing redundancy data. The device may then provide the redundancy data to an error correction circuit coupled with the data plane that stored the redundancy data. An output of the error correction circuit may be used to generate syndrome bits, which may be decoded by a syndrome decoder. The syndrome decoder may indicate whether a bit of the data should be corrected by selectively reacting to inputs based on the type of data to be corrected. For example, the syndrome decoder may react to a first set of inputs if the data bit to be corrected is a regular data bit, and react to a second set of inputs if the data bit to be corrected is a redundant data bit.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: May 25, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kiyoshi Nakai
  • Patent number: 11016841
    Abstract: The invention introduces a method for proactive error-correcting code (ECC) failure handling, at least including the following steps: obtaining a completion element (CE) from a completion queue (CQ); determining whether an execution reply table of the CE comprises an unsecure value; if so, reallocating a physical address for a user data transaction corresponding to the unsecure value; and outputting a write command into a submission queue (SQ) for programming the user data transaction into the reallocated physical address.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: May 25, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Sheng-Liu Lin
  • Patent number: 11012090
    Abstract: A method and a device for generating a data packet to be transmitted comprising data and at least one value for a cyclic redundancy check (CRC) value, are described, wherein the CRC value is generated using at least one previously determined polynomial on the basis of at least some of the data and the method comprises initializing a counter value, counting units of data, wherein the counter value changes for each unit of data, and adding a CRC value into the data packet, when the counter value reaches a reference value or all units of data in the data packet have already been counted, wherein the CRC value is generated over the units of data which have been counted since the counter value last reached the reference value or since the counter value was initialized. Furthermore, a method and a device for checking a corresponding received data packet are described.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 18, 2021
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventors: Frank Quakernack, Daniel Jerolm
  • Patent number: 11003697
    Abstract: A process for generating regular expressions (regexes) as extraction patterns in a cluster computing system includes: receiving log events, a set of seed words, and a set of seed patterns; determining whether the set of seed words is full; if not, generating a new patterns by iteratively adding new patterns whose pattern scores S1 surpass a first preset score into the set of seed patterns; selecting a subset of seed patterns from the set of seed patterns; determining whether the subset of seed patterns is empty if not, generating a subset of seed words whose word scores S2 surpass a second preset score and iteratively adding the subset of seed words into the set of seed words; and repeating the above steps until the set of seed patterns is full and the set of seed words is empty; and finally pruning the set of seed patterns.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 11, 2021
    Assignee: HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY (HUTECH)
    Inventors: Khanh Duc Tran, Nghia Van Bui