Abstract: An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The decision threshold is adjusted to balance a number of corrected ones and zeros.

Abstract: In one embodiment, the invention is directed to a data selection circuit for a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The data selection circuit is connected to receive the debug data and comprises logic for receiving the debug data as a plurality of N-bit portions of block-aligned data and outputting a designated one of the N-bit portions; and circuitry for providing to the receiving logic a control signal for designating one of the N-bit portions.

Abstract: According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. Functionality may be provided in the performance monitoring application for initiating the measurement of secondary metrics with regard to identified instructions, data addresses, ranges of identified instructions, or ranges of identified data addresses, based on counter values for primary metrics. Thus, for example, when a primary metric counter, or a combination of primary metric counters, meets or exceeds a predetermined threshold value, an interrupt may be generated. In response to receiving the interrupt, counters associated with the measuring of secondary metrics of a range of instructions/data addresses may be initiated.

Abstract: A programmable bit error rate monitor includes an error counter, a monitoring period counter with a programmable upper bound to set the monitoring period, and an error flag generator that compares the actual error count to a programmable threshold. The error flag generator may generate flags at different sensitivity levels, and the user may programmably select one of those flags. The three flags can be generated by independent comparators, or they can be extrapolated from the base error flag—e.g., by comparing only certain bits of the error count to corresponding bits of the threshold.

Abstract: A method and semiconductor integrated circuit in which a receiver receives reception data and executes reception processing on the basis of a clock signal supplied from a PLL and a transmitter which receives parallel transmission data and executes serial transmission processing on the basis of the clock signal, and having a loop back function of supplying data output from the transmitter to the receiver for test. The receiver capable of executing control so as to make a phase of the input data coincide with that of a recovery clock.

Abstract: In one embodiment, the invention is directed to a match circuit for implementation in a general purpose performance counter (“GPPC”) connected to a bus carrying debug data. The match circuit comprises logic for activating a match signal when a selected N-bit portion of the debug data matches an N-bit threshold for all bits selected by an N-bit match mask (“mmask”).

Abstract: First and second control circuit sections that mutually communicate via a series-parallel converter comprise first and second adder-subtracter respectively. When any receiving error occurs in each control circuit section, a variation value 3 is added to the adder-subtracter on the receiving side. When data is normally received, a variation value 1 is subtracted from the adder-subtracter. Initial value of the adder-subtracter is set to 9. When a current value exceeds 11, first and second error detection signal is generated to carry out alarm display or initialization, and initialization and restart of the other-side control circuit section.

Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores test algorithm instructions. A Rom logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Abstract: A semiconductor testing circuit being arranged for testing a semiconductor storage device, and having a simple construction and a great number of executable test patterns. Counters designate portions of a write/read address by count values outputted from the counters, respectively, where each of the portions is comprised of one bit or a plurality of successive bits. A switching circuit selectively outputs counter-control signals for individually controlling operations of the counters. Each of the counter-control signals is a common counter-control signal commonly used for the counters or the most significant bit of one of the portions outputted from a first one of the counters other than a second one of the counters for which the counter-control signal is outputted. Thus, it is possible to change assignment of the write/read address to the count values of the counters.

Abstract: In some embodiments, a first comparator compares a first error rate and a first threshold value and a second comparator compares a second error rate and a second threshold value. Other embodiments are described and claimed.

Abstract: A data processing system includes first, second, and third agents connected to a shared bus. The third agent is able to receive information via the shared bus from the first agent or from the second agent. The third agent includes a skew compensation circuit to determine signal skew in signal received via the shared bus and to compensate for the skew by adding delay into selected signals of the bus. The skew compensation circuit determines whether the first agent or the second agent is the sender of information received by the third agent via the shared bus. The skew compensation circuit alters the skew compensation based on the identity of the sender such that the delay into the bus signals is specific to the corresponding sender.

Abstract: A method and apparatus for detecting flaws requiring sparing of portions of storage media included as part of a hard disk drive are provided. A window of a selected portion of the storage medium is formed, and the density of defects detected within that window is calculated. If the density of defects exceeds a threshold amount, a signal is passed to the controller. The portion of the storage media containing the defects that caused the generation of the flag may then be spared. The present invention allows the potential for detected defects to significantly affect the ability of the storage medium to be assessed. Furthermore, the present invention does not require that the location of each defect be stored in memory. Accordingly, the present invention is economical to implement, and allows defects to be assessed in substantially real time and with improved accuracy.

Abstract: An apparatus for monitoring asynchronous transfer mode cells in the communication system is proper for recognizing state information of asynchronous transfer mode cells transceiving between a base transceiver station and a base station controller. Accordingly, the apparatus enables to monitor the contents of the cell by comparing VPI/VCI of the ATM cells inputted to the multiplexing/demultiplexing part to the other VPI/VCI latched hardware, have the cell bus RX I/F count the number of the error-occurring ATM cells by carrying out header error checks of the ATM cells inputted to the cell bus RX I/F itself, and find out how long the cell transferring time takes for transceiving loop is found out by transceiving the test ATM cells between the multiplexing/demultiplexing part being the ATM low rate subscriber multiplexing/demultiplexing board assembly (ALMA) and the base transceiver station.

Abstract: A system and method for efficiently correcting block errors in packet-based digital communications are provided whereby the ratio of redundant symbols/message symbols over the length of a data packet decreases in order to more efficiently use available bandwidth. The reduction of this ratio, and subsequently the change in a corresponding framing schedule, may be determined through negotiations between the transmitting device and the receiving devices. Each receiving device calculates a redundancy requirement based on signal-to-noise ratio samples. This requirement is returned to the transmitting device in the form of a schedule request. The transmitting device determines if a new framing schedule is needed based on the schedule request, and communicates this new framing schedule to the receiving device. Once the receiving device acknowledges receipt of the new schedule, the transmitting device switches to the new framing schedule for future data packet transmissions.

Abstract: An error rate detector is provided. The error rate detector includes a sequence generator that is adapted to generate a test sequence for comparison with a received sequence. The error rate detector also includes a self synchronization circuit that is responsive to the test sequence received from the sequence generator and the received sequence. The self synchronization circuit is adapted to move the sequence generator to a different point in the sequence based on a measure of mismatches between the test sequence and the received sequence.

Abstract: A logic analyzer according to the subject invention employs a bi-directional counter that can be incremented in response to detection of certain events, and decremented in response to detection of other, different, events. Both an overflow (incremented to a predetermined count) and an underflow (decremented to a predetermined count) can be tested by a trigger machine of the Logic Analyzer.

Abstract: Packets of data from multiple queues are transferred onto a single channel. Each queue has associated with it a data rate for servicing a packet within the queue. Each queue has an integer that, relative to the other numbers, represents is inversely related to the assigned data rate. Each queue has associated with it a counter and that is loaded with its corresponding integer. The counter values are compared, and the queue corresponding to the lowest counter value has a packet coupled to the channel. The counter of the selected queue is incremented by its integer. The next queue that is selected is the one that corresponds to the counter with the lowest count value after the counter that corresponds to the previously selected queue has been updated.

Abstract: A memory tester tests a random access memory device under test (DUT) comprising addressable rows and columns of memory cells, and provides a computer with enough information to determine how to efficiently allocate spare rows and columns for replacing rows and columns containing defective memory cells. During a test the memory tester writes a “fail” bit into each address of an error capture memory (ECM) to indicate whether a correspondingly addressed memory cell of the DUT is defective. The tester also includes a set of programmable area fail counters, each for counting of the number of memory cells within a separately selected area of the memory's address space. After the test, the computer processes the counts to determine whether it needs to allocate the spare rows and columns and, in some cases, to determine how to allocate the spare rows and columns.

Abstract: An asynchronous FIFO circuit has a memory; asynchronous read and write for reading a predetermined amount of data from and reading the predetermined amount of data into the memory on a first-in-first-out basis; an error write counter of counting up by 1 if the predetermined amount of data written into the memory contains an error; an error read counter of counting up by 1 if the predetermined amount of data read from the memory contains an error; and a comparator for comparing a value of the error write counter with a value of the error read counter, the comparator outputting a logic level of 0 when the value of the error write counter is coincident with the value of the error read counter, and the comparator outputting a logic level of 1 if the former value is different from the latter value.

Abstract: The present invention, in one embodiment, is a network having at least one controllable CAN-based sensor device having a microcontroller, a power source and at least one host controller. Preferably, the network is a Smart Distributed System-based network. In this embodiment, each microcontroller communicates with the controller, generating and storing a value in at least one counter when a successful message is transmitted to the controller. When a unsuccessful message is detected by the microcontroller, a counter generates and stores a second or decremental value in the same or different counter. When the sum total value of error messages in the counter reaches a marginal critical value, a message is transmitted to the controller while maintaining the microcontroller's communication with the network. When a counter reaches a critical value, the microcontroller enters a bus off mode and disconnects the sensor device, and thus the microcontroller, from the network.

Abstract: Method and apparatus for link physical error tracking that includes a one or more shift registers, one or more counters, and a comparator. The shift register receives one or more status bits for an input data stream denoting whether bytes of the input data stream have a link physical error. The counter increments an error count when receiving at least one status bit that denotes a link physical error, and decrements the error count when receiving at least one status bit from an output of the shift register that denotes a link physical error. The comparator compares the error count with a maximum value. A retrain signal is generated if the error count becomes larger than or equal to the maximum value. The retrain signal may be used to signal that a connection between two nodes needs to be retrained to get the two nodes back into synchronization. Link physical errors that occur aligned and misaligned with a rising edge of a symbol clock are trackable.

Abstract: A system, method and apparatus for generating security codes that may be used in providing software security are disclosed. In a preferred embodiment, at least one analog data signal representing a security code is generated by security circuitry. Such analog data signal is input to an analog input port of a computer. The generated security code may be used to prevent unauthorized operation of a software program. In a preferred embodiment, such an analog data signal is a resistance value, and such an analog input port of a computer is a game port. Most preferably, multiple sequences of resistance values are generated and input to the analog pins of the game port. A combination of the multiple sequences of resistance values form a security code that may be used to provide software security for a software program. Additionally, one or more confounding signals may be generated to make decoding the security code more difficult.

Abstract: A pulse code analyzer for analyzing data transmitted by transmitter/receivers on a transmission facility interconnecting the transmitter/receivers. The analyzer apparatus has a data converter with a reference and an auxiliary channel for receiving the data and clock apparatus for recovering a clock signal from the data and generating variable time delayed subtone clock signals to the data converter reference and auxiliary channels. Processor apparatus coupled to the data converter and clock means controls a time delay between the subtone clock signals and the voltage level of data received by the channels to detect errors occurring in the received data and records the detected errors in counter apparatus coupled to the data converter channels and clock apparatus. The processor apparatus records a three dimensional matrix of the recorded errors determining a probability predicting the data errors.

Abstract: A communication device communicates with a station and includes a receiver which receives speech signal frames from the station. The speech signal frames have speech signals. The communication device further includes a counter and an attenuation circuit. The counter counts the number of bad frames of the received speech signal frames. The attenuation circuit diminishes the amplitude of the speech signals when the count of the counter is higher than one indicating more than one bad frame is received. The station is either connected to a switched network or is a satellite station.

Abstract: A circuit arrangement for sensing errors in bit patterns for recording and plotting the occurrence in time, precisely to a bit, of transmission errors in a binary test signal. A pulse-generating device (5), which is fed a bit error signal sequence (BFS) generates a pulse (IS) in response to every signal change. A counting device (11), increments a counter as a function of a supplied bit timing (BT) and resets it to count value 1 when the pulse (IS) from the pulse-generating device (5) is applied. A buffer device (13) linked to the outputs of the counting device stores the counter contents of the counting device (11) in response to the application of a pulse (IS). An evaluation device (17,19,23) is fed, stores and displays the buffered counter contents.

Abstract: A communications system in which information is transmitted in a plurality of time slots grouped into a plurality of superframes which are, in turn, grouped into a plurality of paging frames. A remote station receives paging messages once in each paging frame.

Abstract: A packet based policing method and apparatus is disclosed which increases the throughput of a network by avoiding the waste of resources. The invention receives cells for a first packet at a node in a network, determines whether a non-conforming cell may be passed according to a running credit value, identifies whether a cell is conforming or non-conforming, passes the cell if the running credit value indicates that a non-conforming cell may be passed or if the cell is a conforming cell, borrows a cell credit if the credit value indicates that a non-conforming cell cannot be passed, wherein the borrowing of the cell credit allows the running credit value to be decremented until reaching a predetermined negative number and decrements the running credit value.