Abstract: An information transmission device that is included in components and carries out communication between the components in an information processing device including a control monitoring unit that controls and monitors the components, comprising: a transmission control unit that stores a transmission parameter; a transmission unit that has transmission data input thereto in a first transmission speed or a second transmission speed having a transmission speed lower than the first transmission speed, adjusts the transmission data according to the transmission parameter, and sends the transmission data as a transmission signal to the information transmission device which is a connection destination; a receive control unit that stores a receive parameter; and a receiving unit that adjusts a receive signal received from the information transmission device which is a connection destination in accordance with the receive parameter, and outputs the receive signal in the first transmission speed or the second transmiss

Abstract: Systems and methods are disclosed that are responsive to a rate of change of a performance parameter of a memory. In a particular embodiment, a rate of change of a performance parameter of a non-volatile memory is determined. The rate of change is compared to a threshold, and an action is performed in response to determining that the rate of change satisfies the threshold.

Abstract: In some embodiments the continuous measuring of temperature in remote memory devices operating within an electrically noisy environment is facilitated by coordinating the progressive approximation of temperature within quiescent periods of non-activity as known by a memory controller.

Abstract: A method, apparatus and computer program product are provided for use in a system that includes one or more processors, and multiple threads that are respectively associated with the one or more processors. One embodiment of the invention is directed to a method that includes the steps of generating one or more test cases, wherein each test case comprises a specified set of instructions in a specified order, and defining a plurality of thread hardware allocations, each corresponding to a different one of the threads. The thread hardware allocation corresponding to a given thread comprises a set of processor hardware resources that are allocated to the given thread for use in executing test cases. The method further includes executing a particular one of the test cases on a first thread hardware allocation, in order to provide a first set of test data, and thereafter executing the particular test case using a second thread hardware allocation, in order to provide a second set of test data.

Abstract: An apparatus and method for deciding a target Packet Error Rate (PER) in a wireless communication system are provided. The method includes setting a target PER, comparing a variance of the target PER (?p(k)) with a previous target PER variance (?p(k?1)), and updating a next target PER variance (?p(k+1)) using an average capacity and a previous average capacity in accordance with the comparison result between the target PER variance (?p(k)) and the previous target PER variance (?p(k?1)).

Abstract: In a digital broadcast receiver, when a bit error rate (BER) is larger than a threshold in a BER determining part, power is supplied to a first tuner and a second tuner for diversity reception. When the BER is smaller than the threshold, power supply to one of the first tuner and the second tuner is stopped for single reception. This structure allows power supply to one of the tuners to be stopped in excellent reception environments, thus reducing power consumption.

Abstract: A decoder architecture and method for processing codewords are provided. In one implementation, the decoder architecture includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder configured to receive codewords one at a time from the input buffer. The decoder processes each codeword only for a minimum amount of time for the codeword to become error free. The decoder architecture further includes an input buffer monitor and supply regulator configured to change a voltage supply to the decoder responsive to an average amount of time or each codeword to become error free.

Abstract: Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.

Abstract: A facsimile machine receives image data from a facsimile machine of another end. A Random Access Memory (RAM) stores a measured average value and fluctuation of an Eye Quality Monitor (EQM) value of the image data, and a number of error lines of the image data as an EQM data table. In past facsimile communication, a main control unit receives a training signal from the facsimile machine of the other end, and executes a training process. The main control unit measures an average value and fluctuation of an EQM value of the training signal, and compares the measured average value and the fluctuation of the EQM value with the average value and the fluctuation of the EQM value stored in the EQM data table. When there is no match, the main control unit executes the training process again.

Abstract: The invention includes a novel scan chain structure for LSSD or GSD IC operation. The scan chain structure includes a first flip-flop (L1) and a second flip-flop (L2) configured to operate the first flip-flop (L1) in normal mode operation, in scan mode operation, in initialization mode and in low leakage power mode operation, wherein each flip-flop within a long scan chain of latches includes a data input, data output, a clock input, a scan-in input and a scan-out output, arranged for normal mode operation. A buffer circuit is electrically connected between the scan-out output of the second flip-flop (L2) and the scan-in input of the first flip-flop (L1) for the next latch in the scan chain, the buffer circuit including a control element that controls the operation the first flip-flop (L1) to scan mode or low power leakage mode. The first flip-flop (L1) is set to a data output value upon exit from low power leakage mode that is the same value that it is set to at initialization during normal mode operation.

Abstract: RAID control of multiple hard disk drives in a computer system includes performing a fault-tolerant data computing operation for a written data. The timing for performing the fault-tolerant data computing operation is determined by accessing a data stored in one of the hard disk drives, detecting a partial data length of a data stream having been transmitted from the hard disk drive to the computer system, issuing a triggering signal when the data length has reached a unitary length less than the total length of the data stream, and then performing the fault-tolerant data computing operation with the unitary length of data in response to the triggering signal.

Abstract: A method and system for improving Field Replacement Unit (FRU) isolation in memory sub-systems by monitoring Voltage Regulator Module (VRM) induced memory errors. A comparator compares the output voltage coming from the VRM to memory. If the comparator detects a VRM output voltage transient that is outside a rated threshold, then a counter is increased by one. If the counter exceeds a count threshold, a VRM error is posted. If a memory failure occurs within a predetermined period of time, then the VRM error pinpoints the VRM output voltage transient as being the likely cause of the memory failure.

Abstract: A method and system of establishing communications between at least two independent software modules is provided. The design comprises providing a media connection between software modules, wherein the software modules employ a communications protocol and participate in a bi-directional master-slave relationship between a master module and a slave module. The design further comprises sending arbitrary data between the master and slave modules, wherein the arbitrary data is used by the master module to control and obtain status from the slave module, and sending arbitrary data further enables the slave module to return data and status information to the master module. The design also employs a communications watchdog between the master and slave modules, wherein the communications watchdog monitors communications quality between the master and slave modules and impairs functionality in the master and slave modules when communications quality degrades.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: The invention proposes a method for controlling a variable of transmission between a mobile network element and a fixed network element, wherein the transmission is effected by repeatedly sending of data units, and a control of the variable of the transmission based on a target data unit error rate is performed, the method comprising the steps of detecting (S2), whether a received data unit includes an error, analyzing (S3), in case an error is detected, the transmission number of the data unit, detecting (S4), whether the analyzed diversity of the data unit is equal to a target transmission number, and forwarding (S5) the data unit to a network control element in case the transmission number of the data unit is equal to the target transmission number, or in case no error is detected. The invention also proposes a corresponding fixed network element and a corresponding network control element.

Abstract: A failure threshold host command that provides a host with the capability to tune a storage controller path failure threshold based on the host application performance requirements. The failure threshold host command comprises path failure threshold rules that the storage controller uses to determine when a CHPid has reached a failed state condition.

Abstract: A method according to one embodiment includes monitoring a data transfer operation for detecting temporary errors; determining whether art error burst has occurred based on the monitoring; if an error burst has occurred, altering a condition of the data transfer operation; monitoring the data transfer operation having the altered condition for detecting temporary errors; determining whether another error burst has occurred based on the monitoring of the data transfer operation having the altered condition; and if another error burst has occurred; altering another condition of the data transfer operation. Additional systems and methods are also presented.

Abstract: A system and method for detecting a correct transmission format upon encountering a decoding error in a variable-format transmission scheme, wherein the decoding error results from an unsuccessful decoding of a frame. The invention provides for prioritizing the permissible formats, resulting in a prioritized order. The frame data is then decoded according to one or more of the permissible formats in the prioritized order, and if the decoding is successful in accordance with one of the formats, that format is selected as the correct transmission format.

Abstract: A data transfer method for connecting a master unit on an upstream side and a plurality of slave units on an downstream side in series with serial bus by a daisy chain system and transferring data having an appended error check code or error correction code between a data transmitter and a data receiver, the data transfer method including: transferring the data flowing in the serial bus in the slave unit from the data transmitter to the data receiver without performing an error check or error correction; performing an error check of the data in a circuit provided in the slave unit aside from a circuit in which the data flow; and informing a result of the error check to the master unit individually by the slave unit, which has performed the error check of the data.

Abstract: A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, a memory relocation mechanism in the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. When a correctable error occurs, the memory relocation mechanism uses data from a partner mirrored memory block as a data source for the memory block with the uncorrectable error and then relocates the data to a newly allocated memory block to replace the memory block with the uncorrectable error.

Abstract: A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the plurality of error occurrences are associated with a single bit of a bus. The determined, single bit may correspond to a faulty component of the bus. This level of identification efficiently addresses problems. For instance, a corrective algorithm may be applied if the plurality of error occurrences are associated with the single bit. Alternatively, the bus may be disabled if the plurality of error occurrences are not associated with the single bit of the bus. In this manner, implementations may detect, identify and act in response to multiple failure modes.

Abstract: Provided is a test system conducting a parallel bit test. The test system, conducting a parallel bit test on a plurality of memory modules mounted on a socket, comprises a plurality of counters and a comparator. Each of the counters counts the number of data output signals in the same logic state, among the data output signals outputted from each memory of the memory modules, and outputs a count signal. The comparator compares the count signal outputted from each of the counters and outputs a comparison signal corresponding to a defect of the memory modules. According to the test system, defects in a memory module can be accurately detected and a possibility of an error in the detection can be reduced when a plurality of memory modules are tested, as compared to conventional test systems.

Abstract: A method of assembling a plurality of frames including cell/packet-formatted data according to a predetermined frame format for transmission in a communication signal in a wireless or satellite environment. The method begins by assembling a data payload for each frame having a first variable size, including at least one of a partial data cell/packet and a complete data cell/packet. Then, for each frame a block code having a second variable size is generated for use in error correction. Each frame is provided with a frame header which defines aspects of the frame. Finally, the data payload, the block code and the format header are combined to form a frame corresponding to the plurality of frames, the format header defining a first portion of the frame, the data payload defining a second portion of the frame and the block code defining a third portion of the frame.

Abstract: Based on an expected error rate for a wireless transmission, the length of the transmission may be limited so that the probability of an error in one or more particular data segments is no greater than a predetermined threshold value. The expected error rate and/or the threshold value may be periodically changed, based on various criteria.

Abstract: Embodiments of the invention enable the integrity of data processed by a switch to be guaranteed better than 10?9 undetected erroneous frames per flight hour. To do this, rules for disabling ports are included in the switch management program. These rules include a maximum absolute admissible number of erroneous frames, to a maximum relative rate of admissible erroneous frames and a minimum number of erroneous frames constituting a significance threshold. Random errors are detected at the level of each frame due to the insertion of a CRC. Deterministic or data-dependent errors able to deceive systematically the CRC check are made random by means of a frame index.

Abstract: Methods and apparatus for dynamically configuring a redundant area of a physical page are disclosed. According to one aspect of the present invention, a method for dynamically configuring a redundant area of a page associated with a physical block of a non-volatile memory of a memory system includes determining when at least one byte associated with the redundant area is to be altered. The byte includes error correction code (ECC) information associated with a first ECC algorithm at the time of the determination. The method also includes altering the byte when it is determined that the byte is to be altered. Altering the byte includes altering the byte to include ECC information associated with a second ECC algorithm.

Abstract: A data error-detecting method for detecting errors before C1 decoding procedure is provided. First, a bit modulation is performed for modulating data channel bits obtained from an optical disk into 8-bit data. When the data channel bits is determined to introduce a legal mapping, an erasure bit having a first value is derived and tagged at the modulated 8-bit data, otherwise an erasure bit having a second value is derived and tagged at the modulated 8-bit data. After the 8-bit data being arranged as a codeword composed of 32 erasure bits respectively tagged with 32 8-bit data, counting the number of the modulated 8-bit data tagged with the erasure bit having the second value. When the counted number is less than 4, the codeword composed modulated 8-bits data tagged with the erasure bits having the second value can be corrected.

Abstract: A communication system comprises a transceiver capable of receiving a data burst as part of a paging block. The system also comprises processing logic capable of comparing at least part of the data burst to a plurality of permutations of the data burst to locate a matching permutation. The processing logic determines a bit error rate (BER) in accordance with a difference between the data burst and the matching permutation. The processing logic uses the BER to operate the communication system.

Abstract: A method for monitoring the availability of a data processing system is proposed. For example, the system runs a management application, which involves the periodic transmission of blocks of data from multiple local computers to a central computer. In the method of the invention, whenever a block of data must be transmitted by a generic local computer, an expected transmission delay of a next block of data is estimated; this information is then attached to the block of data. As a result, the central computer receiving the updated block of data can calculate an expected receiving time of the next block of data accordingly. If the next block of data is not received in due time, the central computer determines a failure of the local computer. Preferably, the central computer also scans a subset of ports of the local computer, so as to ascertain whether the problem is due to a temporary unavailability of the application or to an actual crash of the local computer.

Abstract: A method for operating a volatile random access memory as a detector, with predetermined information being stored in at least one area of the volatile random access memory. The method includes interrupting a supply voltage for the at least one area of the random access memory during a time period, reading information from the at least one area of the random access memory, and checking the extent to which the predetermined information and the information that has been read match or whether the predetermined information and the information which has been read have a predetermined relationship.

Abstract: Disclosed is a method and system enabling to remove a noise effectively by establishing types of shocks that may occur possibly and by sensing a shock using the error corresponding to the shock. The present invention includes the steps of reading a data recorded on a disk, detecting an error or errors from the read data using CIRC (cross interleaved Reed-Solomon code), counting a number of the detected errors, and of judging whether a shock is generated or not using the counted number of the errors.

Abstract: Exemplary embodiments of the present invention relate generally to an improved off-board tool for communicating with a vehicle diagnostic system using a CAN communications protocol. In one exemplary embodiment, an off-board tool having an executable program for linking the off-board tool to a vehicle diagnostic system is provided. The program includes code for transmitting a first message, having a first length from the off-board tool to the vehicle diagnostic system and code for determining whether an acknowledgment receipt of the first message is received by the off-board tool from the vehicle diagnostic system. The program further includes code for transmitting a second message, having a second length, from the off-board tool to the vehicle diagnostic system if the acknowledgement receipt of the first message is not received by the off-board tool. Another exemplary embodiment provides a method for linking an off-board tool to a vehicle diagnostic system.

Abstract: In digital broadcast receiver (100), when a bit error rate (BER) is larger than a threshold in BER determining part (109), power is supplied to tuner (103) and tuner (104) for diversity reception. When the BER is smaller than the threshold, power supply to one of tuner (103) and tuner (104) is stopped for single reception. This structure allows power supply to one of the tuners to be stopped in excellent reception environments, thus reducing power consumption.

Abstract: Methods and systems for identifying configuration parameters for a network device are provided. The method includes generating a stream of traffic data, where the traffic data has a known characteristic. Then, applying the stream of traffic data to the network device, where the network device has a specific type, and the network device generates an output based on the traffic data. The method then includes monitoring performance of the network device while the traffic data is processed by the network device, and the monitoring is configured to generate monitoring data for the traffic data applied to the network device having the specific type. Also, the method includes analyzing the output from the network device, where the analyzing is performed to identify how the traffic data was handled by the network device, and the analyzing is configured to generate performance metrics. The method further includes saving the monitoring data and the performance metrics to a knowledge database.

Abstract: Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: Geometrically-dependent error rates are used to identify sectors for XORing data in a RAID system for parity purposes in such a way that the probability of failure of any particular group is minimized.

Abstract: An apparatus comprising a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a controller. The controller includes an error recovery module configured to retry a data communication when an error is detected and deactivate the SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value. Other devices, systems, and methods are disclosed.

Abstract: An estimation apparatus for estimating a channel response of a radio propagation path using a received signal including a first known signal, comprises a generator which generates a reference signal matrix, a calculator which calculates a generalized inverse matrix of the reference signal matrix including singular values which exceed a preset threshold value, an estimation unit configured to estimate an impulse response of the radio channel modeled using a transversal filter based on the first known signal and the generalized inverse matrix, and a converter which converts the estimated impulse response into a frequency-domain signal to acquire a frequency transfer function of the channel.

Abstract: Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.

Abstract: An apparatus and method for decision threshold control in an optical signal receiver. A forward error correction (FEC) decoder provides a feedback signal representative of corrected errors. The decision threshold is adjusted to balance a number of corrected ones and zeros.

Abstract: In at least some embodiments, a Programmable Logic Device (PLD) is configured to using a counter in conjunction with a threshold value to determine whether a configuration data frame is to be reloaded into a frame register if errors are encountered. In at least other embodiments, a Programmable Logic Device (PLD) is configured to sequentially load configuration data frames into a frame register, check for errors in the configuration data frames during sequentially loading, and correct errors during sequentially loading without reloading one or more previously-loaded different configuration data frames.

Abstract: A transfer start/end detecting section detects timing at which a DMARQ signal becomes an H level or an L level. A transfer time-measuring section measures a transfer time during which data transfer is actually performed within a period in which a predetermined number of data blocks are transferred. A transfer byte count-measuring section measures a transferred byte count of data that have successfully been transferred. An effective data transfer rate-computing section computes an effective data transfer rate by dividing the transferred byte count by the transfer time. A transfer rate-comparing section compares the effective data transfer rate with a transfer rate that is one step slower than a current transfer rate output from a selectable transfer rate-storing section. If the former is slower, a transfer rate-switching section switches to the transfer rate that is one step slower. A large decrease in the effective data transfer rate caused by data corruption is prevented.

Abstract: An apparatus and method for deciding a target Packet Error Rate (PER) in a wireless communication system are provided. The method includes setting a target PER, comparing a variance of the target PER (?p(k)) with a previous target PER variance (?p(k?1)), and updating a next target PER variance (?p(k+1)) using an average capacity and a previous average capacity in accordance with the comparison result between the target PER variance (?p(k)) and the previous target PER variance (?p(k?1)).

Abstract: A data communication apparatus determines whether the error type is a burst error or not based on an error occurrence state of the data received from a data transmitting apparatus and transmits error type-basis error information. The data communication apparatus receives the error type-basis error information and sets the redundancy degree of an FEC processing section based on the error rate of the errors other than a burst error.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: A method a system for automatically controlling an adaptive interleaver involves monitoring performance parameters of a transmission system and controlling the adaptive interleaver in response to the performance parameters. The SNR and the data rate of the transmission system are preferably determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the SNR. Alternatively, the BER and the data rate of the transmission system are determined. The data rate is analyzed and the adaptive interleaver is adjusted in response to the data rate and the BER. Alternatively, any one of the SNR, BER or data rate can alone be monitored and used to the adaptive interleaver. The system provides a effective system for adjusting an adaptive interleaver in response to performance parameters of a transmission system.

Abstract: Electronic apparatus such as a cordless phone, the electronic apparatus includes detection means for detecting the error of received data and at least two speech buffers as speech buffers for temporarily storing the received voice data. In case the electronic apparatus is in a position where it can communicate with a repeater and a base unit, the electronic apparatus stores the voice data transmitted from the base unit into one speech buffer and stores voice data transmitted from the repeater into the other speech buffer, and uses the voice data of a lower error rate. This maintains high speech quality. In case the electronic apparatus roams from a second wireless network formed around the repeater to a first wireless network formed around the base unit, smooth roaming is provided without degrading the speech quality by using the voice data of a lower error rate stored in either of the two speech buffers, even when the conversation state is gradually degraded and more errors are detected in the received data.

Abstract: A method for transmitting on an optical connection an input data sequence having first and second logic states, includes encoding the input data sequence prior to transmission on the optical connection, where the encoding minimizes the first logic states in the encoded data sequence. The encoding includes: arranging the input data sequence in parallel on a number of bus lines; counting the first logic states in the input data sequence; comparing the counting result with a value equal to half of the lines; and logically inverting the input data sequence on the lines if the counting result is greater than half of the lines of the input data sequence. The method further includes: ordering values of the input data sequence; identifying the first value having the first logic state; and applying the encoding operation just to the ordered values subsequent to the first value having the first logic state.