Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such as in spare cells of only one page or distributed among header regions of multiple pages. The page or pages containing the block cycle count are initially read from each block that is being erased, the cycle count temporarily stored, the block erased and an updated cycle count is then written back into the block location. User data is then programmed into individual pages of the block as necessary. The user data is preferably stored in more than two states per memory cell storage element, in which case the cycle count can be stored in binary in a manner to speed up the erase process and reduce disturbing effects on the erased state that writing the updated cycle count can cause.

Abstract: In one embodiment, a method may determine a number of data transitions occurring in a forbidden zone at each of a first and second slice levels and adjust a slice level offset for an amplifier based on the number of data transitions at the first and second slice levels. Furthermore, a phase window of the forbidden zone may be adjusted to attain a desired bit error rate for a receiver.

Abstract: An integrated circuit includes a testable delay path. A transition of a delay path input signal causes a subsequent transition of a delay path output signal. A pulse generator receives the delay path input and output signals and produces a pulse signal having a pulse width indicative of the delay between the delay path input and output signal transitions. A delay line receives the pulse signal from the pulse generator. The delay line generates information indicative of the pulse signal pulse width. The delay line may include multiple stages in series where each stage reduces the pulse width of the pulse signal. The delay line may include a high skew inverter having PMOS and NMOS transistors having significantly different gains. The pulse generator is configured to produce a positive going pulse signal regardless of whether the delay path is inverting or non-inverting.

Abstract: In a receiver operable in response to a data signal, an eye aperture size is detected along a time axis by an eye aperture detection circuit and is controlled by a control circuit so that it becomes a maximum. The eye aperture detection circuit determines different decision time points of the same level arranged along a time axis and judges whether or not an error is caused to occur at each of the decision time points, so as to detect the eye aperture size and to produce detection results. The control circuit processes the detection results in accordance with a predetermined algorithm to successively vary the eye aperture size and to keep the data signal at an optimum amplitude.

Abstract: In a method and a device for testing a plurality of measured devices in parallel by using a single signal generator and a single bit error measuring device, a serial testing signal for is converted and demultiplexed into parallel signals corresponding to channels respectively assigned to a plurality of measured devices and a redundant channel, one of the plurality of parallel signals being a passing signal passing through the redundant channel is converted into a channel determination signal for specifying an alignment of the measured devices, output signals of the measured devices and the channel determination signal are multiplexed corresponding to a demultiplexing mode used for demultiplexing the serial signal, and bit errors are measured in the multiplexed signals and measured devices at which the bit errors are generated are detected in consideration of the channel determination signal.

Abstract: Systems and methods for multi-stage signal detection in MIMO transmission including Bernoulli-Gaussian detection are provided. A multistage iterative signal decoder is provided that exploits the property that in a relatively simply decoding scheme such as mean square error (MSE) or zero-forcing (ZF) only a small portion of the total symbols are mis-detected. Therefore, an optimality test is performed on the output of a relatively low complexity decoder unit. If the symbol passes the optimality test, it is presumed to be correctly decoded. Otherwise, the symbol is sent for further processing to a relatively higher complexity decoding unit such as a sphere decoder. In this way, processing efficiency is increased, because only those symbols requiring additional processing are processed by the high complexity processing unit.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing three thresholds; receiving a binary serial data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; data stream inputs below the first threshold and above the third threshold are a “0” if both the second and third bits are “1” values, and as a “1” if either of the second and third values is a “1”; data stream inputs above the second threshold and below the third threshold are a “1” if both the second and third bits are a “0” value, and as a “0” if either of the second and third values is a “0”.

Abstract: A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

Abstract: A state machine method and system are provided for determining non-causal channel equalization thresholds. The method comprises: receiving a non-return to zero (NRZ) data stream encoded with forward error correction (FEC); setting x=0; in State 0, adjusting a third threshold (Vopt) in response to corrected bit errors; if x=0, setting a first and second threshold equal to the third threshold; in State 1, if x=0, simultaneously adjusting the first threshold and the second threshold, to minimize the total number of corrected bit errors; in State 2, following State 0, adjusting the first threshold, independent of the second threshold, to minimize the total number of errors; in State 3, following State 0, adjusting the second threshold, independent of the first threshold, to minimize the total number of errors; and, adding 1 to x and returning to State 0.

Abstract: A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149.1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

Abstract: A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.

Abstract: A technique for determining a symbol erasure threshold for a received communication signal containing symbol information is disclosed. The technique begins by performing a first threshold calculation to produce an initial symbol erasure threshold, then performing a first margin calculation to produce an initial symbol erasure margin and then modifying the initial symbol erasure threshold using the initial symbol erasure margin to produce a modified symbol erasure threshold. By then periodically modifying the modified symbol erasure threshold adaptive via updating the symbol erasure threshold and/or symbol erasure margin based on various error quantities, the technique can compensate for time-variant considerations, such as drifting noise levels.

Abstract: An emulation parameter indicative of a data processing operation performed by a data processor is exported from the data processor. The parameter value is provided as a plurality of digital bits. After determining that the bits of a first group within the plurality of bits all have the same bit value and that a predetermined bit within a second group of the plurality of bits has a bit value equal to the bit value of the bits of the first group, only the second group of bits is output from the data processor without outputting the first group of bits.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: establishing a first threshold (V1) to distinguish a high probability “1” first bit estimate; establishing a second threshold (V0) to distinguish a high probability “0” first bit estimate; establishing a third threshold (Vopt) to distinguish first bit estimates between the first and second thresholds; receiving a non-return to zero (NRZ) data stream; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; in response to the comparisons, determining the value of the first bit.

Abstract: A decision function generator for a Viterbi decoder includes a compressor module for receiving arguments of a decision function and for evaluating functions of the arguments of the decision function, a memory module coupled to the compressor module for generating an intermediate function from the functions of the arguments, and a decompressor module coupled to the memory module for generating a sign value, an integer value, and a fractional value constituting a value of the decision function from the intermediate function.

Abstract: A method for optimizing a source synchronous clock reference signal timing to capture data from a memory device (e.g., DDR SDRAM) includes conducting an iterative two-dimensional data eye search for optimizing the delay of the source synchronous clock reference signal (e.g., DQS). Embodiments of the present invention are directed to tuning the delay for each device for the optimal margin in two dimensions: maximize the distance from the data eye walls and maximize the noise margin on the interface. An iterative data eye search is performed while varying the DQS delay timing and noise margin.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing thresholds to distinguish a first bit estimate; comparing the first bit estimate in the NRZ data stream to a second bit value received prior to the first bit, and a third bit received subsequent to the first bit; in response to the comparisons, determining the value of the first bit; tracking the NRZ data stream inputs in response to sequential bit value combinations; maintaining long-term averages of the tracked NRZ data stream inputs; adjusting the thresholds in response to the long-term averages; and, offsetting the threshold adjustments to account for the asymmetric noise distribution. Two methods are used to offset the threshold adjustments to account for the asymmetric noise distribution: forward error correction (FEC) decoding and tracking the ratio of bit values.

Abstract: A data and clock recovery circuit is provided for generating a recovered version of a transmitted data stream. The data and clock recovery circuit comprises three main circuit modules, namely a data recovery circuit, a clock recovery circuit, and a detector circuit. The data recovery circuit is arranged to receive a data stream, and to generate therefrom an estimate of the signal levels for each bit-period of the originally transmitted data stream. The estimates of the signal levels are stored within the data recovery circuit and are sampled by the clock recovery circuit so that the original data stream is recovered. The data recovery circuit is also arranged to generate a so-called “word metric” which is a quality factor representing the accuracy of the estimated signal levels. The clock recovery circuit is arranged to use both the received data stream, and the word metric generated in the data recovery circuit, to determine whether or not the current sampling time is optimal.

Abstract: An apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and having a predetermined input bit period, and sending output data signals corresponding to the input data signals. Glitches are detected in the input data signals by detecting reversals of signal level having a duration less than the input bit period. A glitch time value corresponding to the glitch duration is determined, and then a sampling clock rate is set at a rate determined from the glitch time value. The input data signals are sampled at the sampling clock rate to generate a sequence of input data samples. A voting number of input data samples are monitored and an output signal is provided, representing the value of a majority of the sequential input data samples.

Abstract: An apparatus for correcting duty cycle error is provided which includes circuitry capable of determining existence of a duty cycle error from input data received over data transmissions lines where the circuitry generates duty cycle correction data based on the duty cycle error. The apparatus also includes a digital analog converter (DAC) being coupled to the circuitry where the DAC is capable of receiving a magnitude portion of the duty cycle correction data from the circuitry. The apparatus further includes an adjustable bias driver being coupled to the circuitry, the DAC and the data transmission lines. The adjustable bias driver receives the magnitude portion of the duty cycle correction data from the DAC and receives a polarity portion of the duty cycle correction data from the circuitry where the adjustable bias driver adjusts the polarity of signals applied to the data transmission lines for correcting the duty cycle error.

Abstract: A first device delivers a clock offset message to a second device. The second device offsets its data transmission according to the clock offset message. A test pattern is transmitted from the second device to the first device. The first device then checks the received test pattern to determine whether the transmission was successful. The first device can then deliver an additional clock offset message to the second device to instruct the second device to offset its data transmission by a different value than was used previously. The second device again transmits the test pattern and the first device again checks the received pattern. By trying a number of clock offset values and determining which values result in successful transmissions of data, the first device can determine the optimal clock offset value and instruct the second device to use this value for all transmissions.

Abstract: The invention relates to a receiving circuit for receiving message signals, having a first sampler for converting the message signal into a first sampled signal by a first sampling method, having at least one second sampler connected in parallel with the first sampler for converting the message signal into a second sampled signal by a second sampling method, and having an analyzing unit for decoding the first sampled signal and/or the second sampled signal and checking them for errors.

Abstract: Method and apparatus for determining at least one characteristic of a digital data signal. The method includes identifying at least one region of a waveform such as an Eye Diagram that contains information for determining at least one characteristic of interest of the digital data signal. Sufficient samples of the digital data signal are then taken to fully construct only the identified at least one region of the Eye Diagram without fully constructing the entire Eye diagram, and the at least one characteristic of interest is then determined from the fully constructed at least one region of the Eye Diagram.

Abstract: A system and a method are provided for non-causal channel equalization using error statistics. The method comprises: receiving a non-return to zero (NRZ) data stream input encoded with forward error correction (FEC); establishing a plurality of thresholds to generate a first bit estimate; comparing the first bit estimate in the data stream to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; in response to the comparisons, determining the value of the first bit; FEC decoding the determined first bit value; and, using FEC error statistics to adjust the thresholds by evaluating the number of errors associated with a plurality of three-bit sequence combinations.

Abstract: Methods for monitoring the accuracy of positional measurements by encoders that translate positional information into signals include determining the difference between two signals generated by the encoder and comparing the difference to a threshold value. Differences greater than the threshold indicate an error in measurement by the encoders. The methods may be practiced using one or more computer programs. The methods may be practiced with any encoder, including absolute and incremental encoders. Encoders include components to implement the methods.

Abstract: A test signal attenuation circuit is built into a signal transmitter for modifying the energy content of the transmitter output signal. The built-in test signal attenuation circuit includes circuits for generating an attenuated, degraded, chopped signal. The built-in test signal attenuation circuit may be used for purposes of testing the performance of a link under degraded conditions.

Abstract: A system for the encryption and decryption of data employing cycle stealing to accelerate data processing operations. The cycle stealing is employed by using level sensitive latches in a microcode controller system for storing addresses and code words. The microcode controller system controls the data path hardware for executing the encryption/decryption operations.

Abstract: In a semiconductor device which outputs read-out data and a reference clock synchronized therewith for use in passing the data to other device, the generating timing of the reference clock and the generating timing of the data are compared by timing comparators 11A and 11B with first and second strobe pulses, and the logical values of the timing comparison result are compared by logic comparators 12A and 12B with first and second expected values. A logical condition decider 13 decides whether the combination of the logical comparison results satisfies a predetermined condition. When the predetermined condition is met, the decider 13 decides that the phase difference between the reference clock and the data is larger than a predetermined value, or that the duration of the data is longer than a predetermined time.

Abstract: A computer program product, apparatus, and method for correcting errors introduced into a set of data bits during transmission of the set of data bits over a channel includes determining a confidence measure for each data bit based only on the values of one or more of the data bits, each confidence measure representing the probability that the value of the corresponding data bit is correct; and changing the value of a given data bit when the confidence measure for the given data bit indicates that the value of the given data bit is not correct, thereby producing a corrected data bit.

Abstract: An increase in the code error rate in a received signal is detected in a light receiver. An loss of signal detector circuit for a light receiver 20 comprises a main discrimination circuit 8a for comparing the intensity of an electric signal obtained by converting a light signal by photoelectric conversion using a photoelectric conversion element 1 with a predetermined discrimination threshold; a reference discrimination circuit (8b, 8c, . . . ) for comparing the intensity of the electric signal with regard to a reference threshold which differs from the discrimination threshold; and an operation circuit 9 for detecting loss of the signal based on the results of the comparisons performed by the main discrimination circuit 8a and the reference discrimination circuit (8b, 8c, . . . ).

Abstract: A method of detecting and correcting bit errors in a digitally encoded data stream includes correlating a received bit transition in the data stream with a multitude of possible bit transitions to generate corresponding correlated bit transition values. A bit transition decision corresponding to a greatest correlated bit transition value is then generated for the received bit transition. Consecutive bit transition decisions generated for the data stream are compared to identify bit transition decision errors. Respective bit transition decisions are examined to determine if each decision is consistent with a prior adjacent bit transition decision in the data stream. If a bit transition decision error is identified, then the next greatest correlated bit transition decision is substituted for the bit transition decision in error.

Abstract: Method and apparatus for discovery of operational boundaries for shmoo tests. Specifically, a method of testing operational boundaries is described in one embodiment of the present invention. The method discloses the discovery of an operational range for a hardware device over a plurality of varying operating parameters. The operational range is discovered by testing points, as defined by the plurality of varying operating parameters, to discover an operational boundary of the device. The operational boundary comprises a plurality of boundary points that lie just outside of the operational range of the device. The operational boundary is discovered automatically and without testing all of a plurality of interior operational points within the operational boundary.

Abstract: The invention is a method and apparatus for compression of binary data. The signal is used before modulation to increase the effective transmission rate by compressing it prior to being encoded onto a magnetic tape or other storage media. The transition bits of the data have a bit period no smaller than the smallest bit period without increasing the maximum frequency. However, non-transition bits have a bit period smaller than that of the transitioning bits. Since there is at least one full bit period between any two transitions, the maximum frequency is unaffected and is used for synchronization. Noise in a transmission is masked using bit period information, and since no other transition can be valid until at least the transition bit period has passed, noise occurring before passage of the transition bit period does not result in an error.

Abstract: A system for controlling the effects of “glitching” on a high speed digital bus using one or more level sensitive latches. Reductions in the propagation of intermediate transitioning data results in reduced power consumption by the digital circuit, which is particularly important in wireless communication applications.

Abstract: A method and device for adaptive quantization of soft bits includes numerically sorting soft bits of an external data block having a log likelihood ratio distribution of the soft bits, each of the soft bits having a value, the sorted soft bits having extreme values, determining two point values in the log likelihood ratio distribution of the data block respectively located at a clipping distance away from each extreme value of the sorted soft bits, defining an adapted quantization range with a half-length equal to half of a difference between the two point values or with a half-length equal to a larger of two absolute values of the two point values, and placing each of the soft bits within a respective sub-range of the adapted quantization range. An adapted quantization range is determined whenever the log likelihood ratio distribution of the data block changes.

Abstract: Adjusting a clock signal includes receiving a data stream, detecting a bit in the data stream using a first amount of data in the data stream, adjusting the clock signal based on the detected bit, detecting the bit in the data stream using a second amount of data in the data stream, the second amount of data comprising more data than the first amount of data, and correcting the clock signal if a result of initial detecting differs from a result of subsequent detecting.

Abstract: An iterative decoding system for intersymbol interference (ISI) channels has a module for extracting bit reliabilities from a partial response (PR) channel, an iterative decoder, and a module for updating the bit reliabilities. A transmitter parses a data sequence into blocks that are encoded to generate a sequence of codewords. By encoding, a correlation among the bits of each codeword output to the PR channel is created. A maximum likelihood sequence detector (MLSD) in the receiver produces estimates of transmitted bits from samples of the output from the PR channel. The MLSD detector has a priori knowledge of typical error events that can occur during transmission through the channel. Along with the bit estimates, at each time instant the MLSD detector generates set of error event likelihoods.

Abstract: A method, in an oversampling clock and data recovery system, for detecting that sampling is stuck taking place at a data edge, by detecting a data edge in an early or a late region relative to a good region and incrementing a stuck early or stuck late counter; and if one counter reaching a maximum, setting a condition indicating that sampling is stuck taking place at a data edge. If a data edge is detected in the good region, or in each of an early and a late region in a single data period, the stuck counters are reset to zero. The detection of which stuck counter has reached a maximum can cause the moving of a sampling clock forward or backward, ending when a data edge occurs in a good region, or in each of an early region and a late region in a single data period.

Abstract: A data-decoding apparatus having bit-detecting section 4. In the apparatus, an RF signal is reproduced from a recording medium and converted to digital data. If the RF signal has a level (amplitude) equal to a comparator level, the bit-detecting section 4 outputs channel-bit data having logic level “0” or “1” in accordance with whether the sum of the amplitudes of the two RF signals respectively preceding and following that RF signal is higher or lower than the comparator level.

Abstract: The invention relates to a receiving circuit for receiving message signals, having a first sampler for converting the message signal into a first sampled signal by a first sampling method, having at least one second sampler connected in parallel with the first sampler for converting the message signal into a second sampled signal by a second sampling method, and having an analyzing unit for decoding the first sampled signal and/or the second sampled signal and checking them for errors.

Abstract: One aspect of the invention provides a novel scheme to improve channel jitter tolerance and perform data recovery across a serial data channel. In one implementation, the invention samples each data unit in the data channel multiple times and, using two data cycles, selects one of the samples as representative of the data unit. According to one aspect, the invention performs edge detection between adjacent data samples to determine the location of transitions between data units (bits). A representative data sample is chosen which is as far away as possible from the detected edge and the next expected edge and yet adjacent to, or equal to, the ideal current sample point. According to another aspect of the invention, as between two equally possible samples, the algorithm selects the sample which is furthest from the distribution of prior cycle edges.

Abstract: A signal generation unit (10, 20) for providing digital test signals for a device under test—DUT—(40) comprises a signal generator (10) for generating a digital test signal with defined timing. A controllable delay unit (20) receives and delays the digital test signal by a controllable variable time delay, whereby a control unit (35) controls the time delay of the delay unit (20) in order to induce a defined jitter function as well as a defined jitter spectrum to the digital test signal.

Abstract: A method and apparatus are provided for channel equalization with a digital finite impulse response (DFIR) filter using a pseudo random sequence. A readback signal of a pseudo random bit sequence is obtained. Samples are obtained from the readback signal of the pseudo random bit sequence. Tap gradients are calculated responsive to the obtained samples. The tap weights of the digital finite impulse response (FIR) filter are modified responsive to the calculated tap gradients. Dibit samples and error samples are obtained from the readback signal of the pseudo random bit sequence and applied to a tap gradients calculator. Tap gradients are calculated by a bitwise multiplier and accumulation tap gradient calculation circuit. An attenuation function attenuates the calculated tap gradients by a programmable attenuation value.

Abstract: In multi-carrier communication, error amounts, which are deviations between the coordinate points of eye patterns detected from actual reception signals of each sub-carrier, and the target coordinate points of eye patterns from the reception signals are calculated by an eye pattern display controller and displayed on an oscilloscope.

Abstract: Hashes are short summaries or signatures of data files which can be used to identify the file. Hashing multimedia content (audio, video, images) is difficult because the hash of original content and processed (e.g. compressed) content may differ significantly.

Abstract: A method for use in connection with any kind of detector that receives an input signal via a partial-response channel and which provides a detector output signal and a merge-bit signal. According to the present scheme, the colored noise of the input signal is whitened in order to provide a filtered signal. The filtered signal is filtered to provide a first output signal using a first matched filter and a second output signal using a second matched filter. The merge-bit signal is used to adjust the first matched filter to match a first most likely error event and to adjust the second matched filter to match a second most likely error event. It is then determined whether said first likely error event or said second likely error event is the most likely error event, and the actual errors of detector output signal are corrected using said most likely error event.

Abstract: A data decoding scheme operates on individual code symbols within an encoded data stream, enabling data to be recovered from the code symbols at a high rate. The decoding scheme, typically included within a receiver of a digital communication system or data network, does not rely on processing and storing multiple code symbols and is unencumbered by storage memory elements and decoding rate limitations associated with receiving and processing blocks of multiple code symbols. The decoding scheme generates bit sequences corresponding to each alternate data state of a received code symbol. Error vectors are generated as a result of comparing each of the generated bit sequences to the received code symbol. The data state of data represented by the code symbol within the encoded data stream is recovered from the code symbol by selecting the minimum of the generated error vectors.

Abstract: An error processing circuit for a receiving location of a system for transferring binary data in the form of pulse sequences, wherein the system has a number of receiving locations connected via a double-line bus having a first line and a second line. The circuit includes a data output, a decoder having three decoder outputs, of which a first decoder output associated with both lines delivers a first decoder output signal dependent on the difference between the potential values of both lines, a second decoder output associated with the first line delivers a second decoder output signal dependent on the difference between the potential value of the first line and a first mean potential value, and a third decoder output associated with the second line delivers a third decoder output signal dependent on the difference between the potential value of the second line and a second mean potential value.

Abstract: An apparatus for detecting data within a signal having both data and noise is disclosed herein. The apparatus includes means for receiving first samples of an input signal, a first detection unit and a second detection unit. The first detection unit processes the first data samples to create a first bit signal, a second bit signal and a probability related signal. The second detection unit includes first and second modification units and a selection unit. The first and second modification units separately modify the first data samples based on the first and second bit signals, respectively, to create first and second error signals, respectively. The selection unit selects one of the first and second bit signals based on the first and second error signals and a threshold signal.