Abstract: A built-in self test (BIST) circuit and method is provided for testing semiconductor memory. A linear feedback shift register (LFSR) is used for addressing the memory locations to be tested. Test data is derived at least partially from the address data generated from the linear feedback shift register.

Abstract: This patent describes a boundary scan system where memories, i.e. flip flops or latches, used in data scan cells are also used functionally, but memories used in control scan cells are dedicated for test and not used functionally. The control scan cells can be scanned while the circuit is in functional mode, since their memories are dedicated. However, the data scan cells can only be scanned after the circuit transitions into test mode, since their memories are shared. This boundary scan system advantageously provides; (1) lower test circuitry overhead since the data scan cells use shared memories, (2) safe entry into test mode since the control scan cells can be scanned during functional mode to pre-load safe control conditions, and (3) avoidance of floating (i.e. 3-state) busses that can cause high current situations.

Abstract: The invention provides a semiconductor integrated circuit device that includes a combination circuit incorporated in a chip, plural input pads and output pads, and a shift register made up with plural SFFs in which the input pins and output pins of the consecutive SFFs are connected, respectively, to the input pads and the output pads directly or via the combination circuit. In this configuration, the output pads and the input pads are connected to each other inside the chip to thereby form a test path.

Abstract: There is provided a boundary-scan test device incorporated into a semiconductor integrated circuit for running self-diagnostics on the semiconductor integrated circuit. The device comprises a bypass unit for, when a package in which the semiconductor integrated circuit is assembled does not have one or more corresponding external input/output pins associated with one or more predetermined boundary-scan registers, changing the length of a boundary-scan register chain that consists of a plurality of boundary-scan registers by bypassing the one or more predetermined boundary-scan registers according to a bypass control signal applied thereto.

Abstract: An address generator provides for generation of addresses for a plurality of different tests by allowing for primitive polynomial-based pseudo-random bit-streams to be shifted into the address generator. Embodiments of the present invention utilize the address values to generate data values to be stored in a memory under test. Likewise, an expected data value is generated and compared to the stored value. A data comparator verifies the stored data to the expected value. A single latch stores compare results for a plurality of memory locations.

Abstract: A system for testing a number of integrated circuit (IC) devices under test (DUTs) having interface circuitry coupled to a single or multi-channel tester for receiving data values from the tester and providing error information concerning the DUTs. The interface circuitry forwards data values (received from the tester over a single channel) to a number of DUTs in parallel. The circuitry performs comparisons using data values read from the DUTs, and in response generates error values indicative of the comparison. The error values may then be returned to the tester over the same or a different channel.

Abstract: An integrated circuit having a central built-in self-test unit (BIST) that uses internal scan chains for testing embedded memory modules. The embedded memory modules receive address and data signals from a set of input flip-flops configured to form a scan chain. The BIST is coupled to an input scan chain and includes a pattern generator to shift a test pattern into the input scan chain for testing the embedded memory modules. Output flip-flops capture data from the embedded memory modules are also configured as a scan chain. The BIST includes address control logic to bypass the normal addressing logic of the embedded memory module when the BIST operates is operating in a memory test mode.

Abstract: A semiconductor device having multiple memory circuits of varying sizes includes scan test circuitry that enables the memories to be simultaneous loaded with pattern data and tested. A first memory circuit has a first memory, a first address scan chain that receives serial scan-in address data and generates a first address signal, and a first data scan chain that receives serial scan-in data and generates a first data input signal. A second memory circuit has a second memory, a second address scan chain that receives the serial scan-in address data and generates a second address signal, and a second data scan chain that receives the serial scan-in data and generates a second data input signal.

Abstract: An integrated circuit is presented having a plurality of logic modules dispersed about a surface of a semiconductor substrate. Each logic module includes a set of control and status registers including at least one control register storing a control value. A functional unit of each logic module performs one or more logic functions dependent upon the control value stored in the control register. A central controller is coupled to the each of the logic modules. The central controller is adapted to receive address, data, and control signals (e.g., from signal lines of an external bus coupled to I/O pads of the integrated circuit), and issues read/write commands to read/write the control and status registers dependent upon the address, data, and control signals. A write command may, for example, modify the control value stored in a selected one of the control registers. The integrated circuit may include a bus which couples the central controller to each of the logic modules.

Abstract: A semiconductor integrated circuit device with fault analysis function performs test operation for a memory circuit (such as a RAM) in which a comparison control circuit (6) generates a comparison control signal CCMP in order to select one or more memory cells in each memory cell group (34, 35, 36 and 37) corresponding to a single bit, a specified row, a specified bit, or a specified pattern, and then outputs the comparison control signal CCMP to scan flip flops (2, 3, 4 and 5) each including a comparator (292). The comparator (292) performs the comparison operation between data and expected values EXP and then outputs a comparison result only when address signals are input and data are red from memory cells, as the object of test, addressed by these address signals.

Abstract: In a method for checking the functioning of memory cells of an integrated semiconductor memory, a first group of the memory cells is tested. The test results, separately for each tested memory cell, are buffer-stored in at least triple copies in a second group of the memory cells. A comparison is made between the copies of each of the test results and the evaluation thereof. The addresses of the respective memory cells of the second group are determined by an address transformation. The latter is configured in such a way that significant clusters of functional errors in an error-affected second group of the memory cells do not influence the result of the test method.

Abstract: A multiport testing procedure capable of detecting faults that occur between static random access memory ports as well as traditional cells faults uncovers all possible faults and covers all cells in the memory, without placing architectural constraints on the memory. While executing a test sequence on one port of the memory array, concurrent memory accesses are performed through other ports in the memory. If a fault exists between the port under test and any other port, then the concurrent operations interfere with the values read and/or written on the port under test, and the test uncovers the fault. Thus, for any one test port, the interport test requires only as many memory operations as the associated single port test, keeping test time to a minimum. One embodiment detects faults between the test port, which is a read/write port, and any other port, including read ports and write ports, comprising six passes through the memory.

Abstract: A system for testing integrated circuit chips is comprised of a pattern generator that is coupled to a memory which stores variable length instructions that specify sets of bit streams for testing the chips. Each variable length instruction includes a code which indicates the number of bit streams in the set. Each bit stream in the set consists of a selectable number of bits which start on a word boundary and vary in increments of one bit. If the code indicates that the number of bit streams in a set is only one, then that one bit stream is stored in consecutive words of the memory. If the code indicates the number bit streams in a set is more than one, then those multiple bit streams are stored in an interleaved fashion in consecutive words in the memory. A respective series of unused bits starts immediately after each bit stream and ends on a word boundary.

Abstract: A new built-in self-test architecture for multiple memories in a chip is proposed in the present invention. In this architecture, all memories under test are tested in parallel using only one address generator. When the address generated from the address generator exceeds one memory's address space the memory is turned off by a BIST controller. Each word in each memory is tested by a scan-in/out method. That is, the D flip-flops in the input and output ports of each memory are connected in series and form two scan chains, respectively. Only one data input and one data output are required for the scan chains of each memory. The outputs of all scan chains are connected to a self checker for fault analysis in parallel. The address generator, data generator, self checker and the test controller are all built in a chip to satisfy the requirement of built-in self-testing.

Abstract: An event based test system for testing an electronics device under test (DUT) by supplying a test signal to the DUT and evaluating an output of the DUT at a timing of a strobe signal. The event based test system includes an event memory for storing timing data of each event which represents a time difference between two adjacent events, an address sequencer for generating address data for accessing the event memory, a timing count logic for summing the timing data to produce an overall time of each event relative to a predetermined reference point, an event generation circuit for generating each event based on the overall time for formulating the test signal or strobe signals, and a host computer for controlling an overall operation of the event based test system.

Abstract: A semiconductor memory device includes a plurality of scan flip-flops connected in series for storing parallel data externally provided in a normal operation mode and for storing serial data externally provided in a scan mode by shifting the serial data. The semiconductor memory device further includes a control circuit which controls the plurality of scan flip-flops to refrain from shifting the serial data when data-read operations and data-write operations are conducted in the scan mode.

Abstract: A method of configuring scan mode circuitry of an integrated circuit (IC) device includes parsing through an initial file of the scan-flops that are to be included in the scan mode circuitry. The initial file can be prepared with a synthesis tool such as Synopsys. A particular subset of scan-flops are parsed, according to an identified number to be included in each scan chain. A holding tank is created to hold each subset of scan-flops for each scan chain. Each holding tank is then used to form a scan path and to stitch the corresponding scan chain. The parsing of the scan-flops into holding tanks can be performed with a c-shell script. Also, the c-shell script can be called by a Synopsys dc_shell script.

Abstract: A programmable logic device is provided that contains circuitry that may be used for observing logic signals from programmable logic circuits on the device for testing the operation of the device. Circuitry is also provided that may be used for preloading data into various circuits on the device. The logic signal observing circuitry may allow registered signals to be observed, may allow combinatorial signals to be observed, or may allow both registered and combinatorial signals to be observed.

Abstract: A memory address generator having a small chip area, a method for generating a memory address and a SRAM built-in self test (BIST) circuit using the same are described. When the number of addresses of a memory to be tested is 2.sup.n, where n is the number of bits in an address, the address generator includes an up counter for generating a first address of a series of sequentially increasing addresses, and an inverter for inverting the first address to generate a second address of a series of sequentially decreasing addresses. The address generator also includes a selector for selecting one of the first and second addresses, in response to a control signal, to output the selected address as an address of the memory. When the number of addresses of the memory to be tested is not 2.sup.

Abstract: A bus control logic circuit is provided that may be tested for a variety of bus fault conditions including no-connection faults, cross-connection faults and bus-contention stuck faults. The bus control logic circuit operates in a normal mode and in a test mode. In the normal mode, the bus control logic circuit operates as a conventional driver decoder and is testable for no-connection faults and cross-connection faults. In the test mode, the bus control logic circuit also is testable for bus-contention stuck faults. To test for bus-contention stuck faults, drivers having addresses of a first parity are hard disabled and one of the hard disabled drivers is addressed. Because the addressed driver is hard disabled, the only driver that can be enabled is a non-addressed driver erroneously enabled due to a bus-contention stuck fault. To detect the bus-contention stuck fault, the signal line is placed in a known logic state that only changes if a driver is erroneously enabled due to a bus-contention stuck fault.

Abstract: A method and system for testing a plurality of addressing modes in a microprocessor comprising executing a test instruction which is stored in memory, subsequently overwriting the test instruction in memory and then re-executing the test instruction. The test instruction is stored at a memory location which is within a code segment. A data segment is defined to overlap with the code segment and a portion of the test instruction is overwritten by storing data within the overlapping data segment. The overwritten portion of the test instruction identifies the addressing mode of the test instruction and the stored data represents the next addressing mode to be tested. In an x86 architecture, the overwritten portion of the test instruction may comprise a MODR/M byte and an SIB byte, each of which may take on values from 00 to ff (hexadecimal). The addressing modes of the microprocessor may therefore be tested by sequentially incrementing the MODR/M and SIB bytes and executing the test instruction.

Abstract: Boundary Scan integrated circuits are provided with a plurality of new registers between two dedicated pins, Test Data In (TDI) and Test Data Out (TDO) pins. The new registers include an address register and a plurality of test data registers which are addressable by the address register using address-dependent instructions in the instruction register (IR). Instructions for the addressable registers may be steered to the correct register with an ADDLOAD instruction placed in the instruction register followed by an address-dependent instruction. The ADDLOAD instruction makes the address register active between the TDI and TDO pins. Any instruction from a set of address-dependent instructions may be steered to any register handling address-dependent instructions allowing a small number of instructions to be used in a large number of addressable data registers. At the same time non-addressable registers, such as the Boundary Scan register, use address-independent instructions.

Abstract: A digital system includes a number of digital subsystems interconnected by a shared bus structure that is mutually exclusively accessible for communicating data between the subsystems. The system is structured to be tested by pseudo-random scan test methodology. Each subsystem includes a counter that, during scan test periods, provides an enable signal to the bus access or driver circuitry of the associated subsystem. A scan test operation is preceded by pre-loading each counter with a predetermined state so that, initially, and throughout the test period, one and only one digital subsystem will drive the shared data bus. Each scan sequence (comprising a scan in, an execution cycle, and a scan out of the pseudo-random test strings) will result in the counters being clocked once so that a new subsystem will be enable to drive the bus the next sequence, permitting the bus access circuitry of each subsystem, and the bus itself, to be tested.