Abstract: A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks, to share a test access mechanism. During test mode, the test architecture is configured to decouple clock sources of the test access mechanism, the scan controllers and the scan chains.

Abstract: A test apparatus includes a bus switch unit capable of switching the output ports to select which of the output ports an input signal is output from, a control unit for inputting a plurality of control signals, according to a test program for testing the electronic device, to the bus switch unit and controlling which of the output ports each of the control signals is output from, a plurality of slots provided corresponding to the plurality of output ports, and a device interface capable of switching the connectors, which couple the plurality of slots and the electronic device, to select which of the connectors the slot is coupled to, wherein the device interface further includes a diagnosis decoder for sequentially supplying each of the test modules with a diagnosis signal via each of the connectors, and the control unit detects which of the test modules the diagnosis signal received via each of the connectors is supplied to and which of the connectors each of the output ports is coupled to based on a result

Abstract: A method for testing at least two arithmetic units installed in a control unit includes: loading of first test data for testing a first arithmetic unit; saving the loaded first test data in a second memory unit of a second arithmetic unit; switching the first arithmetic unit to a test mode, in which a first scan chain of the first arithmetic unit is accessible; reading the first test data from the second memory unit; shifting the first test data which have been read through the first scan chain of the first arithmetic unit switched to the test mode for providing test result data for the first arithmetic unit; checking the provided test result data for plausibility for providing a test result for the first arithmetic unit.

Abstract: Disclosed is a system and method for disk drive grouping in a multi-cell disk drive test system. A test platform includes a plurality of cells. Each cell is configured to receive and to provide communication with a disk drive. An automated loader/unloader is coupled to a test computer and is responsive to the test computer. The automated loader/unloader is configured to identify disk drives and to selectively load and unload disk drives into and out of the plurality of cells. Particularly, once the automated loader/unloader has identified a first disk drive, the test computer is configured to: determine a grouping criteria based upon the first disk drive; detect a subsequent disk drive having the same grouping criteria as the first disk drive; and cause the automated loader/unloader to load the subsequent disk drive into one of the plurality of cells.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: A circuit testing apparatus for testing a device under test is disclosed. The device under test comprises a first output end and second output end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines a test result for the device under test according to the first output signal and the second output signal.

Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.

Abstract: There is presented a system and method for characterizing an integrated circuit (IC) for comparison with a pre-defined system-level characteristic related to an aspect of IC operation, wherein a test procedure on the IC that invokes this aspect is executed, while at least one operational bottleneck is invoked to constrain operation of the IC to exhibit a system-level operation thereof related to the aspect. Data generated via the test procedure in response to the bottleneck is collected and the system-level operation exhibited thereby is compared for consistency with the pre-defined system-level characteristic.

Abstract: A method, apparatus and program product improve computer reliability by, in part, identifying a plurality of error occurrences from Error Correction Codes. It may then be determined if the plurality of error occurrences are associated with a single bit of a bus. The determined, single bit may correspond to a faulty component of the bus. This level of identification efficiently addresses problems. For instance, a corrective algorithm may be applied if the plurality of error occurrences are associated with the single bit. Alternatively, the bus may be disabled if the plurality of error occurrences are not associated with the single bit of the bus. In this manner, implementations may detect, identify and act in response to multiple failure modes.

Abstract: A system and method for testing a processor. The system includes a gold processor and a test processor, wherein the test processor is the device under test (DUT). The test processor and the gold processor are identical. A first memory is coupled to the gold processor by a first memory bus and a second memory, independent of the first, is coupled to the test processor by a second memory bus. The first and second memories are identical. A memory bus comparator coupled to the first and second memory buses compares memory bus signals generated by the gold and test processors, and selectively provide a first indication if a mismatch occurs. A peripheral bus comparator is also coupled to the gold and test processors, and compares downstream transactions generated by the gold and test processors and to provide a second indication if a peripheral bus comparison results in a mismatch.

Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.

Abstract: An apparatus comprising a processor and an internal memory. The processor may be configured to test an external memory using (i) a netlist and (ii) a testing program. The internal memory may be configured to store the testing program. The testing program may be downloadable to the internal memory independently from the storing of the netlist.

Abstract: Techniques are provided for modeling memory operations when generating test cases to verify multi-processor designs. Each memory operation has associated therewith a set of transfer attributes that can be referenced by a test generator. Using the transfer attributes, it is possible to generate a variety of interesting scenarios that handle read-write collisions and generally avoid reloading or resources. The model provides accurate result prediction, and allows write access restrictions to be removed from sensitive memory areas, such as control areas.

Abstract: A method, system and computer program product for performing device characterization Logic Built-In Self-Test (LBIST) in an IC device. Test parameters of the LBIST are saved in a memory of the IC device, and nominal operational parameters of the IC device are used to define a signature of the LBIST. A determination whether the LBIST is passed or failed is made within the characterized IC device.

Abstract: A method for checking expected network traffic is disclosed. The method for checking expected network traffic includes accessing pre-registered expected results of a network traffic checking exercise that include expected packet content verification information for individual packets of the network traffic. In addition, the method includes accessing network traffic where individual packets of the network traffic include actual packet content verification information. Individual packets are identified that have expected packet content verification information that does not match their actual packet content verification information and individual packets are identified that have expected packet content verification information that does match their actual packet content verification information.

Abstract: Methods, apparatus and systems are provided that enable the generation of random regression suites for verification of a hardware or software design to be formulated as optimization problems. Solution of the optimization problems using probabilistic methods provides information on which set of test specifications should be used, and how many tests should be generated from each specification. In one mode of operation regression suites are constructed that use the minimal number of tests required to achieve a specific coverage goal. In another mode of operation regression suites are constructed so as to maximize task coverage when a fixed number of tests are run or within a fixed cost.

Abstract: Disclosed is an arrangement for testing an embedded circuit as part of a whole circuit located on a semiconductor wafer. Disclosed is an integrated semiconductor arrangement comprising a whole circuit (8) with inputs and outputs (7), an embedded circuit (1) that is part of the whole circuit (8) and is equipped with embedded inputs and outputs which are not directly connected to the inputs and outputs (7) of the whole circuit (8); a test circuit (2, 5, 6) that is connected to the embedded inputs and outputs in order to feed and read out signals during a test phase. A separate supply voltage connection (3) is provided which is used for separately supplying the embedded circuit (1) and the test circuit (2, 5, 6) independently of a supply voltage of the whole circuit (8) such that the inputs of the whole circuit do not have to be connected for testing the embedded circuit while only the inputs and outputs that are absolutely indispensable for testing the embedded circuit need to be connected to a test system.

Abstract: A method, system and computer program product for performing real-time LBIST diagnostics of IC devices. During LBIST, stump data and identifiers of test cycles are saved in the IC device-under-test (DUT). If compressed stump data does not match a pre-defined coded value (i.e., “signature” of the test cycle), the saved stump data and an identifier of the failed test cycle are preserved, otherwise the determination is made the DUT passed the test cycle. Identifiers and stump of the failed test cycles are used to analyze errors, including virtually non-reproducible errors.

Abstract: A semiconductor integrated circuit system has a control target circuit executing a program, a system information monitor unit for outputting system information indicating a state of the control target circuit, a circuit characteristic monitor unit for determining a circuit characteristic of the control target circuit and outputting the circuit characteristic as circuit characteristic information, a malfunction determination unit for determining whether or not the control target circuit is normally operating based on the system information, a reference circuit characteristic holding unit for holding the circuit characteristic information as reference circuit characteristic information when the control target circuit is normally operating, a malfunction factor determination unit for determining a malfunction factor based on the circuit characteristic information and on the reference circuit characteristic information when the control target circuit is not normally operating, and a correction target determinatio

Abstract: Disclosed are embodiments of a system, method and service for detecting and analyzing systematic conditions occurring in manufactured devices. Each embodiment comprises generating a unique signature for each of multiple tested devices. The signatures are generated based on an initial set of signature definitions and the values for those signature definitions that are derived at least in part from selected testing data. A systematic condition is detected based on commonalities between the signatures. The systematic condition is then analyzed, alone or in conjunction with additional information, in order to develop a list of underlying similarities between the devices. The analysis results can be used to refine the systematic condition detection and analysis processes by revising the signature definitions set and/or by modifying data selection.

Abstract: Provided is a method and system for testing a DUT. The system includes a plurality of testing devices for interacting with the DUT and conducting a plurality of different tests on the DUT, and a computer-readable memory for storing computer-executable instructions defining the plurality of tests to be conducted by the testing device on the DUT. A scheduler component designates at least a first test and a second test from the plurality of tests to be conducted on the DUT in parallel, wherein said designating is based at least in part on content of the computer-executable instructions defining the first test and the second test. And a controller initiates the first test and the second test to be conducted in parallel and initiating at least a third test sequentially relative to at least one of the first and second tests.

Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.

Abstract: Embodiments described herein relate to systems and methods for testing integrated circuit devices within an environment that is representative of the application environment in which an integrated circuit device will be used. In at least one embodiment, the testing system comprises a second reference integrated circuit device that provides flexibility in testing, allowing only the input to a first reference integrated circuit device of an application system to be tapped and not necessarily both input to and output from the first reference integrated circuit device to be tapped. In some embodiments, the input to the first reference integrated circuit device may be subsequently modified by a controller.

Abstract: A semiconductor integrated circuit device includes: a plurality of devices under test formed on a substrate; a selection circuit formed on the substrate which selects two of the plurality of devices under test; a magnitude comparison circuit formed on the substrate which measures an electrical characteristic of the two selected devices under test and makes a magnitude comparison between values of the measured electrical characteristic; an address memory circuit formed on the substrate which stores addresses of the two devices under test between which the magnitude comparison has been made; and a control circuit formed on the substrate and connected to the selection circuit, the magnitude comparison circuit, and the address memory circuit.

Abstract: A fault location estimation system includes single-fault-assumed diagnostic unit nodes; error-observation node basis candidate classification unit; inclusion fault candidate group selection unit; inter-pattern overlapping unit; and multiple-fault simulation checking unit.

Abstract: A network device, such as a router or switch, has a CPU and a memory operable to receive, store and output computer code. The code includes device configuration files, traffic pattern files, and standard-behavior-output template files adapted for detecting network device functional defects and bottlenecks. The device is operable in a testing mode to act as either a Device Testing Doctor (DTD) or a Device Under Test (DUT), in which it loads into or accepts from a related, interconnected and similarly configured and operable network device selected ones of the device configurations, transmits to or receives from the other device selected ones of the input traffic patterns, compares its own output or that of the other device in response to the input traffic pattern with selected ones of the standard-behavior-output templates, and detects a network device defect or bottleneck in itself or in the other device based on the comparison.

Abstract: Chain or logic diagnosis resolution can be enhanced in the presence of limited failure cycles using embodiments of the various methods, systems, and apparatus described herein. For example, pattern sets can be ordered according to a diagnosis coverage figure, which can be used to measure chain or logic diagnosability of the pattern set. Per-pin based diagnosis techniques can also be used to analyze limited failure data.

Abstract: A method, apparatus and computer program product are provided for use in a system that includes one or more processors, and multiple threads that are respectively associated with the one or more processors. One embodiment of the invention is directed to a method that includes the steps of generating one or more test cases, wherein each test case comprises a specified set of instructions in a specified order, and defining a plurality of thread hardware allocations, each corresponding to a different one of the threads. The thread hardware allocation corresponding to a given thread comprises a set of processor hardware resources that are allocated to the given thread for use in executing test cases. The method further includes executing a particular one of the test cases on a first thread hardware allocation, in order to provide a first set of test data, and thereafter executing the particular test case using a second thread hardware allocation, in order to provide a second set of test data.

Abstract: Among the various embodiments described is a method of detecting defects in a cell of an integrated circuit that analyzes exercising conditions applied to an input of the cell during a capture phase of testing with failed test patterns that produce an indication of a fault and that analyzes the exercising conditions that are applied during a capture phase of testing with observable passing patterns that do not provide an indication of a fault. From the analysis, true failing excitation conditions and passing excitation conditions can be determined and used to identify whether a defect is in the cell or on an interconnect wire of the integrated circuit.

Abstract: A reconfigurable high performance computer includes a stack of semiconductor substrate assemblies (SSAs). Some SSAs involve FPGA dice that are surface mounted, as bare dice, to a semiconductor substrate. Other SSAs involve memory dice that are surface mounted to a semiconductor substrate. Elastomeric connectors are sandwiched between, and interconnect, adjacent semiconductor substrates proceeding down the stack. Each SSA includes a local defect memory and a self-test mechanism. The self-test mechanism periodically tests the SSA and its interconnects, and stores resulting defect information into its local defect memory. The computer is configured to realize a user design and then is run. A defect is then detected. If the defect is determined to be in a part of the computer used in the realization of user design, then the computer is reconfigured not to use the defective part and running of the computer is resumed, otherwise the computer resumes running without reconfiguration.

Abstract: An integrated circuit is used to monitor and process parametric variations, such as temperature and voltage variations. An integrated circuit may include a temperature-sensitive oscillator circuit and a temperature-insensitive oscillator circuit, and frequency difference between the two sources may be monitored. In some embodiments, a parametric-insensitive reference oscillator is used as a reference to measure frequency performance of a second oscillator wherein the second oscillator performance is parametric-sensitive. The measured frequency performance is then compared to a tamper threshold and the result of the comparison is indicative of tampering.

Abstract: The present invention provides a method for digitally obtaining contours of fabricated polygons. A GDS polygon described in a Geographic Data System (GDS) file is provided. Based on the GDS polygon, a plurality of identical polygons is fabricated with the same fabrication process such that shapes of the plurality of identical polygons are altered by optical effects in the same or similar way. The plurality of identical polygons forms poly-silicon gates of a plurality of test transistors. The position of source and drain islands along a length of a poly-silicon gate for each of the plurality of test transistors is different. Using Automated Test Equipment (ATE), a digital test is performed on a circuit including the plurality of test transistors to obtain test responses, the test responses being raw digital data. The test responses may be displayed in a histogram reflecting a contour of the plurality of identical polygons or post-processed to reconstruct a contour of the plurality of identical polygons.

Abstract: A method including obtaining an operational status of a first processor core, where the first processor core is associated with a plurality of processor cores located on a chip; configuring a first IO block of a package design based on the operational status of the first processor core, where the package design is based on a fully functional chip; and configuring a stackup of the package design after configuring the first IO block for use with the chip.

Abstract: An electronic system comprises a processor, a diagnostic port, and a switching circuit, including a switch connected between the diagnostic port and the processor, for enabling and disabling the diagnostic port and for restricting access to contents of the electronic system prior to enabling the diagnostic port. A method for operating the electronic system is also included.

Abstract: An electronic device includes a scan-based circuit that includes a combinational decompressor, a combinational compressor, scan chains, and logic which typically includes a number of storage elements. Cycle time normally needed to shift data into or out of a scan cell to/from an external interface of the electronic device is reduced by use of one or more additional storage element(s) located between the external interface and one of the combinational elements (decompressor/compressor). The one or more additional storage element(s) form a pipeline that shifts compressed data in stages, across small portions of an otherwise long path between the external interface and one of the combinational elements. Staged shifting causes the limit on cycle time to drop to the longest time required to traverse a stage of the pipeline. The reduced cycle time in turn enables a corresponding increase in shift frequency.

Abstract: A verification scenario generation device including a first input unit which accepts input of a device list showing devices connected with a circuit to be verified, parameter setting information for the devices, and a test bench combination list corresponding to the devices, a test bench library which holds the test bench, and a test bench generation unit to generate a test bench for verification, a scenario template generation unit which generates a scenario template. The device further includes a data combination list generation unit which generates a combination list of data kinds, a verification item generation unit which generates verification items based on a combination list of the data kind and a combination list of the test bench input, and a verification scenario generation unit which generates a verification scenario based on the scenario template, and the verification items.

Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. In one or more embodiments, the test module can include a linear-feedback shift register.

Abstract: A high-speed signal testing system that includes a digital circuitry for providing a pattern tester with oscilloscope functionality at minimal implementation cost. The digital circuitry includes a time-base generator that provides a high-speed repeating time-base signal. The time-base signal, in conjunction with a sub-sampler and an accumulation memory, allows the system to zoom in on, and analyze portions of, one or more bits of interest in a repeating pattern present on the signal under test. Such portions of interest include rising and falling edges and constant high and low bit values.

Abstract: Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

Abstract: A seed generator for a scrambler comprises a seed set identifier that identifies a seed set based on received user data symbols, which include a plurality of M-bit symbols. A seed selector selects a scrambling seed for the scrambler from the seed set based on Hamming distances between at least two of the M-bit symbols in the seed set.

Abstract: A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

Abstract: A testing system for a device under test (DUT) includes a test parameter-generating device and a platform module. The test parameter-generating device stores test information, and is operable so as to execute a test algorithm, so as to generate a transmission signal upon execution of the test algorithm, and so as to generate a test environment with reference to the transmission signal. The platform module is operable so as to conduct testing of the DUT using the test information stored in the test parameter-generating device under the test environment generated by the test parameter-generating device.

Abstract: A method and a system for defining groups of tests that may be concurrently performed or overlapped are provided. Channel-independent test groups are determined such that each group includes tests that the input/output channels may be utilized simultaneously without conflicts. The channel-independent test groups are divided into block-under-test (BUT) conflict test groups and total-independence test groups. The total-independence test groups may be performed concurrently. Performance of the BUT-conflict test groups may be overlapped such that the input/output channels are used concurrently, but the execution of the tests by the blocks of the device-under-test (DUT) is performed sequentially.

Abstract: A test apparatus tests a device under test. The test apparatus includes a period generator that generates a rate signal determining a test period according to an operating period of the device under test, a phase comparing section that inputs an operational clock signal for the device under test generated from the device under test and detects a phase difference between the operational clock signal and the rate signal using the rate signal as a standard, a test signal generating section that generates a test signal to be supplied to the device under test in synchronization with the rate signal, a delaying section that delays the test signal in accordance with the phase difference to substantially synchronize the delayed signal with the operational clock signal, and a test signal supplying section that supplies the delayed test signal to the device under test.

Abstract: A method and system for testing a semiconductor memory device using low-speed test equipment. The method includes providing a high-frequency test pattern by grouping a command signal and an address signal into command signal groups and address signal groups each corresponding to L cycles of a clock signal output from automatic test equipment (ATE) where L is a natural number. A valid command signal and a valid address signal, which are not in an idle state, are extracted from each of a plurality of command signal groups and each of a plurality of address signal groups. The valid command signal and the valid address signal are compressed into signals having a length corresponding to 1/M (M is a natural number larger than 1) of the cycle of the clock signal where M is a natural number larger than 1. A position designating signal indicating the positions of the valid command signal and the valid address signal in each command signal group and each address signal group is generated.

Abstract: Consensus testing of electronic system. A tester (112) for testing an electronic system (100) includes: a traffic interface (114) to receive traffic (102) from a test of an electronic system (100); an element comparator (118) to extract a value from an element of the traffic (102) and to compare the extracted element value with an element value (110) obtained from another test of another electronic system (104, 106, 108); and a test result generator (122) to generate consensus information (124) on the interoperability of the electronic system (100), based on comparing (120) the extracted element values of the electronic system (100) with the element values obtained from the other test of the other electronic system (104, 106, 108).

Abstract: A system that generates test patterns for detecting transition faults in an integrated circuit (IC). During operation, the system receives slack times for each net in the IC. Note that a slack time for a net is the minimum amount of delay that the given net can tolerate before violating a timing constraint. For each possible transition fault in the IC, the system uses the slack times for nets in the IC to generate a test pattern which exposes the transition fault by producing a transition that propagates along the longest path to the transition fault.

Abstract: A method, system and computer readable medium for on-chip testing is presented. In one embodiment, the method, system or computer readable medium includes identifying which LBIST channels of a plurality of LBIST channels do not contribute to a particular test and excluding from that particular test each LBIST channel that does not contribute to that particular test.

Abstract: A chip testing device having a plurality of testing units is provided. Each testing unit comprises a selector, a flip-flop unit, a first buffer and a second buffer. The selector is controlled by a control signal and has a first input terminal, a feedback input terminal, and a first output terminal. The flip-flop unit has a second input terminal coupled to the first output terminal, a clock signal input terminal for receiving a reference clock signal, and a second output terminal outputting an output data. The first buffer is coupled to the flip-flop unit to convert the output data to a high voltage data, and outputs the high voltage data. The second buffer is coupled to the first buffer to convert high voltage data to low voltage data and transmit the low voltage data to the feedback input terminal.