Abstract: Methods, apparatuses and systems are disclosed for preserving, verifying, and correcting data in DRAM device during a power-saving mode. In the power-saving mode, memory cells in the DRAM device may be refreshed using a self-refresh operation. This self-refresh operation may allow bit errors to occur in the DRAM device. However, by employing error correction coding (ECC), embodiments of the present invention may detect and correct these potential errors that may occur in the power-saving mode. Furthermore, a partial ECC check cycle is employed to check and correct a sub-set of the memory cells during a periodic self-refresh process that occurs during the power-saving mode.

Abstract: The invention concerns a method (500) for tracking sequence numbers. The method includes the steps of detecting (512) an error in a first set of data (120), determining (514) a range (144) of possible sequence numbers (122) for a second set of data (120) and using the range of possible sequence numbers, producing (516) a block code (126) for the second set of data in which the block code is used to verify that one of the range of possible sequence numbers is a correct sequence number for the second set of data.

Abstract: An electronic radio frequency (RF) identification system 10 is disclosed and claimed. The system includes an interrogator 11 and a plurality of RF transponders 12.1 to 12.n. In use, each transponder is operative in response to an interrogation signal 14 to respond with a forward error correctable data message 16.1 including base data encoded as symbol characters in accordance with a forward error correcting code, such as a Reed Solomon Code, and check characters on the base data as defined in the forward error correcting code. The interrogator 11 utilizes data relating to the forward error correcting code, the symbol characters and check characters in the received forward error correctable data message, to reconstruct the base data in the event of corruption of the forward error correctable data message during transmission.

Abstract: A host controller interface to manage the complexity of accessing mass storage that takes into account the special handling needs of various memory technologies such as polymer memories.

Abstract: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Abstract: An error detection and correction circuit is connected to at least one memory bank of a CAM device. During background processing (i.e., when the CAM is not performing reading, writing or searching functions) the error detection and correction circuit tests all of the CAM locations that it is connected to in sequence. If an error is detected, the error detection and correction circuit rewrites the CAM location with the correct data. Multiple error correction and detection circuits can be used in the CAM device to test multiple CAM locations simultaneously.

Abstract: A DRAM memory has a reduced refresh rate in a sleep mode to conserve power. Error Correction Codes (ECC) are used to correct errors that may arise due to the reduced refresh rate. ECC encoding occurs at the time of entering the sleep mode and ECC decoding for error detection and correction need only take place upon wake up when resuming active mode. In addition, the memory system reassigns a portion of the memory for storing the additional parity bits required for the error correcting code (ECC).

Abstract: In a UMTS (universal mobile telecommunications system) based system, a wireless receiver comprises a convolutional decoder, a processor and memory. The convolutional decoder processes a received signal and provides a Yamamoto-Itoh (YI) metric to the processor. The processor (a) retrieves, from a look-up table stored in the memory, a compensation factor as a function of the YI metric value provided by the Viterbi decoder; (b) retrieves, from another look-up table stored in the memory, an initial BER estimate as a function of the YI metric; and (c) modifies the initial BER estimate with the retrieved compensation value to provide a BER estimate.

Abstract: When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.

Abstract: A system and method are provided for non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing thresholds to distinguish a first bit estimate; comparing the first bit estimate in the NRZ data stream to a second bit value received prior to the first bit, and a third bit received subsequent to the first bit; in response to the comparisons, determining the value of the first bit; tracking the NRZ data stream inputs in response to sequential bit value combinations; maintaining long-term averages of the tracked NRZ data stream inputs; adjusting the thresholds in response to the long-term averages; and, offsetting the threshold adjustments to account for the asymmetric noise distribution. Two methods are used to offset the threshold adjustments to account for the asymmetric noise distribution: forward error correction (FEC) decoding and tracking the ratio of bit values.

Abstract: An electronic radio frequency (RF) identification system 10 is disclosed and claimed. The system includes an interrogator 11 and a plurality of RF transponders 12.1 to 12.n. In use, each transponder is operative in response to an interrogation signal 14 to respond with a forward error correctable data message 16.1 including base data encoded as symbol characters in accordance with a forward error correcting code, such as a Reed Solomon Code, and check characters on the base data as defined in the forward error correcting code. The interrogator 11 utilizes data relating to the forward error correcting code, the symbol characters and check characters in the received forward error correctable data message, to reconstruct the base data in the event of corruption of the forward error correctable data message during transmission.

Abstract: A digital magnetic recording/reproducing apparatus includes an LVA (List Viterbi Algorithm) detector which produces first to nth best sequences (n>1) of a decoded result, and replaces a likelihood ratio and a path memory of the ith best sequence (i=2, 3, . . . , n) with those of the (2i?1)th best sequence when contents of path memories of the (i?1)th and ith best sequences are equal to each other and an absolute value of a difference between likelihood ratios of the (i?1)th and (2i?1)th best sequences is smaller than a decision threshold. Alternatively, the LVA detector initializes a likelihood ratio of the ith best sequence to be a likelihood ratio of the (i?1)th best sequence with a constant difference value added thereto when contents of path memories of the (i?1)th and ith best sequences are equal to each other.

Abstract: A system for providing an error indication of video data received from a first link of a data interface between a computer system video controller and a display system and for providing the error indication to the video controller from the display system via a second link of the data interface. Such a system can be utilized to determine if an error condition exits in the video data path between the video controller and display system. In one example, the data interface conforms to the Digital Visual Interface (DVI) specification. A diagnostic routine of an operating system can be utilized to generate a set of test video data and compare the generated error indication with a standard error indication to determined an error condition. Also, such a system allows a remote system to request a test of the video data path. In one embodiment, the error indication is provided to the video controller from the display system by inserting the error indication into a display information data structure such as, e.g.

Abstract: A method and system for detecting a failure in a dynamic random access memory (DRAM) array having a plurality of cells organized in a matrix fashion of rows and columns. The method includes reading the content of a first row of cells of the memory array during a first refresh cycle. After obtaining the content from the first row of cells, a first complement of the content is generated. The generated first complement is then written back to the first row of cells during the writeback operation of the first refresh cycle. During the subsequent refresh cycle, the first complement in the first row of cells is read and a second complement of the first complement is generated. Next, the original content in the first row of cells is compared with the second complement. In response to the original content not being equal to the second complement, a control signal is generated to indicate a failure in the memory array.

Abstract: Improved error screening techniques are used in processing digital audio or other types of information received in a digital communication system. Control information associated with a given packet of the received information is identified and compared with a decoding requirement of the packet, in order to control the generation of an error indicator for the packet. More particularly, the error indicator may be generated in response to an inconsistency between the control information and the decoding requirement. For example, the control information may include an indication of packet length that can be compared to a number of bits required to decode the corresponding packet, with any inconsistency between the packet length indication and the number of required bits leading to the generation of an error flag for the packet.

Abstract: Bit probability estimates generated by a turbo decoder are employed to weight the bits of a received packet before combining the received packet with a redundant packet. Bits are individually weighted by the corresponding bit probability estimate and all bits within the received packet are weighted by a block confidence estimate generated from the cumulative bit probability estimates for the received packet. Weighted packet bits are combined within either weighted packet bits for the redundant packet or unweighted received bits for the redundant packet. The bits are combined by adding counterpart weighted (or weighted and unweighted) systematic and parity bit values within the two packets while inserting disjoint parity bit values within the combined result. Decoding performance for incremental redundancy systems utilizing turbo decoding is improved.

Abstract: An apparatus for restoring the cell data storage regions of the common memory in an asynchronous transfer mode (ATM) switch system, comprises a first multiplexer for multiplexing the cell data with the header and content data separated, a second multiplexer for multiplexing the addresses generated from a plurality of FIFO registers, an address checker for checking the addresses from the second multiplexer to generate a first and second address signals if the addresses are checked normal, an address memory storing all addresses of the common memory in error state to selectively convert the addresses into normal state according to the second address signal from the address checker, a controller for checking the address memory at predetermined intervals to restore an address stored in error state to a normal state, and an address multiplexer for generating an idle address to an IAP according to the first address signal and address restored signal.

Abstract: A CDMA communication system provides a dedicated control channel capable of efficiently communicating control messages between a base station and a mobile station. In a dedicated control channel transmission device, a controller determines a frame length of a message to be transmitted and outputs a frame select signal corresponding to the determined frame length. A message generator generates frame data of the message to be transmitted according to the frame select signal. A transmitter spreads the frame data and transmitting the spread frame data through a dedicated control channel. In a dedicated control channel reception device, a despreader despreads a received signal. A first message receiver deinterleaves and decodes the despread signal in a first frame length to output a first message, and detects a first CRC corresponding to the decoded signal.

Abstract: A memory traffic access controller (18) responsive to a plurality of requests to access a memory. The controller includes circuitry (18d) for associating, for each of the plurality of requests, an initial priority value corresponding to the request. The controller further includes circuitry (18b, 18d, 18e, 18f) for changing the initial priority value for selected ones of the plurality of requests to a different priority value. Lastly, the controller includes circuitry for outputting (18d) a signal to cause access of the memory in response to a request in the plurality of requests having a highest priority value.

Abstract: A memory controller, upon detecting an interval of inactivity (that is, no read or write access from a processor or I/O devices with respect to main storage or memory SDRAMs) halts external refresh commands from the processor, and initiates STR mode in main storage to preserve data contents in the memory SDRAMs and to save energy. Then, upon detecting a read or write operation, the memory controller signals main storage to exit STR mode.

Abstract: An image processing apparatus comprises a receiving device for receiving encoded image data which is encoded by using orthogonal transform in a predetermined block unit, an error detecting device for detecting a transmission error of the encoded image data, a correcting device for correcting the transmission error in the predetermined block unit, and a decoding device for decoding the encoded image data and outputting image data for reproducing an image. The image processing apparatus satisfactorily controls the amount of compressed data and prevents a deterioration of image quality even if any error occurs on a transmission path, thereby reproducing good image quality.

Abstract: A storage controller, upon detecting an interval of storage inactivity, inhibits external storage refresh commands and places the storage in self timed refresh (STR) mode. Upon detecting storage activity while storage is in STR mode, the controller terminates STR mode in storage. Upon detecting a scrub request while storage is in STR mode, the controller terminates STR mode in the storage and thereafter services the scrub request. Upon completing execution of the scrub request, the controller returns storage to STR mode.

Abstract: The present invention provides a memory system that optimizes, during a sleep mode, a refresh period for a memory device, such as DRAM, which stores meaningful data and for which a refresh operation is required to prevent the loss of data.

Abstract: An error-correcting dynamic memory (100) which performs error correction (110) only during refresh or during the second (or subsequent) read of a burst read or during a writeback. Further, the memory may contain an error-correction-code-obsolete bit in addition to data bits and check bits in order to generate check bits during refresh and not during write. This provides error correction without read access delay or write delay at the cost of slightly more exposure to soft errors.

Abstract: Information is processed to produce a plurality of information symbols. The plurality of information symbols are encoded according to a concatenation of an error correction code and a nonorthogonal modulation code to produce a modulated communications signal. The modulated communications signal is communicated over a communications medium, and process the communicated modulated communications signal is processed to produce information. Preferably, the information symbols are encoded according to an error correction code, preferably a convolutional code, to produce a plurality of coded symbols. The plurality of coded symbols are preferably interleaved to produce a plurality of interleaved coded symbols. The interleaved coded symbols are then modulated according to a nonorthogonal code to produce the modulated communications signal.