Abstract: A memory controller for use in a data storage device is provided. A low-density parity check (LDPC) process performed by the memory controller includes an initial phase, a decoding phase, and an output phase. The memory controller includes a variable-node circuit and a check-node circuit. During the initial phase, the variable-node circuit performs the following steps: obtaining a channel value, that is read from a flash memory, from a channel-value memory; transmitting the channel value to the check-node circuit to calculate a syndrome; and in response to the syndrome not being 0, setting a value of a register corresponding to each entry of a plurality of entries in a variable-node memory, and entering the decoding phase.

Abstract: According to one embodiment, a memory system includes non-volatile memory and volatile memory. A controller encodes a first unit size data portion to be written into the non-volatile memory and generates a first error correction code for the data portion, then writes the data portion into the non-volatile memory. The controller also stores the first error correction code in the volatile memory. When non-volatilization of an error correction code protect the data portion is requested, the controller encodes the data portion to generate a second error correction code for the data portion, and then writes the second error correction code into the non-volatile memory. The second error correction code is smaller in size than the first error correction code.

Abstract: A data storage device configured to access a magnetic tape is disclosed, wherein the data storage device comprises at least one head configured to access the magnetic tape. A first plurality of data blocks are encoded into a first plurality of ECC sub-blocks including a first ECC sub-block, and the first plurality of ECC sub-blocks are encoded into a first ECC super-block. The first ECC sub-block is written to the magnetic tape, and a write-verify of the first ECC sub-block is executed by reading the first ECC sub-block. When the write-verify passes, a second plurality of data blocks are encoded into a second ECC super-block, and when the write-verify fails, a third plurality of data blocks and the first ECC sub-block are encoded into the second ECC super-block, wherein the second ECC super-block is written to the magnetic tape.

Abstract: An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.

Abstract: A signal forwarding device receives a dual-encoded first set of data that is encoded according to first and second sets of encoding parameters. The signal forwarding device decodes the dual-encoded first set of data, using decoding parameters that correspond to the second set of encoding parameters, to generate a single-encoded first set of data that is encoded according to the first set of encoding parameters. The signal forwarding device transmits the single-encoded first set of data to the destination device, which decodes the single-encoded first set of data using decoding parameters that correspond to the first set of encoding parameters. If the decoding is unsuccessful, the destination device requests retransmission. The signal forwarding device decodes a stored copy of the single encoded first set of data, using decoding parameters that correspond to the first set of encoding parameters, and retransmits the first set of data to the destination device.

Abstract: Systems, methods, and computer-readable media are disclosed for performing reduced latency error decoding using a reduced latency symbol error correction decoder that utilizes enumerated parallel multiplication in lieu of division and replaces general multiplication with constant multiplication. The use of parallel multiplication in lieu of division can provide reduced latency and replacement of general multiplication with constant multiplication allows for logic reduction. In addition, the reduced symbol error correction decoder can utilize decode term sharing which can yield a further reduction in decoder logic and a further latency improvement.

Abstract: A discrete multitone transceiver (DMT) includes a deinterleaver operable to de-interleave a plurality of bits. The DMT further includes: a forward error correction decoder operable to decode the plurality of bits, a module operable to determine, during Showtime, an impulse noise protection value, wherein the impulse protection value specifies a number corrupted DMT symbols that can be corrected by the forward error correction decoder in combination with the deinterleaver, and a receiver coupled to the deinterleaver. The receiver receives using a first interleaver parameter value, receives a flag signal, and changes to receiving using a second interleaver parameter value that is different than the first interleaver parameter value, wherein the second interleaver parameter value is used for reception on a pre-defined forward error correction codeword boundary following reception of the flag signal.

Abstract: Disclosed are: a transmission method for receiving an input bit for data to be transmitted to a reception end, determining a position of a parity bit according to a value indicated by additional information to be transmitted together with the data, and transmitting a bitstream by encoding the input bit and the parity bit according to the position of the parity bit; and a processing method for decoding the bitstream by taking into consideration of a position at which the parity bit is added to the input bit in the bitstream received from a transmission end, and acquiring the additional information transmitted together with the data indicated by the input bit according to the decoded result.

Abstract: A method and system for implementing error correcting code using a product code decoder. The method and system receive a product code, wherein the product code is a matrix of row and column component codes, generate a plurality of row syndromes column syndromes from the received product code, store the plurality of row syndromes in a row syndrome queue, store the plurality of column syndromes in a column syndrome queue, the column and row syndrome queue to support the plurality of modes of operation corresponding to the plurality of phases of decoding the product code, correct the plurality of row syndromes and columns syndromes in the row and column syndrome queues based on errors detected in respective row and column syndromes and errors detecting in overlapping syndromes, and correct the product code in a codeword buffer at locations corresponding to corrections in the plurality of row syndromes and the plurality of column syndromes.

Abstract: A method includes distributively encoding data stored in a storage system using an erasure-correcting code. The encoded data is distributed into multiple w storage device arrays in the storage system. Each storage device array includes n storage devices. Each storage device is divided into m sectors or pages. The n storage devices are grouped into l groups of t storage devices each. Data erasures in the w storage device arrays are corrected by recovering erased data using the erasure-correcting code of un-erased data based on each row and column in each m×n array being protected by the erasure-correcting code for the data. Each group of t storage devices contains extra second responder parities to correct extra data erasures in addition to data erasures corrected by first responder vertical parities in each m×t subarray, and w, n, m, l and t are positive integers.

Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM). A reliability metric for each symbol of each of a plurality of codewords read from the NVSM is generated, and a number of erasures for a first codeword are generated, wherein the number of erasures exceeds the correction power of the first codeword. A reliability metric of the first codeword is modified corresponding to one of the erasures. The reliability metrics for each codeword including the modified reliability metrics of the first codeword are first iteratively processed using a low density parity check (LDPC) type decoder, thereby first updating the reliability metric for each symbol of each codeword. The reliability metrics for the first codeword are second updated using the parity sector, and the second updated reliability metrics for the first codeword are second iteratively processed using the LDPC-type decoder.

Abstract: One example of integrated interleaved Reed-Solomon decoding can include computing a number of syndromes for each of a number of interleaves and correcting a number of erasures in each of the number of interleaves.

Abstract: A method and data storage system receives a confidence vector for a non-binary symbol value read from a memory cell of a non-volatile memory device, where the confidence vector includes a first plurality of confidence values and transforms the first plurality of confidence values into a first plurality of likelihood values using a forward tensor-product transform. A respective binary message passing decoding operation is performed with each of the first plurality of likelihood values to generate a second plurality of likelihood values, and the second plurality of likelihood values are transformed into a second plurality of confidence values of the confidence vector using a reverse tensor-product transform.

Abstract: A system, computer program product, and computer-executable method for use with a distributed storage system comprising a plurality of storage nodes each having attached storage devices, the system, computer program product, and computer-executable method including receiving a request, at a first storage node of the plurality of storage nodes, to store a large portion of data, using at least one of a first type of data chunk and a plurality of a second type of data chunks to store the large portion of data, processing each of the plurality of the second type of data chunks, processing each of the at least one of the first type of data chunk, and returning an acknowledgement to the request.

Abstract: An example methods for interleaved BCH codes can include encoding a plurality of portions of data using a first generator polynomial to obtain a plurality of respective BCH codewords. The method can include encoding an additional BCH codeword based at least in part on a second plurality of portions of data and the plurality of BCH codewords using a second generator polynomial. The method can include outputting the plurality of respective BCH codewords and the additional BCH codeword.

Abstract: An encoder and a method for encoding a first stream of bits, the method may include splitting the first stream of bits to multiple second streams; encoding, in parallel and by using multiple linear feedback shift registers (LFSRs), the multiple second streams to provide third streams, wherein each second stream of the multiple second streams is encoded using an LFSR of the multiple LFSRs; wherein the encoding comprises feeding the multiple second streams to the multiple LFSRs; merging the third streams to provide a fourth stream; wherein the fourth stream is stored in the multiple LFSRs; and encoding the fourth stream to provide a fifth stream; wherein the encoding of the fourth stream comprises concatenating the multiple LFSRs while bypassing feedback circuits of some of the multiple LFSRs; and shifting the fourth stream through the multiple LFSRs.

Abstract: An error checking and correcting (ECC) decoder is provided to perform a BCH decoding to decode codeword into decoded data. The ECC decoder includes a syndrome generator circuit, an error locator polynomial circuit, and a decoding circuit. The syndrome generator circuit generates a plurality of syndromes corresponding to the codeword. The error locator polynomial circuit performs an arithmetic operation by using the syndromes to generate a plurality of coefficients in an error locator polynomial. The arithmetic operation includes a plurality of operators, wherein at least one of the operators is a lookup table circuit. The decoding circuit obtains at least one solution to the error locator polynomial with the coefficients and corrects the codeword according to the solution to the error locator polynomial to generate the decoded data.

Abstract: A method begins by a dispersed storage (DS) processing module encoding data using a dispersed storage error coding function to produce a set of encoded data slices. The method continues with the DS processing module encoding a first encoded data slice of the set of encoded data slices using a zero information gain (ZIG) function based on a second encoded data slice of the set of encoded data slices to produce a ZIG encoded data slice. The method continues with the DS processing module outputting the ZIG encoded data slice and a subset of encoded data slices of the set of encoded data slices, wherein the subset of encoded data slices includes less than a decode threshold number of encoded data slices and does not include the first or the second encoded data slice.

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The decoding method includes: executing at least one first iteration decoding procedure of an LDPC on a first codeword according to a first clock signal by a correcting circuit; generating a control parameter according to a first iteration count of the first iteration decoding procedure; outputting a second clock signal to the correcting circuit according to the control parameter; and executing at least one second iteration decoding procedure of the LDPC on a second codeword according to the second clock signal by the correcting circuit.

Abstract: The present embodiments relate to Reed-Solomon encoding, and to circuitry for performing such encoding, particularly in an integrated circuit. A Reed-Solomon encoder circuit may receive a message with data symbols and compute a partial syndrome vector by multiplying the data symbols with a first matrix. The Reed-Solomon encoder circuit may further compute parity check symbols by solving a system of linear equations that includes the partial syndrome vector and a second matrix. As an example, the second matrix may be decomposed into a lower triangular matrix and an upper triangular matrix, and the parity check symbols may be computed by performing a forward substitution and a backward substitution using the lower and upper triangular matrices. The Reed-Solomon encoder circuit may generate a Reed-Solomon code word by combining the data symbols and the parity check symbols, and provide the Reed-Solomon code word at an output port.

Abstract: A syndrome calculation circuit receives input data r(x) including data and a parity bit and having a code length n of (2m?1) bits at maximum which is represented by a Galois field GF(2m), and performs syndrome calculation so as to meet s??i+?j z?(?i+?)?1+??1+(?j+?)?1+?1??(A) thereby calculating syndromes s and z. An error position polynomial coefficient calculation circuit calculates the coefficient of an error position polynomial to obtain s×z by multiplying s and z by one multiplier. After that, 2-bit error data positions i and j are specified. Errors at the error data positions i and j of the input data are corrected.

Abstract: A method for hierarchical correction coding includes converting data for a storage system into w storage device arrays, each storage device array including n storage devices, and each storage device divided into m sectors or pages. The n storage devices are grouped into l groups of t storage devices each. Erasures in the w storage device arrays are corrected based on protecting each row and column in each m×n array by an erasure-correcting code. Each group of t storage devices contains extra parities to correct extra erasures in addition to erasures corrected by vertical parities in each m×t subarray, and w, n, m, l and t are positive integers.

Abstract: Devices and methods for video decoding with application layer forward error correction in a wireless device are generally described herein. In some methods a partial source symbol block is received that includes at least one encoded source symbol representing an original video frame. In such methods, the at least one encoded source symbol is systematic, the source symbol is decoded to recover a video frame, and the video frame is provided to a video decoder that generates a portion of an original video signal from the recovered video frame.

Abstract: This invention discloses a memory control module and its associated control method. The memory control module includes a storage unit, an ECC unit, and a read/write control unit. The storage unit is to store a target data. The ECC unit includes multiple first encoders and a second encoder. The first encoders perform an encoding operation on the target data and generate multiple first sets of parity check bits, which comprise at least two lengths. The second encoder performs an encoding operation on the target data and the multiple first sets of parity check bits and generates a second set of parity check bits. The read/write control module converts the target data, the first sets of party check bit sets and the second set of parity check bits into a data format of a memory module.

Abstract: Technology is disclosed for a data storage architecture for providing enhanced storage resiliency for a data object. The data storage architecture can be implemented in a single-tier configuration and/or a multi-tier configuration. In the single-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data fragments, which are stored across many storage devices. In the multi-tier configuration, a data object is encoded, e.g., based on an erasure coding method, to generate many data segments, which are sent to one or more tiers of storage nodes and at least one latent storage. Each of the storage nodes further encodes the data segment to generate many data fragments representing the data segment, which are stored across many storage devices associated with the storage node. The I/O operations for rebuilding the data in case of device failures is spread across many storage devices, which minimizes the wear of a given storage device.

Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.

Abstract: A frame error correction circuit may identify and correct errors in data frames provided to a receiver as part of a diversity communications scheme. The frame error correction circuit may further align the data frames so that the data frames can be compared. The frame error correction circuit may perform a bit-wise comparison of the data frames and identify inconsistent bit positions where bits in the data frames differ from one another. Once inconsistent bit positions have been identified, the frame error correction circuit may access a permutation table of permutations of bits at the inconsistent bit positions. In some implementations, the frame error correction circuit uses the permutation table to reassemble permutations of the data frames. In various implementations, the frame error correction circuit performs a CRC of each permutation of the data frames, and provides a valid permutation to a network.

Abstract: A data storage system stores sets of data blocks in extents located on storage devices. During operation, the system performs an erasure-coding operation by obtaining a set of source extents, wherein each source extent is stored on a different machine in the data storage system. The system also selects a set of destination machines for storing destination extents, wherein each destination extent is stored on a different destination machine. Next, the system performs the erasure-coding operation by retrieving data from the set of source extents, performing the erasure-coding operation on the retrieved data to produce erasure-coded data, and then writing the erasure-coded data to the set of destination extents on the set of destination machines. Finally, after the erasure-coding operation is complete, the system commits results of the erasure-coding operation to enable the set of destination extents to be accessed in place of the set of source extents.

Abstract: The present discloses provides a decoding method, decoding apparatus and decoder for correcting burst errors. In particular, the decoding method for correcting burst errors comprises: computing an initial syndrome of a received data frame, wherein the data frame is encoded according to cyclic codes for correcting burst errors; determining error correctability of burst error contained in the data frame based on the computed initial syndrome; and processing the burst error in the data frame and outputting the processed data frame based on the determined error correctability. With the decoding method, decoding apparatus, and decoder of the present invention, error correctability of burst errors contained in a data frame can be determined before the data is send out, while having smaller decoding latency through determining the error correctability and error pattern of the burst errors contained in the data frame using initial syndrome of the data frame.

Abstract: In one embodiment, a data storage system includes a write channel for writing data to a storage medium, the write channel configured to utilize a partial reverse concatenated modulation code. The write channel includes logic adapted for encoding data sets using a C2 encoding scheme, logic adapted for adding a header to each subunit of the data sets, logic adapted for encoding the headers of the data sets with a first modulation encoding scheme, logic adapted for encoding data portions of the data sets with a second modulation encoding scheme, logic adapted for encoding portions of the one or more C2-encoded data sets using a C1 encoding scheme, logic adapted for combining the C1-encoded portions with the modulation-encoded headers of the C2-encoded data sets using a multiplexer, and logic adapted for writing the one or more combined C1 - and C2-encoded data sets to data tracks.

Abstract: A computing system includes: a communication unit configured to: determine a relaxed coding profile including a polar-processing range for processing content data over a bit channel; process the content data based on a total polarization level being within the polar-processing range, the polar-processing range for controlling a polar processing mechanism or a portion therein corresponding to the bit channel for the content data; and an inter-device interface, coupled to the communication unit, configured to communicate the content data.

Abstract: A method includes generating a first subset of codeword symbols by processing, during each of a plurality of iterations, a first input and a second input. The first input is a function of (i) an output, during a respective one of the plurality of iterations, of a last processing stage of a first plurality of processing stages and (ii) a symbol, of a first subset of original symbols, corresponding to the respective iteration. The second input is a function of (i) an output, during the respective iteration, of a last processing stage of the second plurality of processing stages and (ii) a symbol, of a second subset of original symbols, corresponding to the respective iteration. The method also includes generating a second subset of codeword symbols by processing, during each of the plurality of iterations, the first input and the second input.

Abstract: Methods and systems for efficient Reed-Solomon (RS) decoding are provided. The RS decoding unit includes both an RS pseudo decoder and an RS decoder. The RS pseudo decoder is configured to correct a small number of errors in a received codeword, while the RS decoder is configured to correct errors that are recoverable by the RS code. The RS pseudo decoder runs in parallel with the RS decoder. Once the RS pseudo decoder successfully decodes the codeword, the RS decoder may stop its processing, thereby reducing the RS decoding latency.

Abstract: A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols.

Abstract: The error correction processing includes: data reproduction processing of reproducing recording data, constituted by a plurality of data units each made of a plurality of bits, from a recording medium sequentially; error correction processing of performing error correction in the row direction and error correction in the column direction at least once for an error correction code block that has the reproduced recording data arranged in the row direction over a plurality of rows; determination processing of determining whether uncorrectable data is left behind after execution of the error correction processing; and erasure correction processing of performing, when it is determined that uncorrectable data is left behind, column-direction error correction considering data constituting at least one row of the error correction code block as erasure data, even in cases where uncorrectable data in the error correction in the row direction is not left behind.

Abstract: A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols.

Abstract: The present invention relates to a device and a method for transmission, a device and a method for reception, and a program that make it possible to obtain an undetected error probability characteristic close to a limit value in a system using a CRC for a plurality of pieces of data having different code lengths. A generator polynomial for header data which generator polynomial is used when a CRC coding process is performed on header data and a generator polynomial for sub-header data which generator polynomial is used when the CRC coding process is performed on sub-header data are set in a transmitting device. The transmitting device selects a generator polynomial according to data set as an object of the CRC coding process.

Abstract: In one embodiment, a system for combination error and erasure decoding for product codes includes a processor and logic integrated with and/or executable by the processor, the logic being configured to receive captured data, generate erasure flags for the captured data and provide the erasure flags to a C2 decoder, set a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data, and selectively perform, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. In more embodiments, a method and/or a computer program product may be used for combination error and erasure decoding for product codes.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for encoding and decoding information.

Abstract: A fault tolerance method for combinational circuits is provided. In order to increase reliability of combinational circuits, extra redundant modules are added to the circuit logic. The method further utilizes redundancy techniques to improve soft error reliability, and is based on probability of occurrence for combinations at the outputs of circuits, thus enhancing the reliability of the combinational circuits.

Abstract: A turbo decoder configured to perform MAP (Maximum A Posteriori) decoding for a plurality of data blocks including encoded noise, comprises a first MAP decoder configured to perform MAP decoding for a first data block that is included in the plurality of data blocks; an interleaver configured to interleave a result of performing MAP decoding for the first data block; a second MAP decoder configured to perform MAP decoding based on a data included in the first data block and an interleaved data of the first data block; a deinterleaver configured to deinterleave a result of performing MAP decoding from the second MAP decoder for the first data block; and at least one storage unit configured to be formed between the first MAP decoder, the interleaver, the second MAP decoder and the deinterleaver.

Abstract: A method and system for constructing a generator matrix is disclosed. The method includes: receiving a parity check matrix H, wherein the parity check matrix H includes multiple circulant sub-matrices; rearranging the parity check matrix H by column and row permutations to obtain a rearranged parity check matrix H?; and constructing the generator matrix G based on the rearranged parity check matrix H?.

Abstract: Systems, methods and apparatus are described to interleave LDPC coded data for reception over a mobile communications channel, such as, for example, a satellite channel. In exemplary embodiments of the present invention, a method for channel interleaving includes segmenting a large LDPC code block into smaller codewords, randomly shuffling the code segments of each codeword and then convolutionally interleaving the randomly shuffled code words. In exemplary embodiments of the present invention, such random shuffling can guarantee that no two consecutive input code segments will be closer than a defined minimum number of code segments at the output of the shuffler. In exemplary embodiments of the present invention, by keeping data in, for example, manageable sub-sections, accurate SNR estimations, which are needed for the best possible LDPC decoding performance, can be facilitated based on, for example, iterative bit decisions.

Abstract: Impulse and/or burst noise signal to noise ratio (SNR) aware concatenated forward error correction (FEC). Adaptive processing is performed on a signal based on one or more effects which may deleteriously modify a signal. For example, based on a modification of a signal to noise ratio (SNR) associated with one or more impulse or burst noise events, which may be estimated, different respective processing may be performed selectively to differently affected bits associated with the signal. For example, two respective SNRs may be employed: a first SNR for one or more first bits, and a second SNR for one or more second bits. For example, as an impulse or burst noise event may affect different respective bits of a codeword differently, and adaptive processing may be made such that different respective bits of the codeword may be handled differently.

Abstract: A transmitter inserts parity samples into a stream of information symbols in an inter-symbol correlated (ISC) signal. The inserted parity samples may be utilized to generate estimates of corresponding information symbols when they are received by a receiver. The information symbols may be pulse shaped by a first pulse shaping filter characterized by a first response. The parity samples may be pulsed shaped by a second pulse shaping filter characterized by a second response. The first response and the second response are diverse or uncorrelated. The transmitter may transmit the ISC signal comprising the pulse shaped information symbols and the pulse shaped parity samples. The parity samples may be generated utilizing a non-linear function over a plurality of the information symbols. The non-linear function may be diverse from a partial response signal convolution corresponding to the information symbols and is designed according to a desired SNR value at the receiver.

Abstract: A system and method for modulation diversity uses interleaving. Code bits are placed into groups and are then shuffled within each group.

Abstract: An error-correction coding method that includes outer coding of performing a coding process for an outer code; and inner coding of performing a coding process for an inner code that has an error correction capability adjusted based on an error correction capability of the outer code.

Abstract: Aspects of the disclosure provide a circuit that includes a decoder, an error checking module, and a controller. The decoder is configured to receive codewords, and decode the codewords based on an error correcting code. The error checking module is configured to error-check sectors using an error detecting code in the sectors. Each sector is formed of a plurality of decoded codewords. The controller is configured to store in a memory, when the error checking fails for at least one sector, the decoded codewords and corresponding flags indicative of pass or fail of the decoding of the codewords.

Abstract: Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages.

Abstract: Serially-concatenated codes are formed in accordance with the present invention using a constrained interleaver. The constrained interleaver cause the minimum distance of the serial concatenated code to increase above the minimum distance of the inner code alone by adding a constraint that forces some or all of the distance of the outer code onto the serially-concatenated code. This allows the serially-concatenated code to be jointly optimized in terms of both minimum distance and error coefficient to provide significant performance advantages. These performance advantages allow a noise margin target to be achieved using simpler component codes and a much shorter interleaver than was needed when using prior art codes such as Turbo codes. Decoders are also provided. Both encoding and decoding complexity can be lowered, and interleavers can be made much shorter, thereby shortening the block lengths needed in receiver elements such as equalizers and other decision-directed loops.