Abstract: A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates.

Abstract: A serial communication device bridging between a parallel bus and a serial bus, includes (a) a check bit producer which applies an error correcting code to parallel data transmitted through the parallel bus, (b) a parallel-serial converter which converts the parallel data output from the check bit producer, into serial data, (c) a serial-parallel converter which converts serial data transmitted through the serial bus, into parallel data, and (d) an error detector which checks an error correcting code applied to the serial data, and detects an error in the error correcting code.

Abstract: An Error Correcting Code (ECC) conversion facility includes a first interface for receiving input data protected in accordance with a first ECC, and first and second processing paths, each connected to the first interface. First and second decoders are incorporated into respective first and second processing paths. Each of these decoders serves to extract clear data from input data protected in accordance with the first ECC. The first processing path also includes a decoder that can protect clear data in accordance with a second ECC. The output of the system is then connected to both the first and second processing paths, and produces output data protected in accordance with the second ECC. A first portion of this output data comprises data received from the first processing path, and a second portion of the output data comprises data received from the second processing path.

Abstract: An input data signal string I is temporarily stored in an input register, and is input to a parallel adder operating according to the instruction of a control unit. The control unit designates an address of a ROM storing a check matrix H, and obtains information about locations of “1s” in a specific column of the check matrix corresponding to a current input data bit. The ROM instructs selectors SEL1#1–SEL1#CW to select from a register reg(M) bits corresponding to rows in which the check matrix value is 1 for the specified matrix column and sends the selected values to the adder. Results of the additions and the values output from the reg(M) are selected between for input to the reg(M) through the selectors SEL2#1–SEL2#M. This process is repeated until all the input bits have been processed.

Abstract: A block coding algorithm uses an original block group having n+1 original blocks of m-bit message, which a first original block of m-bit message is encoded as a reference block of n-bit codeword and n original blocks of m-bit message placed after the first original block of m-bit message are encoded as n weighted blocks of n-bit codeword, based on a bit sequence of the reference block. A block decoding algorithm decodes n weighted blocks to generate corresponding original blocks of m-bit message and reconstructs the first original block of m-bit message from a sequence of reference bits, wherein each reference bit implies whether each of n weighted blocks is an A type weighted block or a B type weighted block.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: Disclosed is a method for providing first and second interleaved bit streams to a modulator in order to transmit the first and second interleaved bit streams through at least two antennas in a mobile communication system. An encoder encodes a transmission data stream into a first bit stream with first priority and a second bit stream with second priority being lower than the first priority. An interleaver interleaves the first and second bit streams into the first and second interleaved bit streams. The modulator modulates the first and second interleaved bit streams.

Abstract: Correction and location information are determined from a number of data vectors. The location information comprises values determined from subsets of the data vectors. Two or more of the subsets have one or more data vectors in common, but also have one or more data vectors, in one or more of the subsets, that are not in other subsets. The subsets comprise groups of data vectors, and the groups of data vectors have a size that is a function of a power of two. Transmission codes are used on the data vectors and correction and location information. Received location information and determined location information are compared to determine a data vector having an error. Received correction information and determined correction information are compared to correct the data vector having the error. Failing optical lanes may be replaced efficiently by using a number of multiplexers coupled to electrical lanes and optical lanes.

Abstract: Generating a check matrix includes defining a set of column vectors. A matrix operable to have a plurality of entries is initiated. Each entry has a submatrix that includes a function of a subset of the set of column vectors. The following is repeated until a last entry of the matrix is reached. Subsets of the set of column vectors are generated from the set of column vectors, and an entry is generated from each subset. A weight associated with each entry is calculated, and an entry having a minimum weight is selected. The selected entry is added to the matrix, and the subset of column vectors associated with the selected entry is removed from the set of column vectors. The matrix is reported.

Abstract: Methods and apparatus for encoding codewords which are particularly well suited for use with low density parity check (LDPC) codes and long codewords are described. The described methods allow encoding graph structures which are largely comprised of multiple identical copies of a much smaller graph. Copies of the smaller graph are subject to a controlled permutation operation to create the larger graph structure. The same controlled permutations are directly implemented to support bit passing between the replicated copies of the small graph. Bits corresponding to individual copies of the graph are stored in a memory and accessed in sets, one from each copy of the graph, using a SIMD read or write instruction. The graph permutation operation may be implemented by simply reordering bits, e.g., using a cyclic permutation operation, in each set of bits read out of a bit memory so that the bits are passed to processing circuits corresponding to different copies of the small graph.

Abstract: Methods and apparatus of the present invention can be used to implement a communications system wherein different devices using the same LDPC code can be implemented using different levels of parallelism. The use of a novel class of LDPC codes makes such differences in parallelism possible. Use of a factorable permuter in various embodiments of the invention make LDPC devices with different levels of parallelism in the encoder and decoder relatively easy to implement when using the codes in the class of LDPC codes discussed herein. The factorable permuter may be implemented as a controllable multi-stage switching devices which performs none, one, or multiple sequential reordering operations on a Z element vector passed between memory and a Z element vector processor, with the switching one individual vectors being controlled in accordance with the graph structure of the code being implemented.

Abstract: The present invention provides a cyclic redundancy check (CRC) calculation system for a packet arriving on an n-byte wide bus. In one embodiment, the system includes a bus-wide CRC subsystem configured to calculate an intermediate CRC value based on complete segments of the packet. In addition, the system includes a byte-wide CRC subsystem, coupled to the bus-wide subsystem, configured to calculate a remaining CRC value based on the intermediate CRC value and one or more bytes within an incomplete segment of the packet on a byte by byte basis. In addition, a method of calculating a CRC value for a packet arriving on a n-byte wide bus and a data transmission system incorporating the system are also disclosed.

Abstract: A CRC encoding circuit for generating CRC bits in accordance with initial parallel data having remainder portion data in a last column of the initial parallel data. A first parallel encoding unit is included for generating first CRC bits in accordance with the initial parallel data other than the remainder portion data. A CRC bits selector selects second CRC bits having predetermined number of bytes, from the first CRC bits generated by the first parallel encoding unit. A parallel data selector selects second parallel data having the same number of bytes as the second CRC bits, from the remainder portion data.

Abstract: An apparatus and a method for accelerating Cyclic Redundancy Check (CRC) calculations. The apparatus includes a CRC circuit and an accelerator for accelerating the computation of the CRC code so that the CRC code is outputted immediately after the last bit of the input data stream is inserted to the CRC machine, thereby reducing the time required to compute the CRC calculation. The apparatus accelerates the CRC calculation by eliminating the need to append zeros to the input data stream.

Abstract: A method, apparatus and product for use in generating a remainder based code generates a plurality of preliminary remainder based codes in response to specified data, and synthesizing a remainder based code for the specified data, in response to the plurality of preliminary remainder based codes. In one embodiment, the plurality of preliminary remainder based codes includes at least two preliminary remainder based codes each generated in response to a respective portion of the specified data. In another embodiment, at least two preliminary remainder based codes are generated at least partially concurrently with one another.

Abstract: A CRC encoding circuit for generating a CRC code in accordance with a parallel data having a remainder portion data in a last data set of the parallel data, comprises: a first encoding unit for generating one or more first CRC codes in parallel in accordance with the remainder portion data; a CRC code selecting unit for selecting a second CRC code having predetermined number of bytes, from the first CRC codes generated by the first encoding unit; a converting unit for converting the remainder portion data into a serial data; and a second encoding unit for generating a third CRC code in accordance with the second CRC code selected by the CRC code selecting unit and the serial data converted by the converting unit.

Abstract: A K-bit information signal represented by a polynomial U(x) having a degree K?1 is received. The information signal is transformed to form a transformed information signal using a first transform represented by a polynomial G1(x) having a degree P. The transformed information signal is represented by a polynomial T(x) having a degree K+P?1. T(x) equals U(x)G1(x). An initial cyclic code represented by a polynomial R1(x) is generated for the transformed information signal using a second transform represented by a polynomial G2(x), where G2(x) has high-order leading-zero terms. R1(x) equals the remainder obtained by dividing T(x) by G2(x). The initial cyclic code is transformed to form a final cyclic code represented by a polynomial R2(x) using the first transform. R2(x) equals R1(x)/G1(x).

Abstract: An apparatus and method for generating a (n, 3) code and a (n, 4) code using simplex codes are disclosed. To encode a 3-bit information bit stream to a (n, 3) codeword with n code symbols, a simplex encoder generates a first-order Reed-Muller codeword with (P+1) code symbols from the input information bit stream for n>P, and punctures the first code symbol of the (P+1) first-order Reed-Muller code symbols to produce a (P, 3) simplex codeword. An interleaver permutates the P code symbols of the (P, 3) simplex codeword by columns according to a predetermined pattern. A repeater repeats the column-permutated (P, 3) simplex codeword until the number of repeated codes is n and outputs a (n, 3) codeword with the n repeated code symbols.

Abstract: A CRC generation unit includes a number of CRC calculation assemblies to be selectively employed to incrementally calculate a CRC value for a first sequence of N data bytes. The calculation is iteratively performed, one iteration at a time. Further, the selection of the CRC calculation assemblies is made in accordance with the group size of each of a number of data word groups of the N data bytes. In one embodiment, the CRC calculation assemblies include a first assembly for incrementally calculate the CRC value for an iteration, whenever the group size is n/2 bytes or less for the iteration, and a second assembly for incrementally calculate the CRC value for an iteration, whenever the group size is more than n/2 bytes for the iteration. In one embodiment, the CRC generation unit is a shared resource to multiple network traffic flow processing units of a network traffic routing IC.

Abstract: A system updates a cyclic redundancy check (CRC) value. The system receives data containing an arbitrary number of valid and invalid portions. The valid portions are positioned adjacent to one another. The system also receives a signal representing a quantity of valid portions in the data and a current CRC value. The system updates the current CRC value using the data and signal in a single clock cycle.

Abstract: A CRC value cache architecture and methods of operation of same to reduce overhead processing associated with managing a CRC value cache memory. The invention first provides for transferring from system memory to CRC value cache memory all CRC values for all sub-blocks of a data block in response to access to a first CRC value for a first sub-block. This reduces overhead processing to arbitrate for control of the system memory for each CRC value for each sub-block of a block. The invention additionally provides that a separate cache table is maintained corresponding to each device within the storage controller that requests CRC values. Each of the multiple cache entry tables is therefore shorter and more rapidly searched as compared to prior techniques thereby further reducing overhead processing to manage the cached CRC values.

Abstract: A mechanism for forward error correction (FEC) coding, suitable for use where multiple payload streams are simultaneously transmitted from end-to-end. Instead of deriving parity information based on payload information carried within a given stream, the invention involves FEC encoding across multiple parallel streams and thereby deriving parallel parity information. The parallel parity information may then be transmitted to the receiving end in parallel with the underlying payload information. Beneficially, the invention can substantially reduce the time it takes for the transmitting end to derive parity information or for the receiving end to receive the information necessary to recover from data loss. The invention is especially suitable for use in IP telephony and particularly for implementation in an IP telephony gateway.

Abstract: A CRC code calculation circuit for calculating a CRC code from byte parallel data which is variable-length data. In a CRC code calculation circuit 10 for calculating a CRC code from four-byte parallel data having a residual portion in a final stage, a four-byte parallel CRC code calculation circuit 2calculates a CRC code in parallel from the four-byte parallel data except the final stage. A byte serial conversion circuit 3 converts data of the final stage into serial data. A one-byte serial CRC code calculation circuit 4 calculates a CRC code in serial from the serial data converted by the byte serial conversion circuit 3 using a calculated result of the four-byte parallel CRC code calculation circuit 2 as an initial value.

Abstract: Channel error protection is provided for a source coded bit stream in a communication system by a combination of outer channel coding and inner channel coding implemented across different network layers of the system. One or more of a number of different portions of the source coded bit stream are outer channel coded in a first network layer of the system, e.g., an application layer, using a designated outer channel code, so as to provide an outer channel coded bit stream having different levels of error protection for each of the different portions of the source coded bit stream. The outer channel coded bit stream is then inner channel coded in a second network layer of the system, e.g., a physical layer, using a designated inner channel code to thereby generate a channel coded bit stream. The channel coded bit stream may then be subject to further processing operations prior to transmission in the communication system.

Abstract: The invention concerns a method and a device for error correction coding associating with a data source series a coded data block, to be transmitted to at least one receiver comprising at least two coding stages (21i) each comprising at least two basic coding modules (22i,j), each of said coding stages receiving a series of data to be processed, distributed between said basic coding modules, and delivering a series of processed data, derived from said basic coding modules and at least one branching stage (23i), said branching stage being inserted between two successive coding stages, a first coding stage and a second coding stage, and distributing the processed data derived from each basic coding module of said first coding stage between at least two basic coding modules of said second stage. The invention also concerns the corresponding decoding method and device, based on path likelihood.

Abstract: An apparatus and method for generating a cyclic redundancy code with multiple cyclic redundancy code circuits are disclosed. High throughput data protocols can work more robustly if accompanied by high throughput error checking to verify the integrity of the communicated data. One approach of improving the performance of cyclic redundancy code generation hardware that can save money and development time is to combine multiple cyclic redundancy code circuits to perform the error checking. Data received is processed across the multiple cyclic redundancy code circuits. Future cyclic redundancy code circuits can also be combined according to this approach.

Abstract: A CRC generation unit is equipped with multiple polynomial division circuits (PDC) to perform multiple different bit lengths polynomial divisions in parallel, including outputting of multiple remainder values, for an iteration of an iterative CRC generation for a data block. In one embodiment, the unit also includes a selector to select one of the remainder values, and a register to store the selected remainder value, return the stored remainder value to the PDCs for formation of different bit length dividends, and output the stored remainder value of the last iteration as the generated CRC value. In one embodiment, the unit further includes alignment circuitry to align the data block. In one embodiment, multiple units are provided to generate the CRC values of successive variable length data blocks. In one embodiment, the units form a shared resource to multiple network traffic flow processing units of a network traffic routing IC.

Abstract: The present invention relates to a system and method to generate a CRC (Cyclic Redundancy Check) value using a plurality of CRC generators operating in parallel. The system includes a switching module operatively coupled to a parallel data bus. The switching module generates and places a packet cycle on the parallel data bus to transmit a data packet and packet modification commands to modify the data packet. The system further includes a bridging module operatively coupled to the parallel data bus. The bridging module modifies the data packet in accordance to the packet modification commands, and generates a Cyclic Redundancy Check (CRC) value to reflect modifications made to the data packet. The bridging module utilizes a plurality of CRC generators operating in parallel to generate the CRC value quickly and efficiently.

Abstract: System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an appropriate CRC value of a message. This determination can take into account encoded inversion bits in the message. A collection of pre-calculated CRC values are arranged in a single-column table and then implemented with selected bits of a message by superimposing the bits in each CRC value onto a logical grid. Vertical lines of the grid are associated with 30 exclusive OR (XOR) gates and horizontal lines are associated with bits in an 88-bit message (or the 30 bits of a CRC value or with 8 bits of a sequence number). Through this grid, the inputs to the XOR gates are determined, thereby facilitating rapid calculations of CRC values due to the high processing speeds possible in XOR gates.

Abstract: In a coding system wherein an error correction/detect-ion coding is combined with a synchronization recovering technique using a synchronization code, the problems of a pseudo synchronization and a step out due to error detect-ion are solved. There is provided a coding part 212 for coding an input multiplexed code string 201 to an error correcting/detecting code comprising an information bit and a check bit, and code string assembling part 213 for inserting a synchronization code into any one of a plurality of periodically predetermined synchronization code inserting positions in the code string 201, for arranging the information bit at an optional position in the code string, and for arranging the check bit at a position other than the synchronization code inserting positions in the code string 201 to assemble an output code string 205.

Abstract: The present invention involves a method for generating a partial Cyclic Redundancy Checking (CRC) value of a first interval of data in a digital data stream. The method includes the step of loading a precomputed CRC value corresponding to a one bit followed by a predetermined number of zeros. The predetermined number of zeros correspond to the number of digits of a polynomial minus one. The first interval of data is partitioned into a plurality of bits. The precomputed CRC value corresponding to the one bit followed by the predetermined number of zeros is enabled, for each of the plurality of bits having a value of one. The enabled, precomputed CRC values are combined to generate the partial CRC value of the first interval of data. Advantageously, multiple copies of the process may be executed in parallel to achieve a large speed-up.

Abstract: The invention relates to a parallel CRC generation circuit comprising an input register means (I), an output register means (C), a number of XOR gates (XOR1-XORN) and a coupling means (CM) that feeds predetermined ones of the output lines (C0-CN−1) of the output register means (C) and output lines (I1-In) of the input register means (I) as inputs to the respective XOR gates. According to the invention a matrix representation of the state change based on the selected CRC polynomial is set up and evaluated, such that the coupling means (CM) only uses the minimum number of feedbacks of the output lines and feed-forwards of the output lines of the input register means (I). Thus, the parallel CRC calculation circuit according to the invention has no redundancy and uses only a minimum hardware amount.

Abstract: A block coding algorithm uses an original block group having n+1 original blocks of m-bit message, which a first original block of m-bit message is encoded as a reference block of n-bit codeword and n original blocks of m-bit message placed after the first original block of m-bit message are encoded as n weighted blocks of n-bit codeword, based on a bit sequence of the reference block. A block decoding algorithm decodes n weighted blocks to generate corresponding original blocks of m-bit message and reconstructs the first original block of m-bit message from a sequence of reference bits, wherein each reference bit implies whether each of n weighted blocks is an A type weighted block or a B type weighted block.

Abstract: A parallel, recursive system for generating and checking a CRC value is disclosed, in which the feedback and forward terms are separated, and the forward terms are reduced. Forward logic, which implements the forward terms, is responsive to a number of bits received from the unit of data, and performs logic operations reflecting the reduced forward logic terms on bits received from the unit of data, to produce a first output. In some cases the forward logic is a direct connection to a number of exclusive-OR logic gates. Feedback logic, responsive to an output of a remainder register, operates to perform feedback logic operations reflecting the feedback terms, on an output of the remainder register to produce a second output. The second output is also coupled to the exclusive-OR logic gates. The exclusive-OR logic gates perform a bit-wise exclusive-OR logic operation on the first output and the second output to produce an input of the remainder register.

Abstract: A method, and a system for employing the method, for computing a cyclic redundancy code (CRC) of a communication data stream taking a number of bits M at a time to achieve a throughput equaling M times that of a bit-at-a-time CRC computation operating at a same circuit clock speed. The method includes (i) representing a frame of the data stream to be protected as a polynomial input sequence; (ii) determining one or more matrices and vectors relating the polynomial input sequence to a state vector; and (iii) applying a a linear transform matrix for the polynomial input sequence to obtain a transformed version of the state vector. The method can further include (iv) applying a linear transform matrix to the transformed version of the state vector to determine a CRC for the polynomial input sequence, if the communication data stream is received by a network device.

Abstract: A method, and a system for performing the method, for computing cyclic redundancy code (CRC) for use in a communication data stream M bits at a time for an input sequence u(n) whose length is not a multiple of M. The method includes (i) representing a frame of data to be protected as the input sequence; (ii) determining a cyclic redundancy code (CRC) for the input sequence M bits at a time from a state vector, until a last block of the input sequence is reached; (iii) if the last block of the input sequence is full, then determining the CRC to be a completed CRC; and (iv) if the last block of the input sequence is not full, then performing three functions. The method can further include (v) appending the completed CRC as a frame check sequence (FCS) to the communication data stream for detection by a receiving device.

Abstract: A signal processing circuit and an information recording apparatus in which a memory section has two storage areas each of which has a capacity for at least one block of record data and which are alternately switched to a parity-added data storage area where record data added with a parity by a parity adding section is stored and a transmission area into which the parity-added record data is read and transmitted by a transmission section, and the parity adding section starts adding the parity to record data upon reception of record data for one row of error correcting codes.

Abstract: A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits.

Abstract: Disclosed is a configurable Reed-Solomon encoder and method. The configurable Reed-Solomon encoder comprises a multiplexed multiplier-accumulator, a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer. The configurable Reed-Solomon encoder is preferably implemented in an application specific integrated circuit (ASIC), although it may be implemented in software executed by a high-speed digital signal processor, etc.

Abstract: The present invention relates to a method of utilizing information made available in a bit error check of data words belonging to instructions read into a processor having a first (11) and a second (11′) calculating unit which operate in parallel with one another, a so-called double processor mode. The processor structure also comprises a third and a fourth calculating unit (13, 13′) intended for continuously checking for possible bit errors in read-in data words, a comparator (14) for comparing output data from parallel operating units (11, 11′), a diagnostic unit (15) adapted to determine which of the calculating units delivered correct output data when detecting a difference in output data in the comparator (14), and a control unit (16) adapted to control that the output data from the processor structure (1) originates from a calculating unit that has delivered correct output data.

Abstract: A data block includes a plurality of sub-blocks. Each sub-block includes a sub-block check bit that may be used to detect the presence of a bit error within the sub-block. A composite sub-block is generated, which is the column-wise exclusive-or of the bits of each sub-block. In one embodiment, the composite sub-block is not stored, but rather used for computational purposes only. A plurality of composite check bits is used to detect a bit position of a bit error within the composite sub-block. If a bit error within the data block occurs, the sub-block check bits may be used to detect in which sub-block the error occurred. The composite check bits may be used to determine which bit position of the composite sub-block is erroneous. The erroneous bit position of the composite sub-block also identifies the bit position of the erroneous bit in the sub-block identified by the sub-block check bits.

Abstract: In a parallel concatenated convolutional code (PCCC) or turbo code encoder, information bits are supplied to a first convolutional code encoder for producing first parity bits and via an interleaver to a second convolutional code encoder for producing second parity bits, the output of the encoder comprising the information bits and at least some of the first and second parity bits. The interleaver interleaves the information bits in groups each of N bits, where N is an integer greater than one. A parity bit generator can generate additional parity bits which are operated on by the convolutional code encoders and interleaver. A complementary decoder is described. The grouped interleaving can provide reduced memory requirements and faster convergence of the iterative decoding process.

Abstract: A method and apparatus for generation of CRC generation/checker circuitry. A symbolic simulation-based algorithm to derive boolean equations for a parameterizable data-width CRC generator/checker is described. The equations generated are used to implement a data-flow representation of the CRC circuit in VHDL. The VHDL description is then synthesized into gates.

Abstract: A computationally simple yet powerful forward error correction code scheme for transmission of real-time media signals, such as digitized voice, video or audio, in a packet switched network, such as the Internet. For each window of k data packets, the invention generates and transmits at least one cross-wise parity packet taken as an index-shifted function over the k data packets. The invention thereby enables a receiving end to recover from packet loss.

Abstract: An improved CRC generation mechanism for generating a CRC value of relevant data in a digital data stream is disclosed wherein relevant data in the data stream is identified and partitioned into a plurality of intervals. A CRC value is determined for each interval by partitioning the interval into a plurality of chunks, loading from persistent storage a table of CRC values for a range of chunks, determining a CRC value for each of the chunks with parallel table lookup operations on the table, and combining the CRC values for the chunks. The CRC values for each of the intervals is combined to generate the CRC for the relevant data. The parallel table look operation is preferably a vector permute instruction that is executed by a SIMD-style vector unit.

Abstract: To provide a microprocessor that can perform high-speed CRC code generation and can be implemented simply and at a low cost, a microprocessor has, at a part of a data input path to a shift circuit which is conventionally installed in an ALU of the microprocessor to execute shift commands, one bit of data that corresponds to the path, an exclusive OR circuit, which computes the exclusive OR of an uppermost bit of byte data and a bit data, is provided. For this circuit, a result according to a generating polynomial such as [X8+X4+X3+X2+1] is determined on the basis of the installation location of the exclusive OR circuit along the path, and by setting an initial value to the byte data, inputting one bit of the transmission data sequentially to the bit data and operating the shift circuit, a computed result for the CRC code is derived. Consequently, for the microprocessor, the CRC code can be generated at a high speed using the computation commands of the CRC code section.

Abstract: An error injection tool, connected to a bus to be tested in such a manner as not to interfere with normal operation, is employed for error detection and recovery design verification. The error injection tool is connected to the bus to be tested within a data processing system, the system is powered on, and applications simulating normal system loading are run. A desired error is then selected, and the error injection tool is actuated. The error injection tool monitors bus cycles and transactions through selected signals and, upon detecting an appropriate cycle or transaction, overdrives a selected conductor within the bus being tested to inject an error. The selected bus conductor is overdriven (forced) to a logic high or a logic low for a single clock cycle, simulating the intermittent nature of errors likely to occur during normal operation. Bus error signals are then monitored to ascertain whether the error was successfully injected.

Abstract: Apparatus, and an associated method, for performing error-correction operations to correct errors in a block of block-encoded data. Two ALUs are operable in parallel to perform finite-field mathematical operations and to calculate addresses used pursuant to the error-correction calculations. Instructions pursuant to which the ALUs are operable are stored in a memory device. The instructions are retrieved during operation of error-correcting calculations. The manner by which the error-correcting apparatus operates is alterable by appropriate alteration of the instructions stored at the memory device.

Abstract: An encoder encodes digital signals representative of data by classifying the digital signals into first and second classes indicative of their influence on data quality and subjects them to error detection encoding capable of generating at least two error detection codes which respectively correspond to the first and second classes. A decoder receives the encoded digital signals classified into first and second digital signal classes, decodes the error detection codes, and generates error signals, corresponding to the respective digital signal classes, from which the quality of the received digital signals is estimated and the utility of the received digital signals is determined.

Abstract: Apparatus and an associated method calculates a CRC remainder for a block of data, such as a block of data retrieved from a CD-ROM device. CRC calculations are performed to provide assurances of data integrity subsequent to error corrections of the block of data. CRC remainders associated with N powers of two are stored in the look-up table. When calculating the CRC remainder, selected values stored in the look-up table are retrieved and combined to form the CRC remainder for the block of data.