Abstract: A device for sequentially storing input bit symbols of a given interleaver size N in a memory at an address from 1 to N and reading the stored bit symbols from the memory. The device comprises a look-up table for providing a first variable m and a second variable J satisfying the equation N=2m×J; and an address generator for generating a read address depending on the first and second variables m and J provided from the look-up table. The read address is determined by 2m(K mod J)+BRO(K/J), where K (0≦K≦(N−1)) denotes a reading sequence and BRO is a function for converting a binary value to a decimal value by bit reversing.

Abstract: Methods and apparatus for cyclic code codeword creation, error detection, and error correction are disclosed. The methods and apparatus utilize a set of permuted generator polynomials, each representing shifted and exclusive-ored (XORed) versions of the cyclic code generator polynomial according to a specific input bit pattern. The permuted generator polynomial may be provided by look-up table, hardware, or a software equivalent of this hardware. Use of the permuted generator polynomial greatly reduces the number of calculations required to calculate syndromes and trap errors in codewords. The permuted generator polynomial can be used to replace m iterations of a polynomial division operation with a single XOR operation. The bit pattern used to select a permuted generator polynomial is derived from the m high-order bits of the dividend at each step.

Abstract: Data of an input data series is written into a first interleaver. The data is read out column by column or row by row from the first interleaver and written into a plurality of second interleavers column by column or row by row. The data is read from each of the second interleavers and written into one or a plurality of third interleavers as necessary. The operation is repeated once or a plurality of times, thereby reading the data from each of the interleavers and generating a data series. Interleaving is carried out by generating interleaving patterns with a plurality of interleaving patterns. Further, an interleaving pattern suitable for turbo encoding or transmission is generated.

Abstract: Modem selection of Reed-Solomon codeword configuration to maximize error-corrected data rate given channel analysis. A lookup table of maximal codeword size given parity bytes and channel MSE allows precomputation.

Abstract: A decimated and interleaved multiplication table for finite fields as is useful in Reed-Solomon encoding computations. The generator polynomial coefficients determine the multiplication table content and ordering.

Abstract: A method for interleaving data in packet based communications includes interleaving elements of data in a source sequence to form an interleaved sequence and transmitting the interleaved sequence of the elements of the data. Adjacent elements of data in the interleaved sequence originally were separated by a first number of elements of data in the source sequence. Additionally, originally adjacent elements of data in the source sequence are separated by at least a second number of elements of data in the interleaved sequence.

Abstract: A method for performing a table look-up operation on a first table having N entries includes generating a second table having kN entries based on the first table. The method includes generating a first data field for the second table including table index values having a second interval derived from a first interval of the table index values of the first table and represented by an n-bit binary number; and generating a second data field including computed table values derived from the computed table values of the first table or computed based on the function defining the second data field. The method further includes computing an index value z, extracting address bits from the index value z, where the address bits are data bits more significant than the (n−1)th bit of the index value z, and addressing the second table using the address bits.

Abstract: A method for EFM demodulation is provided which includes a fuzzy logic-based ROM look-up conversion table capable of correcting data errors caused by invalid EFM bit patterns. The ROM look-up table contains the conversion data of valid EFM 14-channel bit patterns to 8-bit digital values. In addition to the valid pattern conversion, the ROM look-up table also includes fuzzy logic-based conversion of all invalid EFM 14-channel bit patterns to 8-bit digital values. The conversion of invalid EFM 14-channel bit patterns to 8-bit digital values allows error correction to begin during EFM demodulation using the inventive method. The invention improves the depth of the overall error correction system by correcting many of the data errors caused by invalid 14-channel bit patterns and most of the simple “off by one clock period” invalid patterns.

Abstract: A low weight encoding circuit of a power delivery system for encoding data sent out on an I/O bus with minimal current drawn so as to minimize signal and timing distortions. Such a low weight encoding circuit comprises a current balance tester arranged to test whether a predetermined number of data bits is current balanced; a current balance encoder and decode bit generator arranged to encode data bits and generate encoded data and corresponding decode bits if the predetermined number of data bits is not current balanced; and a latch arranged to latch either the data bits, via an I/O bus, if said predetermined number of data bits is current balanced or the encoded data and corresponding decode bits, via the I/O bus, if the predetermined number of data bits is not current balanced.

Abstract: Apparatus and method are described for fast code coverage analysis. The present invention for fast code coverage analysis utilizes a technique that provides for capturing an event every first time that a block of code is visited. This allows for generating an event only once during numerous executions of a code block. The generation of only one event provides for an execution time close to the speed of the original source code.

Abstract: An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.

Abstract: A packet is originated in a unit 10 as a data field DATA 11 plus a CRC (cyclic redundancy check) check field CRC 12 by a CRC circuit 13. This packet has a header HDR (with a routing information field RIF) added to it in a unit 20, converting it into a message for transmission through a message network. A check correction field CCF is computed by unit 23 in unit 20, by looking up precomputed check subfields stored with the routing subfields (the routing information field being constructed by selecting from the stored subfields), such that the CRC field is a valid CRC check field for the complete message. At the destination, unit 30 can be the final user unit, checking the entire message and extracting the data field DATA therefrom; the DATA field does not need to be checked, as the CRC field acts as a check both for the data field DATA alone and the entire message.

Abstract: A method and medium tangibly embodying the method of constructing a lookup table of modes for encoding data for transmission in a wireless communication channel from a transmit unit to a receive unit by using at least one quality parameter of the data and its first-order and second-order statistical parameters to arrange the modes in the lookup table. The first-order and second-order statistical parameters can be determined from a simulation of the wireless communication channel or from field measurements of the wireless communication channel. The modes in the lookup table are ordered by a target value of a communication parameter such as PER, BER, data capacity, signal quality, spectral efficiency, throughput or another suitable communication parameter set to achieve a desired quality of service. The quality parameter selected is conveniently a short-term quality parameter such as signal-to-interference and noise ratio (SINR), signal-to-noise ratio (SNR) or power level.

Abstract: A method and apparatus for encoding/decoding data, wherein for one embodiment, during [During] encoding, a microprocessor (201) calculates Ym by standard Reed-Solomon encoding techniques. The microprocessor (201) then utilizes Ym as an index to a look-up table (203), and is returned G0Ym, G1Ym, . . . , GK−1Ym, from the look-up table (203). During syndrome calculation, a second set of parity symbols are generated from the information symbols using the method similar to the encoder, in particular, values for G0Ym, . . . , GK-,Y. are obtained from a first look-up table (503) in a similar manner as encoder to determine the values for G0Ym, G1Ym, . . . , GK−1Ym. A second look-up table (505) is set up to determine roots of the error locator polynomial. The second look-up table consists of several tables and each table contains (Q−1) elements, where Q is the size of the GF(Q) field.

Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.

Abstract: In the disclosed error correcting scheme, information data is encoded and decoded in parallel and in the spectral or frequency domains based on a Reed-Solomon (RS) code. As a result, when compared with space domain decoding, the spectral decoding scheme of the present invention shifts some of the computationally intensive modules into the encoder thus reducing decoder complexity. Thus, integrated circuit implementations of the error correcting scheme of the present invention are faster, have reduced power dissipation and occupy less chip area than serial encoders and decoders.

Abstract: The data contents of memory systems are usually protected via an EDC system. When an error is present in the memory system, the EDC system can only recognize this error after the readout of faulty data.

Abstract: A programmable logic device (130) as may be used in a communication system device such as a digital subscriber line modem (408) to perform Reed-Solomon decoding upon a received frame of digital values is disclosed. The programmable logic device (130) may be implemented as a DSP (130) or a general purpose microprocessor, for example. According to one disclosed embodiment of the invention, a group of look-up tables (60) are arranged, each look-up table (60) associated with one of the possible power values of a finite field, number up to twice the number of correctable errors. The contents of each entry (SYN) of the look-up tables (60) correspond to the finite field (e.g., Galois field) multiplication of a primitive element raised to an index power with a character of the finite field alphabet. Galois field multiplications (62) in syndrome accumulation may now be performed with a single table look-up operation.

Abstract: A decode apparatus for decoding a plurality of encoded messages received over a noisy transmission link, eg., a satellite link or a radio telecoms link comprises a demodulator for demodulating analogue signals to produce a digitized bit stream; an analyzer comprising a received signal strength indicator; a carrier to noise ratio measurement means; a look up table for reading data describing an optimized number of decode iterations; an array of turbo code decoders, each having an associated local storage buffer; and a scheduler means for scheduling demodulated message packets to each of the plurality of decoder processors, depending upon an estimated optimum number of decode operations required for each message packet. Allocation of the message packets to the plurality of decode processors is made such as to optimize overall utilization of the decode processors.

Abstract: The specification relates to a method and an apparatus for generating cyclical redundancy code (CRC) by analyzing segmented groups of bits from a message concurrently, producing a temporary remainder value as a result of a multiple bit lookup from a generating CRC lookup table, using the temporary remainder or a portion thereof along with the next sequential segmented group of message bits as exclusive-or inputs, taking the result of the exclusive-or output and applying the result as a lookup value from the generating CRC lookup table. The process is repeated until the message groups have been depleted, at which time the message is completely coded and the temporary remainder existing at the time represents the CRC checkbits for the message. The recursive method developed in association with the present invention is called a Recursive Syndrome Expansion (RSE).

Abstract: The present invention provides an apparatus for providing error correction data in a digital data transfer system. The apparatus receives a clock signal and provides a first signal using the clock signal. Information data is received and a second signal is provided using the information data. The information data is received in groups which each have a first predetermined number of elements. A plurality of &agr;ROMs provide Galois Field multiples in look-up tables. The &agr;ROMs are addressed using the first signal to provide a first address component and using the second signal to provide a second address component. Modula mathematics are performed utilizing the values from the &agr;ROMs to generate error correction data. The error correction data is in groups each having a second predetermined number of elements. A RAM is accessible by a Trellis encoder and has an array for holding the information data elements and error correction data elements.

Abstract: An apparatus and method of processing signals is provided wherein an input signal has components representing aspects of a physical entity which are in a known state and other components which are unknown. The apparatus and method processes the signal in accordance with stored data representing rules which indicate which combinations of the components are possible. Rules are identified which involve the known components and all of the combinations consistent with the known states are identified. If all of these combinations have the same value for a particular component, the component is determined to have that value in the output signal. The rules are stored as binary representations of the possible combinations, and the components of the input and output signals may represent two allowable states, tautology (undefined state) and inconsistency (inallowable state).

Abstract: Received signal quality (bit error rate) estimates for a communication channel are provided by a receiver apparatus which is connected to the communication channel and which includes a convolutional decoder providing an estimate of a transmitted data frame and an associated final decision metric. The bit error rate estimate is generated by a bit error rate estimation circuit which includes a memory containing values for mapping the final decision metric to a corresponding bit error rate estimate. The bit error rate estimate may be provided to a control node of the communication channel which may use the provided estimate to take a corrective action such as determining whether a handover to a different communication channel should be initiated based upon the bit error rate. The communication channel may be an allocated channel of a cellular radio communication network servicing a mobile terminal receiver apparatus with the control nodes being the base stations of the cellular network.

Abstract: Data are coded with a first error correcting code to produce first coded bits. Control data are coded using a heavily redundant second error corrected code and added modulo 2 to the first coded bits. Decoding is performed by ascertaining which valid codeword of the second code (when added to the received codeword) gives the lowest error count when the resultant is decoded according to the first code.

Abstract: A novel code and method of code construction is disclosed. The disclosed code is a half rate block code designed to function optimally in a Raleigh fading channel. The disclosed code and method may be implemented in an 8-ARY QPSK modulation system. An alternative embodiment is a code and method of code construction for use in a 16-ARY QPSK modulation system. Both codes are systematic and use four symbols to represent two symbols. The first two symbols of the code are the information symbols. The second two symbols are parity symbols. The parity symbols are selected to provide maximum Euclidean distance between code words.

Abstract: A method and apparatus decodes a data packet in a communication system utilizing an error correcting code. Channel symbols are received (302), and channel symbol reliability weights are determined (306) for each. A code word symbol is formed (308) from the channel symbols, and the channel symbol reliability weights are mapped (312) into a code word symbol reliability weight, which is set equal to the minimum channel symbol reliability weight mapped for the code word symbol. The method and apparatus continues (318) to similarly process additional channel symbols until the data packet is completely collected. Then, a predetermined number of code word symbols having the lowest code word symbol reliability weights in the data packet are marked (320) as erasures, after which the data packet is decoded (322) by utilizing a soft decision decoding technique.

Abstract: An error correcting system transforms a degree-five error locator polynomial .sigma.(x) into the polynomial w(y)=y.sup.5 =b.sub.2 y.sup.2 +b.sub.1 y+b.sub.0, where b.sub.1 =0 or 1, and y=.sigma.(x), and determines the roots of .sigma.(x) based on the roots of w(y). The polynomial w(y) has (2.sup.M).sup.2 solutions over GF(2.sup.M), rather than (2.sup.M).sup.5 solutions, since for any solution with b.sub.2 =h.sub.2, b.sub.0 =h.sub.0 and b.sub.1 =1, there is no such solution with b.sub.2 =h.sub.2, b.sub.0 =h.sub.0 and b.sub.1 =0. Conversely, if there is such a solution with b.sub.1 =0 there are no such solutions with b.sub.1 =1. The system can thus use a table that has 2.sup.2M entries and is addressed by {b.sub.2, b.sub.0 }. The table produces roots y=r.sub.i, i=0, 1, 2, 3, 4, and the system then transforms the roots y=r.sub.i to the roots of .sigma.(x) by calculating x=.sigma..sup.-1 (y). To further reduce the overall table storage needs, the table may include in each entry four roots r.sub.

Abstract: A packet is originated in a unit 10 as a data field DATA 11 plus a CRC (cyclic redundancy check) check field CRC 12 by a CRC circuit 13. This packet has a header HDR (with a routing information field RIF) added to it in a unit 20, converting it into a message for transmission through a message network. A check correction field CCF is computed by unit 23 in unit 20, by looking up precomputed check subfields stored with the routing subfields (the routing information field being constructed by selecting from the stored subfields), such that the CRC field is a valid CRC check field for the complete message. At the destination, unit 30 can be the final user unit, checking the entire message and extracting the data field DATA therefrom; the DATA field does not need to be checked, as the CRC field acts as a check both for the data field DATA alone and the entire message.