Abstract: Concatenated codes are improved, and a memory capacity and a memory diagnosis circuit are reduced. Address control used in an interleaver of related art is applied to a register included in a syndrome arithmetic circuit or a check code calculation circuit of related art, and an arithmetic operation result equivalent to that obtained by interleaving is derived.

Abstract: The present invention provides a method for enhancing reliability of information transmission by (a) establishing a matrix based on the length of bits of valid information in frame time slots; and creating a new matrix by presetting Error Correction Coding (ECC) for rows and columns of said matrix; (b) adopting the 1st Interleaving method to re-allocate bits which have been processed twice by using said ECC in said new matrix, to both ends of said frame time slots; and (c) adopting the 2nd Interleaving method to re-allocate the remaining bits in said new matrix to the middle of said frame time slots. After processed like this, the anti-interfering ability of the bits at both ends of TDMA frame time slot can be significantly enhanced, and the bit-error rate is decreased most, and all redundancy bits of Hamming codes can be arrayed at both ends of TDMA frame time slot.

Abstract: A deinterleaver for a wireless communication device is provided that is simple and inexpensive to implement. In particular, a deinterleaver for deinterleaving a stream of data bits representing a plurality of symbols that have been interleaved using a multi-stage interleaving scheme is provided, the deinterleaver comprising preprocessing means for ordering the data bits in the stream into pairs, such that the data bits in the pair are consecutive data bits from a symbol; at least one memory for storing the paired bits, such that each pair of data bits is stored in a respective location in the memory; and a read and write address generator for the at least one memory, the generator being adapted to determine the addresses in the at least one memory that pairs of data bits are to be stored, and to determine the addresses in the at least one memory that pairs of data bits are to be read from.

Abstract: A system and method for erasure flagging for errors-and-erasures decoding in storage devices includes determining a deviation measure between a read/write head position relative to a track of symbols in storage media. A reliability value is determined for the symbols based on the deviation measure. Flagging the symbols with a reliability value below a threshold as erasures is performed. The symbols are decoded using errors-and-erasures decoding in an iterative procedure.

Abstract: A multiprotocol encapsulation forward error correction (MPE-FEC) frame comprising datagrams and FEC data is shown wherein an MPE encapsulator places datagrams in MPE sections and FEC data in MPE-FEC sections. A time slicing block forms a sequence of bursts and dividing the MPE-FEC frame between bursts, such that MPE sections are sent in at least two bursts. The time slicing block adds a burst number parameter to headers of the MPE and MPE-FEC sections to enable a terminal to determine whether to expect further bursts carrying data from the MPE-FEC frame.

Abstract: A structured interleaving/de-interleaving scheme enables efficient implementation of encoding/decoding based on two-dimensional product codes (2D PC). An encoder has an integrated architecture that performs structured interleaving and PC coding in an integrated manner in which locations in the interleaved data stream are related to row and column indices for the 2D PC coding based on closed-form expressions. In one embodiment, a corresponding decoder implements two-stage low-density parity-check (LDPC) decoding based on the same relationships between locations in the interleaved data stream and row and column indices for the LDPC decoding.

Abstract: The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

Abstract: Error correction coding is provided for codeword headers in a data tape format, such as a Linear Tape-Open, Generation 4 (LTO-4) data tape format. The data tape format defines a codeword quad as having first and second codeword headers interleaved with first and second codeword pairs, each codeword header comprising N bytes ck=c0, c1, . . . , cN?2, cN?1 wherein K bytes c0-cK?1 of the first and second headers in a codeword quad differ such that if one is known the other can be inferred. Each header byte ck of a codeword quad is redefined as comprising two interleaved (m/2)-bit nibbles, ek, ok. For each header, nibbles eK-eN?1 and nibbles oK-oN?1 are generated as a function of nibbles, e0-eK?1 and o0-oK?1, respectively. A codeword is assembled with the redefined headers the codeword quad is then recorded onto a recording medium.

Abstract: A system for broadcasting the same data in concatenated convolutional coded (CCC) form from a network of 8-VSB amplitude-modulation transmitters operated with different radio-frequency carrier waves assigns the coded data to time-interleaved ones of time slots that are universal throughout the network. Therefore, a mobile/handheld (M/H) receiver with a single frequency-agile tuner can provide frequency-diversity reception of the time-interleaved data in CCC form. Alternatively, an M/H receiver with two tuners is used to provide frequency-diversity reception of the time-interleaved data in CCC form. The system for a network of 8-VSB AM transmitters that broadcast the same data in CCC form can further provide for each 8-VSB AM transmitter to make repeated transmissions of data in CCC form, to facilitate iterative-diversity reception of those transmissions by M/H receivers.

Abstract: Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a detector including an input to receive a decoded codeword and including circuitry to detect the presence of one or more trapping sets of bits in the decoded codeword. A selection processor is coupled to the detector to select one from a group of trapping sets and correct one or more bits in the decoded codeword based on statistical measures associated with the one or more trapping sets of bits.

Abstract: A system for processing wireless high definition video data to be transmitted in an uncompressed format over a wireless medium is disclosed. In one embodiment, the system includes i) a Reed Solomon (RS) encoder configured to encode a video data stream, ii) a parser configured to parse the RS encoded data stream into a plurality of sub-video data streams, iii) a plurality of convolutional encoders configured to encode in parallel the plurality of sub-video data streams so as to create a plurality of encoded data streams and iv) a multiplexer configured to input the plurality of encoded data streams and output a multiplexed data stream, wherein the multiplexed data stream is transmitted. One embodiment of the invention provides strong error protection for data communications at very high throughput, and makes parallel Viterbi decoding implementation easier at the receiver side.

Abstract: A receiving system and a method of processing data are disclosed herein. The receiving system includes a receiving unit, an equalizer, a block decoder, and an RS frame decoder. The receiving unit receives and demodulates a broadcast signal. Herein, the broadcast signal includes at least a mobile service data and a data group including a plurality of known data sequences. The equalizer channel-equalizes the data group included in the demodulated broadcast signal by using the plurality of the known data sequences. The block decoder performs turbo-decoding in block units on data of portion allocated to the channel equalized data group. And, the RS frame decoder configures an RS frame by gathering data of the turbo decoded M number of portions, wherein M is an integer greater than 1 (M>1).

Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.

Abstract: Methods and techniques are disclosed for correcting the effect of cycle slips in a coherent communications system. A signal comprising SYNC bursts having a predetermined periodicity and a plurality of known symbols at predetermined locations between successive SYNC bursts is received. The received signal is partitioned into data blocks. Each data block encompasses at least data symbols and a set of check symbols corresponding to the plurality of known symbols at predetermined locations between a respective pair of successive SYNC bursts in the signal. Each data block is processed to detect a cycle slip. When a cycle slip is detected, the set of check symbols of the data block are examined to identify a first slipped check symbol, and a phase correction applied to data symbols of the data block lying between the first slipped check symbol and an end of the data block.

Abstract: The present invention relates to a method for providing an equal error protection to data packets in a burst transmission system. The data packets are grouped based upon respective priority levels and error protection is provided to each group of data packets based upon the respective priority level. The error protection codes for each group of data packets depending on the respective priority level is created using data of data packets of the group which are contained in the data section (20) of two or more bursts (10) forming a first set of bursts (50, 50.B, 50.E, 55) and the created error protection codes are transmitted in the error protection section (30) of one or more bursts (10) forming a second set of bursts (60, 60.B, 60.E, 65). The invention further relates to a burst transmission system for performing said method.

Abstract: Apparatus and methods are provided to correct burst errors from a communication channel. Embodiments may include correcting burst errors in received data using a decoder configured as a Meggitt decoder with an additional selection criterion to correct a burst error having a length larger than the code error correction capability.

Abstract: According to an example embodiment, an apparatus may include logic. The apparatus may be configured to: determine, based on an error location polynomial, an error location syndrome corresponding to an actual location of a burst error in a data block; select a burst error pattern that is less than or equal to M bits, and having no more than Y consecutive zeros within the burst error, where M is greater than the order of the error location polynomial; determine an error pattern syndrome based on the selected burst error pattern and the error location polynomial; and determine an actual location of the burst error in the data block based on the error location syndrome and the error pattern syndrome.

Abstract: Circuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i) generating an address corresponding to a memory location of a single-port memory module into which the data unit is to be stored, and (ii) storing the data unit in the memory location based on the address generated for the data unit. Each address is generated in accordance with the first pre-determined function, and each memory location of the single-port memory has a different delay associated with the memory location. The method further includes reading each data unit out of the single-port memory in accordance with the first pre-determined function, wherein data units of the data block are reordered based on each different delay associated with each memory location.

Abstract: An SDRAM convolutional interleaver with two paths. Symbols are assigned to a given one of the two paths, then are sorted to minimize (to one) a number of breaks in a sequential Interleaver write address. After sorting, the symbols are stored staggered in SRAM and burst written to SDRAM. Before writing to SDRAM, data is accumulated for four symbols at a time, and the data is written four symbols wide to optimize SDRAM access time. 8 bit symbols are written 32 bits at a time to SDRAM.

Abstract: A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

Abstract: A system comprising a plurality of channel detectors (CDs) receiving quantized and equalized ISI channel information indicative of an LDPC codeword. The channel information is split for input to the CDs, such that each CD receives channel information indicative of a portion of the LDPC codeword. Each CD outputs at least first soft information for bits of the codeword portion of that CD. The first soft information for the codeword is received by an LDPC decoder, which uses the soft information to produce a user bit sequence and second soft information about the user bit sequence. The system can cause the second soft information to be input to the plurality of CDs, such that iterative processing can occur for the codeword. Other aspects include a system providing clocking of one or more CDs at a frequency selected to balance codeword throughput of the CDs with codeword throughput of an LDPC decoder clocked by a second clock, and methods according to each system.

Abstract: A MIMO transmitting apparatus that achieves a flexible control in accordance with variation of a propagation environment to reduce the number of retransmissions is disclosed. An intra-code-word interleaver performs an interleave process on bits included in symbols to be simultaneously transmitted from a plurality of transmitting antennas. When performing the intra-code-word interleave process, the intra-code-word interleaver performs the interleave process in accordance with an interleave pattern notified from an interleave pattern table. A counter counts a number of retransmission requests, and outputs the number of retransmission requests to the interleave pattern table. The interleave pattern table stores interleave patterns to be used for the intra-code-word interleave process for the respective numbers of retransmission requests, and notifies the intra-code-word interleaver of an interleave pattern in accordance with the number of retransmission requests.

Abstract: In a decoding apparatus in a portable Internet terminal, a channel encoded symbol received from a transmitter is decoded by one of a chase-combining scheme and a code-combining scheme selected based on an ID value of the subpacket indicating a start position of the symbol. In this case, the chase-combining scheme is partly used for the encoded symbol of the information bit. With such a mode, decoding can be performed at a low code rate.

Abstract: An error correction circuit, an error correction method, and a semiconductor memory device including the error correction circuit are provided. The error correction circuit includes a partial syndrome generator, first and second error position detectors, a coefficient calculator, and a determiner. The partial syndrome generator calculates at least two partial syndromes using coded data. The first error position detector calculates a first error position using a part of the partial syndromes. The coefficient calculator calculates coefficients of an error position equation using the at least two partial syndromes. The determiner determines an error type based on the coefficients. The second error position detector optionally calculates a second error position based on the error type.

Abstract: In a method for transmitting data of various traffic types an xDSL modem is utilized. Detectors are used to detect the traffic types of the data which are to be transmitted and the detected traffic types are taken as a basis for dynamically adjusting a data transmission rate for the xDSL modem.

Abstract: Reduced complexity ARP (almost regular permutation) interleaves providing flexible granularity and parallelism adaptable to any possible turbo code block size. A novel means is presented by which any desired turbo code block size can be employed when only requiring, in only some instances, a very small number of dummy bits. This approach also is directly adaptable to parallel turbo decoding, in which any desired degree of parallelism can be employed. Alternatively, as few as one turbo decoder can be employed in a fully non-parallel implementation as well. Also, this approach allows for storage of a reduced number of parameters to accommodate a wide variety of interleaves.

Abstract: There are provided a content data transmission method, device, and program that minimize serious disturbances in reproduced content on the reception side, caused by a transmission error of encoded data, without sending feedback information from the reception side to the transmission side. When an encoder creates encoded data to be distributed, the encoder creates plural items of encoded data at the same time or creates FEC data at the same time in advance and, when storing the data in a file, stores the data as if the data were one item of encoded data. When a distribution server distributes the data using the file, the plurality of items of encoded data are automatically distributed at the same time and the FEC data is distributed. A client receives the plurality of items of encoded data or the FEC data to reduce the probability of data shortage due to a packet loss and, as a result, the deterioration in the image quality and the audio quality is reduced.

Abstract: A method and apparatus for receiving a wireless signal of a control channel wherein the wireless signal includes control information and an N bit field. The N bit field includes an N bit cyclic redundancy check (CRC) and an N bit user equipment (UE) identity wherein the value of N is a positive integer. The UE identity may be any one of a plurality of UE identities associated with the UE.

Abstract: A system including a forecasting module, a decoder module, and an error detecting module. The forecasting module is configured to forecast a number of erasures in an input signal, where the erasures include information about errors in the input signal due to a burst error. The decoder module is configured to decode codewords received in the input signal based on the erasures in response to the number of the erasures being less than or equal to a predetermined threshold. The decoder module is configured to not decode the codewords based on the erasures in response to the number of the erasures being greater than the predetermined threshold. The error detecting module is configured to (i) detect the burst error and (ii) decode the codewords in response to the decoder module not decoding the codewords due to the number of the erasures being greater than the predetermined threshold.

Abstract: Disclosed is a transmission device which transmits a systematic code obtained by adding parity bits to information bits. When the code rate of the systematic code is a value in a specific range determined by the decoding characteristic in a case where dummy bits are not inserted, a dummy bit insertion portion inserts dummy bits into the information bits and shifts the decoding characteristic, so that the code rate assumes a value outside a specific range determined by the decoding characteristic after shifting. An encoding portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the encoding to generate a systematic code, and a rate matching portion, performs rate matching such that the size of the systematic code is equal to a size determined by the physical channel transmission rate, and transmits the systematic code.

Abstract: In transmission systems using digital video broadcasting standards for handheld terminals data is transmitted in bursts. Due to the restricted computing time, buffering of one or more bursts is necessary. The invention provides a memory optimalization for consecutive burst support. Thereby, a cyclic or non-cyclic memory model for a memory unit (19) of the device (1) for receiving bursts is provided.

Abstract: A decoding apparatus and method are described. The decoder includes N successive decoder groups numbered 1 to N arranged in series. Each decoder group includes primary decoding means for decoding the first sequence of codewords in combination with the source sequence of symbols to produce a sequence of primary decoded symbols; intermediate interleaving means for interleaving the sequence of primary decoded symbols using intra-block permutations on the source sequence of symbols and inter-block permutations on each intra-block permuted block across the predetermined number of the intra-block permuted blocks to produce a sequence of intermediate symbols; secondary decoding means for decoding the second sequence of codewords in combination with the sequence of intermediate symbols and a sequence of interleaved source symbols to produce a sequence of secondary decoded symbols; and de-interleaving means for de-interleaving the sequence of secondary decoded symbols to produce a sequence of estimated symbols.

Abstract: A decoding circuit includes a mixed modulation memory access circuit responsive to burst rejection information. The mixed modulation memory access circuit selectively accesses burst memory locations containing a valid burst of coded bits. The mixed modulation memory access circuit selectively avoids accessing burst memory locations containing a rejected burst of coded bits based on the burst rejection information. In one example, the mixed modulation memory access circuit accesses the valid burst when the burst rejection information indicates that the memory location contains valid bursts. In one example, the mixed modulation memory access circuit generates zero confidence information when the burst rejection information indicates that the memory location contains rejected bursts.

Abstract: Provided are a forward error correction decoder and a method thereof. The method comprises: generating mapping information on a location of a symbol; deciding a location of an error in a packet; deciding an erasure of a subsequent packet following the packet on the basis of the error location and the mapping information; and decoding the subsequent packet on the basis of the erasure.

Abstract: A wireless communications apparatus according to the present invention includes a scheduler which allocates, to a user apparatus, at least one resource block included in a system bandwidth; an interleaver which rearranges an order of bits within a bit sequence according to a specified pattern; a unit which creates a transmit symbol including the interleaved bit sequence; and an interleaving-pattern determining unit which determines a range of the bit sequence to be rearranged based on a number of the resource blocks, a data modulation scheme, and a channel encoding rate, determines a rearranging pattern according to the range, and communicates the determined pattern to the interleaver.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: A digital data recording/reproducing method includes the steps of: interleaving data on a PI code for each PI code of a 208-row ECC block; and converting a short burst error into random errors by dispersing errors on the PI codes. Moreover, the digital data recording/reproducing method increases correction capability against several bytes to several tens bytes of errors generated at random without changing burst error correction length by performing this processing for respective PI codes by using interleave rules that are different as much as possible from one another.

Abstract: A method for operating a contention-free interleaver for channel coding is provided that includes generating a sub-table based on a data block size, N, and an offset vector, v, of length x and generating an interleave table based on the sub-table. For a particular embodiment, the interleave table is generated based on the sub-table by generating a plurality of multiplets that together form the interleave table. In addition, the sub-table may be generated based on the data block size and the offset vector by (i) rounding the data block size up to a nearest multiple of the length, x, of the offset vector to generate a modified block size, N?, and (ii) generating the sub-table of a size equal to N?/x.

Abstract: Identifying a burst error is disclosed. Identifying includes computing a syndrome check polynomial corresponding to a burst of length up to 2t?1 in received data and identifying a shortest burst based on the longest consecutive root sequence of the syndrome check polynomial. The received data is corrected based at least in part on the shortest burst.

Abstract: A method, a device, and an apparatus for correcting bursts are disclosed. The method includes: calculating a correction vector according to a received codeword and a check matrix, wherein the check matrix is an Overlapped Quasi Dual Diagonal Matrix; determining a length and position of a burst according to a longest zero element vector between two nonzero elements in the correction vector when the correction vector is nonzero; and calculating out an error mode according to the correction vector and the length of the burst, obtaining an error mode polynomial according to the error mode, correcting the received codeword according to the error mode polynomial, and obtaining a corrected codeword polynomial. The PBC-based implementation method for cyclic codes herein can correct more burst errors than the conventional cyclic code decoding method.

Abstract: In a method of detecting an error pattern in a codeword transmitted across a noisy communication channel, a codeword is detected. A syndrome is then generated by applying a generator polynomial to the codeword. The generator polynomial is adapted to produce a distinct syndrome set for each of “L” (L>1) different error patterns potentially introduced in the codeword during transmission across the communication channel. A type of an error pattern within the codeword is detected based on the syndrome or a shifted version of the syndrome, and then a start position of the error pattern within the codeword.

Abstract: Various embodiments include apparatus, methods, and systems that operate to extend the processes of reading, modifying, and writing data stored in or being provided to a memory array without interrupting a continual stream of data to be written into the memory array. Embodiments may include an apparatus comprising a memory array, and an error code module coupled to the memory array with a data buffer having a plurality of data burst registers operable to receive a plurality of data bursts to be written to the memory array on a corresponding plurality of consecutive clock cycles. The error code module is operable to perform a read/modify/write process on each of the plurality of data bursts within a time period no longer than a period of two consecutive cycles of the plurality of consecutive clock cycles.

Abstract: A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations.

Abstract: A computing device boot-up method begins by a processing module detecting a boot-up of the computing device. The method continues with the processing module addressing a distributed basic input/output system (BIOS) memory to retrieve a plurality of error coded BIOS data slices. The method continues with the processing module reconstructing BIOS data from the plurality of error coded BIOS data slices using an error coding dispersal function. The method continues with the computing device booting up in accordance with the BIOS data.

Abstract: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets.

Abstract: A method and system to improve the link budget of a wireless system using fast Hybrid Automatic Repeat Request (HARQ) protocol. In one embodiment of the invention, the Medium Access Control (MAC) logic in a base station determines whether the quality of the communication link with a mobile station is bad. When the MAC logic in the base station determines that the quality is bad, the base station uses a fast Hybrid Automatic Repeat Request (HARQ) protocol to indicate to the mobile station to send identical information to the base station in each of a plurality of successive or consecutive communication intervals before processing any received identical information from the mobile station. The fast HARQ protocol reduces the latency of receiving the identical information correctly, as compared with the current HARQ protocol.

Abstract: Error bursts are randomized by an interleaver which makes use of “set leaders” to generate permutation indices. The permutation indices are used to route bits from initial positions in an input bit stream to re-arranged or randomized positions in an output bit stream. When the output bit stream is then transmitted and subsequently received by a de-interleaver which returns the received bits to their initial, pre-randomized positions, the resulting received signal has an acceptable bit error rate.

Abstract: In cable modem termination systems (CMTS) and other information transmission systems, a method for changing the interleave depth associated with each data stream is provided. This may be done dynamically, and for any subset of downstream devices such as modems. The interleave depth may be set on an individual device level. Embodiments may decrease data receiving latency on devices that do not suffer from error rates, such as caused by burst noise, while maintaining throughput on devices with high error rates.

Abstract: A system for detecting one or more localized burst errors in a receiving message comprised of a plurality of codewords. The system comprises a trellis code decoder for decoding a receiving message with a plurality of codewords and calculating one or more cumulative metrics of a maximum likelihood path and one or more alternative paths from the receiving message, an error detection code (EDC) decoder for detecting existence of one or more errors in the decoded receiving message received from the trellis decoder, and a localized burst error detector activated by the EDC decoder upon detecting the existence of one or more errors in the decoded receiving message to identify at least one corrupted codeword among the plurality of codewords using the one or more cumulative metrics of a maximum likelihood path and the one or more alternative paths, wherein the system requests the re-transmission of the corrupted codeword.