Abstract: In some implementations, a memory device may detect a read command associated with reading data stored by the memory device. The memory device may determine whether the read command is from a host device in communication with the memory device. The memory device may select, based on whether the read command is from the host device, one of a first voltage pattern or a second voltage pattern to be applied to memory cells of the memory device to execute the read command, wherein the first voltage pattern is selected if the read command is from the host device and the second voltage pattern is selected if the read command is not from the host device, wherein the second voltage pattern is different from the first voltage pattern. The memory device may execute the read command using a selected one of the first voltage pattern or the second voltage pattern.

Abstract: Various implementations described herein relate to systems and methods for a Solid State Drive (SSD) to manage data in response to a power loss event, including writing data received from a host to a volatile storage of the SSD, detecting the power loss event before the data is written to a non-volatile storage of the SSD, storing the write commands to a non-volatile storage of the SSD, marking at least one storage location of the SSD associated with the write commands as uncorrectable, for example, after the power is restored.

Abstract: A scheme for determining a flipping energy used in a bit-flipping decoder. The flipping energy is determined based on: a weight of at least one check node coupled to a column; a syndrome as a product of a noisy codeword and a parity check matrix; and a hard decision value of a previous iteration and a channel output value associated with the column.

Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose-Chaudhuri-Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose-Chaudhuri-Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Abstract: Exemplary methods, apparatuses, and systems include a media temperature manager receiving operating temperature measurements for a memory subsystem. The media temperature manager generates an average temperature using the operating temperature measurements. The media temperature manager determines that the average temperature satisfies a first value for a dynamic temperature threshold. The dynamic temperature threshold indicates a temperature at which the memory subsystem throttles media operations. The media temperature manager increases the dynamic temperature threshold to a second value in response to the average temperature satisfying the first value for the dynamic temperature threshold.

Abstract: A controller includes an Error Correction Code (ECC) encoder adding a first parity to data to generate a data set, and encoding the data set to generate a first parity data set, a buffer temporarily storing the first parity data set, an ECC decoder decoding the first parity data set received from the buffer to generate a decoded data set, a first checker performing a Low Density Parity Check (LDPC) encoding on the decoded data set to generate an LDPC data set to which a second parity is added, and a second checker performing a syndrome check operation on the LDCP data set including the first and second parities.

Abstract: A memory includes a storage circuit, a first reading circuit, a second reading circuit, and a plurality of correcting circuits. The storage circuit includes a plurality of sense amplifier arrays and a plurality of storage unit arrays. The sense amplifier arrays and the storage unit arrays are arranged alternately, and the sense amplifier arrays are configured to perform data reading and writing on the storage unit arrays. The first reading circuit is configured to compare a reference voltage signal with a signal on a first data line corresponding to the first reading circuit, and output a comparison result as read-out data. The second reading circuit is configured to compare the reference voltage signal with a signal on a first data line corresponding to the second reading circuit, and output a comparison result as read-out data.

Abstract: Provided is a system, an information processing method, and a non-transitory storage medium that hardly cause improper operations when a plurality of quantum processors is connected to configure a logical quantum bit.

Abstract: Systems, apparatuses, and methods related to memory device protection are described. A quantity of errors within a memory device can be determined and the determined quantity can be used to further determine whether to utilize single or multiple memory devices for an error correction and/or detection operation. Multiple memory devices need not be utilized for the error correction and/or detection operation unless a quantity of errors within the memory device exceeds a threshold quantity.

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device, to perform operations including initiating a read operation with respect to a block of the memory device, selecting, based on a set of criteria, a default read offset from a set of read offsets, wherein the set of criteria includes at least one of: a parameter related to trigger rate, or an amount of time that an open block is allowed to remain open to control threshold voltage shift due to storage charge loss, and applying the default read offset to a read operation performed with respect to the block.

Abstract: It is suitable for the field of computer graphic processing technologies, and provides a method and apparatus for repairing a graphics processing unit (GPU) video memory access based on active error detection. A small video memory is first distributed and used for error detection of video memory access, and a problem of video memory data access abnormality is found in time through a regular active detection. When the video memory data access abnormality is found, a GPU desktop driving module can suspend a display picture update operation, and a GPU kernel driving module first suspends all video memory access, then re-initializes a video memory controller and repairs the video memory access abnormality, and then restores an access of all the modules to a video memory to normal, refreshes a desktop, and restores a graphic desktop to a normal state.

Abstract: A semiconductor system includes a controller configured to count the number of error check scrub (ECS) operations and configured to generate ECS information that includes information with regard to an address at which the ECS operation is to be performed based on the number of ECS operations. The semiconductor system further includes a memory apparatus configured to perform the ECS operation on a region that is selected by the ECS information.

Abstract: Methods, systems, and devices for read operations for a memory array and register are described. In some examples, a memory device may include one or more memory arrays and one or more registers (e.g., one or more mode registers). The memory device may include circuitry that allows for a command to access a memory array and a command to access a register to be received consecutively (e.g., during consecutive sets of clock cycles). Because the commands may be received during consecutive sets of clock cycles, the corresponding data may also be output from the memory array and register during consecutive clock cycles.

Abstract: According to one embodiment, a storage system includes a network interface controller, a volatile memory and a storage device. The network interface controller is configured to communicate with a client using remote direct memory access. The network interface controller is configured to store write data and a submission queue entry including a write request of the write data transferred using the remote direct memory access in the volatile memory. The storage device is configured to write, when the submission queue entry is stored in a submission queue of the volatile memory, the write data to the storage device based on the submission queue entry.

Abstract: Provided are a memory controller, system, and method for generating multi-plane reads to read pages on planes of a storage die for a page to read. A memory controller determines planes for a read to a page. A storage die of the storage dies includes a plurality of planes having a plurality of blocks and the blocks have pages. The page to read is implemented in pages on the planes. The memory controller determines threshold voltages for the pages in the determined planes and determines a derived threshold voltage from the determined threshold voltages. The derived threshold voltage is used to perform multi-plane reads of the pages from the determined planes.

Abstract: An ECC decoder includes: a memory comprising a memory region; a first converter configured to transmit a hard bit, received from a channel, to the memory to store the hard bit in a first area of the memory region; a second converter configured to receive the hard bit read from the first area and output a reliability value corresponding to the hard bit, whenever a hard decoding operation on the hard bit is iterated; and a variable node configured to perform the hard decoding operation using the reliability value.

Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.

Abstract: A selecting bad data column method suitable for a data storage device is provided. The data storage device includes a control unit and a data storage medium. The selecting method performed by the control unit includes: reading written data of each data column as read data; comparing the read data and the written data of each data column to calculate an average number of error bits of each data column; determining whether the average number of error bits of each data column is greater than or equal to a predetermined value; and recording a data column as a bad data column when the average number of error bits of the data column is greater than or equal to the predetermined value. In this way, in order to avoid the problems that the error correction code can't be corrected or the correction capability is excessively consumed.

Abstract: Methods and systems include memory devices with a memory array comprising a plurality of memory cells. The memory devices include a control circuit operatively coupled to the memory array and configured to receive a read request for data and to apply a plurality of read voltages to the memory array based on the read request. The control circuit is further configured to perform a data analysis for a first set of data read based on the application of the plurality of read voltages and to derive a demarcation bias voltage (VDM) based on the data analysis. The control circuit is also configured to apply the VDM to the memory array to read a second set of data.

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising determining a parameter value of a select gate associated with a first set of memory cells; responsive to determining that the parameter value satisfies a threshold criterion, marking the first block in a grown bad block (GBB) data structure; performing one or more pulse operations on the first block to invalidate data stored on the block; receiving, from a host system, an enhanced erase command referencing a second block; and responsive to determining that the second block is marked in the GBB data structure, discarding the enhanced erase command.

Abstract: Methods, systems, and devices for read threshold adjustment techniques for memory are described. A memory device may read a codeword from a memory array of the memory device using a read threshold having a first value. The memory device may increment one or more counters of the memory device based on reading the codeword. The counter may indicate a quantity of bits of the codeword that correspond to a first logic value. The memory device may detect an error, such as an uncorrectable error, in the codeword based on reading the codeword. The memory device may adjust the read threshold from the first value to the second value based on the quantity of bits indicated by the counter. The memory device may read the codeword using the read threshold having the second value.

Abstract: The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first parity data for the first command is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first parity data is copied from the RAM1 to a parking section in the storage unit, and second parity data associated with the second zone is copied from the parking section to the RAM1. The second parity data is then updated in the RAM1 with the data of the second command and copied to the parking section.

Abstract: Dynamic Random Access Memory (DRAM) and a logic layer having direct access to the DRAM which provides symbolic addressing services. These services are provided by sequencers in the logic layer. The sequencers maintain a DRAM row or row-pair in sorted order, find a location and insert a new data element into the row or row-pair, all while preserving the sorted order. The sequencer is a plurality sequencer groups, each a plurality of sequencer cells. The sequencer cells perform a highly parallel pipeline insertion of a new data element. The logic layer also defines a Self-Addressing Memory Central Processing Unit (SamPU) operatively coupled to, and configured to control, the sequencer. The logic layer provides program memory for SamPU and a memory cache to build an index database. The database is subject to mitosis to accommodate the overflow of any item in the index database.

Abstract: A storage subsystem read voltage determination system coupled to a first storage subsystem may read data from the first storage subsystem at a plurality of different read voltage sets and, for each of the plurality of read voltage sets, generate a respective bit error probability distribution of a number of bit errors per codeword provided by the data read from the first storage subsystem. The storage subsystem read voltage provisioning system also generates an error correction capability graph associated with error correction code used by the first storage subsystem and, based on the bit error probability distributions and the error correction capability graph, generates a respective average codeword error rate for each of the plurality of read voltage sets. The storage subsystem read voltage provisioning system then identifies a first read voltage set for which a minimum average codeword error rate was determined.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a base station, a physical downlink shared channel (PDSCH) transmission in one or more of a half-duplexing mode or a full-duplexing mode. The UE may attempt to decode the PDSCH transmission using a low-density parity-check (LDPC) decoder. The UE may transmit, to the base station, feedback that indicates a difference between a half-duplex channel quality and a full-duplex channel quality based at least in part on one or more decoding parameters associated with the LDPC decoder. Numerous other aspects are described.

Abstract: A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.

Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

Abstract: A decoder including a main memory, a flag memory and a decoding logic is provided. The flag memory is configured to store flag data and the decoding logic configured to perform an iteration. Further, the decoding logic is configured to: perform an ith operation using first data, wherein i is a natural number, flag-encode second data that is results obtained by performing the ith operation on the first data, store results obtained by performing the flag encoding on the second data in the flag memory as first flag data if the flag encoding succeeds, and store predetermined second flag data that is different from the first flag data of the second data in the flag memory if the flag encoding fails.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

Abstract: Apparatuses, systems, and methods for error correction. A memory array may be coupled to an error correction code (ECC) circuit along a read bus and a write bus. The ECC circuit includes a read portion and a write portion. As part of a mask write operation, read data and read parity may be read out along the read bus to the read portion of the ECC circuit and write data may be received along data terminals by the write portion of the ECC circuit. The write portion of the ECC circuit may generate amended write data based on the write data and the read data, and may generate amended parity based on the read parity and the amended write data. The amended write data and amended parity may be written back to the memory array along the write bus.

Abstract: A system includes a memory array of sub-blocks, each sub-block including groups of memory cells, and a processing device. The processing device causes a first wordline to be programmed through the sub-blocks with a mask by causing to be programmed, to a first voltage level: a first group of memory cells of a first sub-block; and a second group of memory cells of a second sub-block. The processing device further scans a second wordline that has been programmed and is coupled to the first wordline, scanning includes: causing a custom wordline voltage to be applied to the second wordline, the custom wordline voltage to select groups of memory cells corresponding to those of the first wordline programmed to the first voltage level; concurrently reading data from the selected groups of memory cells of the second wordline; and performing, using the data, an error check of the second wordline.

Abstract: This disclosure provides methods, devices and systems for transmitting, to one or more local area network clients of the device, a multicast message indicating an available network slice, receiving, from a first local area network client of the one or more local area network clients based on the multicast message, a request to access the available network slice, establishing, at the device based on receiving the request, a connection associated with the available network slice, and transmitting, to the first local area network client based on establishing the connection, a confirmation to access the available network slice.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to decode data from the memory device, store a decoder level for the decoded data in a bloom filter, receive a read command for the data, and decode the data using a decoder associated with the stored decoder level. The decoder level corresponds to a decoder having a certain decoding strength. The decoder level is stored in the bloom filter as an ID, where a bloom filter may be associated with each decoder level.

Abstract: A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.

Abstract: Technology is disclosed herein for efficient use of volatile memory that is used for accumulating parity data of user data being written to non-volatile memory cells. A memory controller may replace primary parity in a first portion of a parity buffer with data other than primary parity while a second portion of the buffer is still being used to store the primary parity. Therefore, the memory controller smartly re-uses the parity buffer, which makes efficient use of the volatile memory. In one aspect, a memory controller accumulates secondary parity for the user data in a first portion of the parity buffer while a second portion of the parity buffer is still being used to store the primary parity. The memory controller may compute the secondary parity from present content of the first portion of the parity buffer and primary parity presently stored in the second portion of the buffer.

Abstract: Described apparatuses and methods provide error correction code (ECC) circuitry that is shared between two or more memory banks of a memory, such as a low-power dynamic random-access memory (DRAM). A memory device may include one or more dies, and a die can have multiple memory banks. The ECC circuitry can service at least two memory banks by producing ECC values based on respective data stored in the two memory banks. By sharing the ECC circuitry, instead of including a per-bank ECC engine, a total die area allocated to ECC functionality can be reduced. Thus, the ECC circuitry can be elevated from a one-bit ECC algorithm to a multibit ECC algorithm, which may increase data reliability. In some cases, memory architecture may operate in environments in which a masked-write command or an internal read-modify-write operation is precluded, including with shared ECC circuitry.

Abstract: A data storage device includes two or more memory devices and a controller coupled to the two or more memory devices. The controller is configured to program data to one or more memory devices of the two or more memory devices, select one or more of the one or more memory devices to have additional ECC for the data of the one or more memory devices, program the additional ECC to a first memory device. The data is programmed with error correction code (ECC). The first memory device is distinct from the one or more memory devices. The first memory device is disposed in a central module, where the central module includes additional decoding capability. The additional ECC and the corresponding data with ECC are concatenated and decoded for additional error correction capability.

Abstract: The disclosed embodiments are related to storing critical data in a memory device such as Flash memory device. In one embodiment, a method performed by a controller of a memory device comprises receiving a critical operation from a host processor, the critical operation accessing a memory array; retrieving a temperature value of the memory array from a temperature sensor; and conditionally processing the critical operation based on the temperature value.

Abstract: An information handling system includes a processor and a basic input/output system (BIOS). The processor executes an operating system, and detects a corrected error from a memory controller of the information handling system. In response, the processor generates a system management interrupt (SMI). In response to the SMI the BIOS executes a SMI handler. The SMI handler detects a row of the corrected error within a dual inline memory module (DIMM) of the information handling system, and determines whether an entry for the row is located within a hash table. In response to the entry for the row being located within the hash table, the SMI handler increments an error count in a field of the entry for the row. Otherwise, the SMI handler adds a new entry for the row to the hash table, and increments an error count in a field of the new entry for the row.

Abstract: A crossing frames encoding management method, a memory storage apparatus, and a memory control circuit unit are disclosed. The method includes: reading a tag swap information corresponding to a first physical group; encoding a first data; storing a first part of the encoded first data to at least one first physical unit corresponding to a first tag information in the first physical group; and storing a second part of the encoded first data to at least one second physical unit corresponding to a second tag information in the first physical group according to the tag swap information. The first tag information corresponds to a first crossing frames encoding group. The second tag information corresponds to a second crossing frames encoding group. The first crossing frames encoding group is different from the second crossing frames encoding group.

Abstract: Methods, devices, and systems related to memory device on-die ECC data are described. In an example, a scrub operation can be performed on data in order to determine which rows of memory cells in an array include a particular number of errors. The particular number of errors can be a number of errors that exceed a threshold number of errors. An address of the determined rows with the particular number of errors can be stored in memory cells of the array for later access. The address of the determined rows can be accessed to perform a user-initiated repair operation, a self-repair operation, a refresh operation, and/or to alter timing of access of the cells or alter voltage of the cells.

Abstract: A data storage device includes a memory device and a memory controller. The memory controller configures a first memory block which is a TLC memory blocks as a data buffer, and accordingly configures a plurality of second memory blocks which are SLC memory blocks. The memory controller uses the first memory block to receive data and accordingly store same data in the second memory blocks as backup data. When an amount of available memory space of the first memory block is smaller than or equal to a predetermined amount, the memory controller determines whether any error has occurred in the data stored in the first memory block. When there is any error occurred in the data stored in the first memory block, the memory controller configures a third memory block and move the backup data stored in the second memory block to the third memory block.

Abstract: In general, according to an embodiment, a storage device includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of pages, each of the pages including a data area of a first size and a redundant area of a second size smaller than the first size. The controller is configured to receive, from a host, a write command, receive, from the host, transfer data associated with the write command. The transfer data includes write data of the first size appended with a first error detection code for the write data. The controller is further configured to store the write data into the data area of one of the pages and the first error detection code into the redundant area of the one of the pages.

Abstract: Method and apparatus for intelligent caching, protection and transfers of data between a cache and a main memory in a data storage environment, such as but not limited to a solid-state drive (SSD). A main memory (MM) has non-volatile memory (NVM) cells configured for persistent storage of user data. A fast response cache (FRC) has NVM cells configured to provide storage of first data prior to transfer to the MM. A write cache (WC) has NVM cells configured to provide storage of second data prior to transfer to the MM. A controller directs input data to either the FRC or the WC. A first type of error correction encoding (ECC1) is applied to the first data and a different, second type of error correction encoding (ECC2) is applied to the second data. Data may be sent from the FRC to the MM either directly or through the WC.

Abstract: A storage device includes: a memory; and a processor configured to, at the time of writing data into the memory, generate a first check code common to a plurality of types of error correction codes from the data on the basis of a correlation relationship between the plurality of types of error correction codes, add the first check code to the data and write the data into the memory, convert the first check code into a second check code based on any one of the plurality of types of error correction codes at the time of reading the data from the memory, and perform error correction by using the second check code.

Abstract: Systems and methods are provided for adaptive bandwidth (BW) management configuring an element management control unit including a set of distribution/central units (DU/CU) for monitoring power and traffic loads at a plurality of cell sites in a network; communicating with a BW management unit coupled to the element management system to adapt BW for users at cell sites by moving users to a set of smaller bandwidth parts (BWPs) at a cell site in response to a set of conditions of AC power outages and reduced traffic loads detected by the BW management unit, and in response to at least one of the detected conditions, instructing based on data from the DU/CU to the BW management unit to move user traffic to a designated lower BWP of the set of smaller BWPs at the cell site while shutting down other BWPs at the cell site to save the power of an operating cell site.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

Abstract: Systems and methods are provided for concatenated error-correcting coding. An apparatus may include a Low-Density Parity-Check (LDPC) decoder configured to perform an iterative LDPC decoding process on bits of an LDPC codeword, a Bose—Chaudhuri—Hocquenghem (BCH) decoder coupled to the LDPC decoder and a BCH scheduler coupled to the LDPC decoder and the BCH decoder. The LDPC codeword may be generated by LDPC encoding a Bose—Chaudhuri—Hocquenghem (BCH) codeword and the BCH codeword may be generated by BCH encoding a data unit. The BCH scheduler may be configured to determine whether a triggering condition for the BCH decoder is met after each iteration of the iterative LDPC decoding process and activate the BCH decoder to operate on an intermediate decoding result of the LDPC decoder if the triggering condition for the BCH decoder is met.

Abstract: A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.

Abstract: A fault handling apparatus and a fault handling method which perform a built-in self-test (BIST) and a repair on a static random-access memory (SRAM) cell, and the fault handling apparatus and the fault handling method store the fault and repair history information of a previous SRAM test, provide the information to a current test, and reflect both BIST results and the information on the previous test, thereby performing multiple repairs until there is no available spare SRAM.