Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device is arranged into at least a first super device and a second super device, each of the super devices having a plurality of active zones. The controller is configured to determine that each of the super devices includes both cold zones and hot zones, where a cold zone is a zone that is overwritten less than a hot zone. The controller is further configured to move cold zones from one super device to another super device upon determining that the another super device is below a threshold limit, where the threshold limit is a minimum free space to be maintained in a super device. The controller is further configured to move cold zones between super devices, such that the cold zones are concentrated in at least one super device.

Abstract: A storage error identification/reduction system includes a storage error identification/reduction subsystem coupled to a storage subsystem including a block. The storage error identification/reduction subsystem receives first data, and writes the first data to first storage locations in the block while writing storage error identification data to second storage location(s) in the block that each are located adjacent at least one of the first storage locations, with the storage error identification data including predetermined values that are written to predetermined locations included in the second storage location(s) in the block. The storage error identification/reduction subsystem then reads the storage error identification data from the second storage location(s) and, based on the predetermined values and predetermined locations of the storage error identification data, identifies errors resulting from the reading of the storage error identification data.

Abstract: A memory control circuit stores codewords in a memory module configured to limit errors to one wire of a memory interface. A codeword includes a first block with a first data portion and a second block with a second data portion. An error correction code symbol in the second block is used to locate and correct errors in the second block. Some bits of the first block are repurposed as metadata. The remaining bits are used as parity bits for detecting errors in the first block. The second block is merged with the first block before being stored to memory and demerged from the first block in a memory read operation. Demerging causes errors in the first block to create errors in a corresponding location in the second block. The location of errors found in the second block is used to locate and correct parity errors in the first block.

Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for storing and accessing data. A method for storing data includes: dividing, in response to receiving a request for storing data from a client, the data into a plurality of data blocks; storing the plurality of data blocks in a plurality of servers respectively; generating metadata of the data to record corresponding addresses for storing the plurality of data blocks in the plurality of servers; and storing the generated metadata in a metadata repository. The embodiments of the present disclosure can effectively improve data transmission efficiency, data availability, and data security in a cloud storage system.

Abstract: An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive in a storage system, from a host device, mapping information associating a key identifier of a datastore-level key with a corresponding datastore comprising multiple logical storage devices of the storage system, to store the mapping information in a datastore-level key data structure of the storage system, to utilize the key identifier to obtain in the storage system the datastore-level key from a key management server external to the storage system, and responsive to receipt of at least one IO operation from the host device relating to at least one of reading or writing encrypted data of at least one of the logical storage devices of the datastore, to utilize the obtained datastore-level key to access the encrypted data in unencrypted form in the storage system.

Abstract: An electronic control device includes a nonvolatile memory having allocated two storage areas that are exclusively switchable between an active state and an inactive state, the two storage areas being set such that in a state in which a program is written in the storage area in the active state, a program is written for updating to the storage area in the inactive state in response to an instruction from an external device, followed by switching the storage area in the active state to the inactive state and switching the storage area in the inactive state to the active state. In the electronic control device, when the program written in the storage area in the active state differs from the program written in the storage area in the inactive state, the program written in the storage area switched to the active state is copied to the storage area in the inactive state.

Abstract: A method, computer system, and computer program product for data monitoring management are provided. A first invalid zero value candidate from a data stream is received. A memory location for the first invalid zero value candidate is received. At a first time an access connection to the memory location is established. At a second time subsequent to the first time the access connection to the memory location is checked. Based on the checking, a determination is made whether the first invalid zero value candidate contains an invalid zero value.

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

Abstract: A method comprising: receiving a request to read data stored in an array of drives; determining that the data is stored on one or more degraded drives in the array; reconstructing the data from one or more drives in the array other than the degraded drives; providing the reconstructed data in response to the request; and after providing the reconstructed data, writing the reconstructed data to one or more drives in the array other than the degraded drives.

Abstract: An information processing apparatus including a memory and a memory controller writing data to the memory in response to a write for writing the data to the memory, in which the memory executes error correction processing for each data of a predetermined data length, and the memory controller executes, in place of the memory, read modify write processing in a case where a data length of the data related to the write instruction is smaller than the predetermined data length.

Abstract: A method for managing soft errors associated with one or more safety programmable logic controllers (PLCs) is provided. The method includes receiving an expected soft error rate for type(s) of input/output (I/O) modules over time, receiving respective soft error data that was aggregated by the respective safety PLCs based on soft errors detected by I/O modules coupled to the respective safety PLCs. Actual soft error rates are determined per I/O module type based on the received soft error data, and soft error rates are predicted for the safety PLC(s) per I/O module type. The actual and/or predicted soft error rates are compared to the expected soft error rate per I/O module type. The method further includes taking one or more actions in response to a threshold deviation between the actual and/or predicted soft error rates relative to the expected soft error rate for the corresponding I/O module type.

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting (EC) layout constitutes a first layout in the form of a Latin Square.

Abstract: Examples herein relate to a storage system that separately handles portions of a write operation that are aligned and misaligned with respect to retrievable segments from a storage device. For misaligned portions, a buffer can be used to store misaligned retrievable segments and update the segments with content provided with the write operation. Aligned portions of content associated with a write request can be written directly to the storage medium or overwrite corresponding retrievable segments present in the buffer. A table or array can track logical block addresses that correspond to content in the buffer or in the storage. Content in the buffer can be kept in the buffer without being backed-up or persisted to the storage until a triggering event occurs such as power loss or low space in the buffer.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: The operational continuity of a programmable device, and a controller using the same is enhanced.

Abstract: Storage devices are capable of identifying zones for sharing parity blocks across zones. Active zones may be segregated across multiple active zones having similar zone properties, and grouped so that parity buffers can be shared. By identifying zones for optimal parity sharing, storage devices and systems can: (i) maintain independent parity for all zones during initial zone writes (i.e. during an erased state when data is written directly to pages and not to the zones), (ii) track zone write pointers and frequency of writes in the zones, (iii) segregate zones with higher correlation and group them together, (iv) utilize these groupings placed across various channels so that zones with high correlations, comprising of the zones that are written together and at the same rate, share the parity buffers, and (v) load and XOR individual parity buffers for optimal parity sharing across all zones.

Abstract: An application may store data to a dataset comprising a plurality of volumes stored on a plurality of storage systems. The application may request a dataset image of the dataset, the dataset image comprising a volume image of each volume of the dataset. A dataset image manager operates with a plurality of volume image managers in parallel to produce the dataset image, each volume image manager executing on a storage system. The plurality of volume image managers respond by performing requested operations and sending responses to the dataset image manager in parallel. Each volume image manager on a storage system may manage and produce a volume image for each volume of the dataset stored to the storage system. If a volume image for any volume of the dataset fails, or a timeout period expires, a cleanup procedure is performed to delete any successful volume images.

Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits.

Abstract: A processing device in a memory system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device determines a syndrome for the sense word using the plurality of parity check equation results, determines whether the syndrome for the sense word satisfies a codeword criterion, and responsive to the syndrome for the sense word not satisfying the codeword criterion, performs an iterative low density parity check (LDPC) correction process, wherein at least one criterion of the iterative LDPC correction process is adjusted after a threshold number of iterations is performed.

Abstract: A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix; transforming the generating matrix into a systematic form, wherein the transformed generating matrix is composed of a parity matrix and a check matrix; sorting rows of the parity matrix according to row weights; determining a number of rows in the parity matrix to be truncated; generating a truncated parity matrix by keeping the sorted rows of the P matrix that have weights less than or equal to weights of the truncated rows of the P matrix so as to minimize a number of logic gate operations; and forming an error correction circuit with the number of logic gate operations minimized according to the truncated P matrix to correct the error of the codeword.

Abstract: Various embodiments, methods, and systems for erasure coding with overlapped local reconstruction codes, are provided. An erasure coding scheme can be defined based on Overlapped Local Reconstruction Codes (OLRC) that achieve high storage efficiency by providing fault tolerance properties that optimize reconstruction for common cases of failures while maintaining the reconstruction costs for uncommon case of failures. In operation, a data chunk is divided into data fragments. The data fragments correspond to zones. A plurality of parity fragments is computed using the data fragments. A parity fragment is computed using a subset of the data fragments. The plurality of parity fragments are assigned to the zones comprising the data fragments, where the data fragments and the plurality of parity fragments define overlapped local construction codes having a plurality of local groups. An unavailable data fragment is recoverable from at least two local groups from the plurality of local groups.

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

Abstract: A memory device, and an operating method of the memory device and a host device are provided. The method of operating a memory device includes receiving a command for requesting an Eye Open Monitor (EOM) operation performance from a host device, receiving pattern data including data and non-data from the host device, performing the EOM operation which performs an error count to correspond to the data, and does not perform the error count on the non-data, and transmitting an EOM response signal including the error count result to the host device.

Abstract: A memory system having an interconnect configured to receive commands from a system to read data from and/or write data to a memory device. The memory system also has a bridge configured to receive the commands from the interconnect, to manage ECC data and to perform address translation between system addresses and physical memory device addresses by calculating a first ECC memory address for a first ECC data block that is after and adjacent to a first data block having a first data address, calculating a second ECC memory address that is after and adjacent to the first ECC block, and calculating a second data address that is after and adjacent to the second ECC block. The bridge may also check and calculate ECC data for a complete burst of data, and/or cache ECC data for a complete burst of data that includes read and/or write data.

Abstract: Aspects related to a resource-constrained system are described herein that can provide object storage services after a service interruption is resolved, even if all of the transactions that were pending and incomplete prior to the service interruption have not yet been recovered and/or executed. For example, file systems implemented by computing systems of the resource-constrained system may treat each file or directory as a separate object. Thus, a transaction directed to one file may not affect the file's directory or other files in the directory. As a result, the resource-constrained system can achieve read-after-write consistency without first recovering and executing the pending, incomplete transactions. Instead, read-after-write consistency for an object can be achieved simply by completing any pending, incomplete transaction directed to that object.

Abstract: A request to restore a specific backup instance is received. In response to the received request to restore the specific backup instance, a new reference backup instance based on the specific backup instance stored at the storage controlled by the backup system is created at a storage controlled by a backup system. Data associated with the specific backup instance is provided to a recipient system from the storage associated with a backup system. A constructive incremental backup snapshot of the recipient system is performed based on the new reference backup instance.

Abstract: A method for wireless communication performed by a user equipment (UE) includes determining whether a network slice-specific authentication and authorization (NSSAA) procedure is complete. The method also includes transmitting a protocol data unit (PDU) session request to attempt establishing a PDU session without providing an Single-NSSAI when the NSSAA procedure is complete. A method for wireless communications, by an access and mobility management function (AMF) includes determining whether all default network slices for a user equipment (UE) are subject to network slice-specific authentication and authorization (NSSAA). The method also initiates NSSAA on the default network slices when all default network slices are subject to NSSAA.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to, during a writing operation, generate a first error-detecting code from data that is input, perform a predetermined conversion on the data into first conversion data, generate a second error-detecting code from the first conversion data, and store the data, the first error-detecting code, and the second-error detecting code in the non-volatile memory. The controller is configured to during a read operation, read the data, the first error-detecting code, and the second error-detecting code from the non-volatile memory, perform a first error detection on the data using the first error-detecting code, perform the predetermined conversion on the data into second conversion data, perform a second error detection on the second conversion data using the second error-detecting code, and output the second conversion data based on results of the first and second error detections.

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller includes an error correction code (ECC) circuit. The ECC circuit is configured to determine data rows of first write data that are not all zeros and store the determined data rows in buffer rows of a buffer along with corresponding row indexes. The memory controller is configured to write second data based on the buffer to the memory device.

Abstract: A field programmable gate array (FPGA) for improving the reliability of a key configuration bitstream by reusing a buffer memory includes a configuration buffer, a configuration memory and a control circuit. The configuration memory includes N configuration blocks. The FPGA stores a key configuration chain by using the configuration buffer and ensures correct content of the key configuration chain through an error correcting code (ECC) check function of the configuration buffer, so that when the FPGA runs normally, a control circuit reads the key configuration chain in the configuration buffer at an interval of a predetermined time and writes the key configuration chain into a corresponding configuration block to update the key configuration chain, thereby ensuring accuracy of the content of the key configuration chain and improving running reliability of the FPGA.

Abstract: A computer-implemented method, in which an access request in relation to data is received. There is Error Correcting Code (ECC) data relating to the data, and the ECC data is configured to enable correction of multiple-bit errors spanning up to a predetermined number of consecutive bits of the data. The ECC data is configured to enable correction of multiple-bit errors spanning up to a predetermined number of consecutive bits of the data. A first integrity verification verifies the integrity of at least the data. If the first integrity verification procedure fails, an error analysis procedure is performed based on the data and the ECC data. Responsive to generation of corrected data by the error analysis procedure, a second integrity verification verifies the integrity of the corrected data. If the second integrity verification is successful, the access request is allowed using the corrected data.

Abstract: A method for rebuilding data, comprising: obtaining, from a metadata node, a source file data layout for a source file and a target file data layout for a target file, wherein the source file is associated with a degraded mapped RAID group and the target file is associated with a new mapped RAID group; generating, by the client application node, a plurality of input/output (I/O) requests to read a portion of the data associated with the source file using the source file data layout; obtaining, in response to the plurality of I/O requests, the portion of the data associated with the source file; rebuilding a second portion of the data associated with source file using the portion of the data; and initiating, storage of at least the second portion of the data associated with the source file in the storage pool using the target file data layout.

Abstract: A control method for a solid state drive is provided. The solid state drive includes a non-volatile memory with plural blocks. In a step (a1), a block is opened. In a step (a2), a program action is performed to store a valid write data into the open block. Then, a step (a3) is performed to judge whether an amount of the valid write data in the open block reaches a predetermined capacity. In a step (a4), if the amount of the valid write data in the open block does not reach the predetermined capacity, the step (a2) is performed again. In a step (a5), if the amount of the valid write data in the open block reaches the predetermined capacity, the open block is closed and the step (a1) is performed again. The predetermined capacity is lower than a capacity of one block.

Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for performing data transfers with improved error encoding. The methods include receiving a request for data transfer from a source medium in the data storage system to a destination medium in the data storage system, wherein the data storage system comprises a computer cluster and a storage cluster; determining whether the source medium and the destination medium are within the storage cluster; based on the determination of whether the source medium and the destination medium are within the storage cluster, transferring the data from the source medium to the destination medium, wherein: the data is transferred without performing error correcting code check when the data is transferred within the storage cluster, and the data is transferred with an error correcting code check when the data is transferred between the computer cluster and the storage cluster.

Abstract: A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

Abstract: A flash memory method includes: classifying data into a plurality of groups of data; respectively executing error code encoding to generate first corresponding parity check code to store the groups of data and first corresponding parity check code into flash memory module as first blocks; reading out the groups of data from first blocks; executing error correction and de-randomize operation upon read out data to generate de-randomized data; executing randomize operation upon de-randomized data according to a set of seeds to generate randomized data; performing error code encoding upon randomized data to generate second corresponding parity check code; and, storing randomized data and second corresponding parity check code into flash memory module as second block; a cell of first block is used for storing data of first bit number which is different from second bit number corresponding to a cell of second block.

Abstract: Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.

Abstract: A control apparatus where control programs and information programs coexist is allowed to change programs flexibly. The control programs and information programs are installed in the control apparatus, which is provided with a shared area. The shared area is an area that at least one control program and at least one information program can access. Shared information is stored in the shared area. The shared information includes at least one of information related to an I/O port accessed by the control programs, and information related to the control program. Each control program is a program that performs scan operation of outputting control information on the relevant control object apparatus coupled to the I/O port accessed for controlling a control object apparatus with respect to the control program, to this I/O port. Each information program is a program that performs information processing that does not include the scan operation.

Abstract: Designs of controllers for flash memory array are described. A controller is designed to form data packs of a predefined size with compressed data segments in different sizes. The data packs are encoded with ECC in two dimensions. When the data packs are read out, the ECC is applied in two dimensions to detect and correct errors that can be corrected by the ECC.

Abstract: In one embodiment, a system includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code comprises encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes.

Abstract: Systems and methods for performing in-storage logic operations using one or more memory cell transistors and a programmable sense amplifier are described. The logic operations may comprise basic Boolean logic operations (e.g., OR and AND operations) or secondary Boolean logic operations (e.g., XOR and IMP operations). The one or more memory cell transistors may be used for storing user data during a first time period and then used for performing a logic operation during a second time period subsequent to the first time period. During the logic operation, a first memory cell transistor of the one or more memory cell transistors may be programmed with a threshold voltage that corresponds with a first input operand value and then a gate voltage bias may be applied to the first memory cell transistor during the logic operation that corresponds with a second input operand value.

Abstract: Methods and apparatus for storing parity bits in an available over provisioning (OP) space to recover data lost from an entire memory block. For example, a data storage device may receive data from a host device, write the data to a block, and generate a corresponding block parity. The device may then determine a bit error rate (BER) of the block and an average programming duration to write the data written to the block, calculate a probability of the block becoming defective based on the BER and the average programming duration, and comparing the probability of the block to a set of probabilities respectively corresponding to a set of worst-performing blocks in a NVM. Thereafter, the device may write the block parity to an available over provisioning (OP) space in the NVM responsive to the probability of the block being greater than any probability in the set of probabilities.

Abstract: Data processing techniques comprise, in response to determining that a storage unit storing first data blocks is damaged, determining storage units associated with the storage unit, and obtaining second data blocks from the storage units, where the second data blocks and the first data blocks are generated by applying to data an error correction code in a first format. The method further comprises recovering the first data blocks based on the second data blocks. In addition, the method comprises generating error correction blocks by applying an error correction code in a second format to the recovered first data blocks, where the second format is different from the first format. The above techniques can reduce input/output operations and shortens the recovery time of data blocks, and further can reduce the risk of data loss even in an extremely bad situation.

Abstract: An electronic device includes a replica delay circuit configured to generate a delayed error check signal by delaying a first error check signal including error information of first data stored in a first memory region. The electronic device also includes an error sum signal generation circuit configured to generate an error sum signal by summing a second error check signal including error information of second data stored in a second memory region and the delayed error check signal.

Abstract: A method of erasing data from a data storage apparatus comprising a memory, the method comprises writing a known data pattern to a plurality of known memory locations of the data storage apparatus, causing the data storage apparatus to perform a data erasure procedure, reading data stored at the known memory locations after completion of the data erasure procedure, comparing the read data and the data of the known data pattern, and determining a verification result based at least in part on the result of the comparison between the read data and the data of the known data pattern.

Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.

Abstract: Host data to be written to a storage area including a set of multiple planes of a memory device is received. A first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data is executed. The set of multi-plane parity data is stored in in a cache memory of a controller of a memory sub-system. A second parity generation operation based on the set of the multiple planes of the host data to generate a set of multi-page parity data is executed. The set of multi-page parity data in the cache memory of the controller of the memory sub-system is stored. A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.

Abstract: Methods, systems, and devices for memory device with enhanced data reliability capabilities are described. For a write operation, a memory device may receive a write command from a host device indicating a first set of data. The memory device may determine to operate in first mode of operation associated with a reliability above a threshold and generate a second set of data to store with the first set of data based on operating in the first mode of operation. For a read operation, the memory device may identify that a read command received from a host device is associated with the first mode of operation. Based on operating in the first mode of operation, the memory device may select one or more reference thresholds (e.g., a subset of reference thresholds) to retrieve the first set of data and transmit the first set of data to the host device.