Abstract: A method for combining a refresh operation with a parity validation for a DRAM-based content addressable memory (CAM) is disclosed. In an exemplary embodiment of the invention, the method includes implementing the memory refresh operation and examining a word included within the CAM. A determination is made as to whether data contained within the word constitutes valid data. If the data contained within the word does not constitute valid data, then the parity validation is bypassed. However, if the data contained within the word does constitute valid data, then the parity validation is implemented. The parity validation further includes reading the data contained within the word, generating a parity bit from the data contained within the word, and comparing the generated parity bit with a previously stored parity bit. If the parity validation is implemented and if the generated parity bit does not match the previously stored parity bit, then the data contained within the word is invalidated.

Abstract: According to one embodiment, a method is disclosed. The method includes interleaving a first error correction code with a second error correction code to generate a third error correction code that provides chip-kill capabilities for a memory system.

Abstract: System and method for rapidly calculating CRC values for messages including encoded bits is described. Tabularized CRC values are used in combination with a logical grid to quickly determine an appropriate CRC value of a message. This determination can take into account encoded inversion bits in the message. A collection of pre-calculated CRC values are arranged in a single-column table and then implemented with selected bits of a message by superimposing the bits in each CRC value onto a logical grid. Vertical lines of the grid are associated with 30 exclusive OR (XOR) gates and horizontal lines are associated with bits in an 88-bit message (or the 30 bits of a CRC value or with 8 bits of a sequence number). Through this grid, the inputs to the XOR gates are determined, thereby facilitating rapid calculations of CRC values due to the high processing speeds possible in XOR gates.

Abstract: A method for recovering user data from a host device stored on a data storage medium where a said data may become corrupted during a read operation comprises: performing a read operation to read at least one encoded data fragment of said plurality of encoded data fragments from said data storage medium; storing status data indicating whether said at least one data fragment was correctly read; writing said read at least one data fragment to a buffer memory; attempting to decode said at least one encoded data fragment in said buffer memory wherein if said attempted decoding is unsuccessful then said method further comprises the steps of: re-reading incorrectly read encoded data fragments from said data storage medium; and attempting to decode said encoded data fragments located in said buffer memory.

Abstract: A disc storage apparatus includes at least one disc having at least one recording surface, at least one head associated with the at least one recording surface for recording data on the at least one recording surface, a decoder circuit which receives coded data from the at least one head, decodes the coded data to parallel data, and outputs the parallel data, and a disc control unit which receives the parallel data from the decoder circuit and outputs the parallel data outside the disc storage apparatus. The apparatus may further include a host interface control unit coupled to a host computer and the disc control unit, wherein the disc control unit outputs the parallel data to the host computer via the host interface control unit, and a buffer memory which stores the parallel data to be outputted to the host computer.

Abstract: A programmable smart membrane and methods therefor. The smart membrane conducts an overall function on at least one of a sorting function, a filtering function and an absorbing function of at least one object having an attribute. The smart membrane includes a plurality of module units disposed adjacent each other. Each of the plurality of module units obtains information from an environment around each of the plurality of module units. The plurality of module units also each perform a function based on at least a first control method that determines the function based on the information for each of the plurality of module units. Wherein the plurality of module units individually perform function to collectively perform the overall function of the membrane based on the attribute of the object.

Abstract: Apparatus and methods for storing predefined information with error correcting code (ECC) in a direct access storage device are provided. Predetermined information is identified and loaded to an ECC generator for customer data to be read and written. The identified predetermined information includes an address for customer data to be read and written. The customer data is written and loaded in parallel to the ECC generator. Then the generated ECC that reflects the pre-loaded predetermined information is written at the end of the written customer data. The customer data and ECC is read and loaded in parallel to the ECC generator. Errors in the predetermined information that is not written to the disk surface, can be detected from the read ECC.

Abstract: An apparatus and method in which ECC bus protection capability can be generated on a memory card in conjunction with a computer system with a built-in ECC capability to reduce data transmission errors. Data generated by the system is transmitted to the card and stored in DRAMs. On a read cycle, the card generates a set of checkbits which are sent to the system on a checkbit bus. The system generates a set of checkbits from the data read from the memory card and compares these checkbits with those received from the memory card. A mismatch indicates transmission error on the bus(s) during a read cycle. Any correctable error is corrected. Data is invalidated if an uncorrectable error is detected. In another embodiment checkbits generated by the system during a write cycle are transmitted to the card an checkbits are generated by the card. These two sets of checkbits are compared and if there is a mismatch data is either flagged as bad or corrected.

Abstract: A computer system includes a processor bus having processor data and processor check bits for performing error detection and correction of the processor data. A CPU is coupled to the processor bus. A memory sub-system is coupled to the processor bus and includes memory check bits, memory address bits, and memory data bits, and an error detection and correction device for detecting an error in the memory address bits using the memory check bits and for detecting an error in the memory data bits using the memory check bits. The CPU can include a processor from the Pentium.RTM. Pro family of processors. The error detection and correction device generates a syndrome table which includes a plurality of entries mapped to correctable or uncorrectable errors, in which a detected multiple-bit error in the memory data bits is mapped to an uncorrectable error entry and a detected error in the memory address bits is mapped to an uncorrectable error entry.

Abstract: In the coding and decoding of Reed-Solomon codes formed of symbols larger than information symbols, redundant circuitry is eliminated, error detection and correction are preformed using a simple construction, and the reliability of error detection and correction is improved by processing only data of the same size as the information symbols. Two bits of dummy data which are surplus bits in 10 bits of one symbol of information are supplied from a dummy data input circuit to 8 bit input data. At the same time, syndrome data is generated form the surplus parts of check symbols by a syndrome data correction circuit. A part of the 10 bit data is selected by a selector, and supplied to a Galois field summation circuit. The output of the Galois field summation circuit is output to a register, and the output of this register is either selected without modification or via a Galois field coefficient multiplying circuit by a selector, and supplied to the Galois field summation circuit.