Abstract: Techniques for operating a DIMM apparatus. The apparatus comprises a plurality of DRAM devices numbered from 0 through N?1, where N is an integer greater than seven (7), each of the DRAM devices is configured in a substrate module; a buffer integrated circuit device comprising a plurality of data buffers (DB) numbered from 0 through N?1, where N is an integer greater than seven (7), each of the data buffers corresponds to one of the DRAM devices; and a plurality of error correcting modules (“ECMs”) associated with the plurality of DRAM devices.

Abstract: A semiconductor device includes a memory region configured to include a plurality of banks and a redundancy region within each of the banks and an error check and correction (ECC) region configured to detect an address of the memory region at which an error has occurred and correct a defect of the memory region by replacing the address at which the error has occurred with a redundancy line of the redundancy region based on address information.

Abstract: A method of correcting stored data includes reading data stored in a portion of a nonvolatile memory. The method includes, for each particular bit position of the read data, updating a count of data error instances associated with the particular bit position in response to detecting that the read data differs from a corresponding reference value of the particular bit position. The reading of the first portion and the updating of the counts of data error instances are performed for a particular number of repetitions. The method includes identifying each bit position having an associated count of data error instances equal to the particular number of repetitions as a recurring error bit position.

Abstract: A memory having variable size blocks of failed memory addresses is connected to a TCAM storing data values of ranges of addresses in the memory. The ranges of addresses correspond to virtual addresses that, in combination with an offset, point away from failed memory addresses. A reduction circuit connected to the TCAM produces an output for each programmed range of addresses based on a virtual address. A priority encoder, connected to the reduction circuit, selects a first range from the reduction circuit and passes the first range to a random-access memory (RAM). Responsive to the virtual address bring an address in one of the ranges of addresses, the priority encoder passes the first range containing the virtual address to the RAM, which passes a corresponding offset value to the Adder based on the first range. The Adder calculates a physical memory address directing the virtual address to a functional memory location.

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for recovering data from a solid state memory.

Abstract: In a data processing system having a plurality of error coding function circuitries, a method includes receiving an address which indicates a first storage location for storing a first data value; using a first portion of the address to select one of the plurality of error coding function circuitries as a selected error coding function circuitry; and using the selected error coding function circuitry to generate a first checkbit value, wherein the selected error coding function circuitry uses the first data value to generate the first checkbit value. When the first portion of the address has a first value, a first one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry. When the first portion of the address has a second value, a second one of the plurality of error coding function circuitries is selected as the selected error coding function circuitry.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: A method for data storage includes storing data, which is encoded with an Error Correction Code (ECC), in a group of analog memory cells by writing respective first storage values to the memory cells in the group. After storing the data, respective second storage values are read from the memory cells in the group, and the read second storage values are processed so as to decode the ECC. Responsively to a failure in decoding the ECC, one or more of the second storage values that potentially caused the failure are identified as suspect storage values. Respective third storage values are re-read from a subset of the memory cells that includes the memory cells holding the suspect storage values. The ECC is re-decoded using the third storage values so as to reconstruct the stored data.

Abstract: An apparatus comprising a memory and a controller. The memory may be configured to process a plurality of read/write operations. The memory may comprise a plurality of memory modules each having a size less than a total size of the memory. The controller may be configured to write user data using a redundancy scheme. Information about the redundancy is (i) stored in a location separate from the data and (ii) used to recover potentially corrupted user data.

Abstract: An object of the present invention is to realize a highly reliable long-life information processor capable of high-speed operation and easy to handle. The processor includes a semiconductor device comprising a nonvolatile memory device including a plurality of overwritable memory cells, and a control circuit device for controlling access to the nonvolatile memory device. The control circuit device sets assignments of second addresses to the nonvolatile memory device independently of first addresses externally supplied, such that the physical disposition of part of the memory cells used for writing of first data to be written externally supplied is one of the first to (N+1)th of every (N+1) memory cells (N: a natural number) at least in one direction.

Abstract: Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

Abstract: A storage system has a RAID group configured by storage media, a system controller with a processor, a buffer memory coupled to storage devices and the processor by a communication network, and a cache memory coupled to the processor and the buffer memory by the network. A processor that stores first data, which is related to a write request from a host computer, in a cache memory, specifies a first storage device for storing data before update, which is data obtained before updating the first data, and transfers the first data to the specified first storage device. A first device controller transmits the first data and second data based on the data before update, from the first storage device to the system controller. The processor stores the second data in the buffer memory, specifies a second storage device, and transfers the stored second data to the specified second storage device.

Abstract: A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.

Abstract: According to one embodiment, a memory controller is provided, the memory controller including an encoding unit that performs 1st stage error-correction coding on 1st data, performs 2nd stage error-correction coding on 2nd data, and performs 3rd stage error-correction coding on 3rd data, wherein the 1st data includes 4 sub-unit data included in 1st unit data, the 2nd data includes 4 sub-unit data included in the 1st and 2nd unit data, and the 3rd data includes 4 sub-unit data included in the 1st to 4th unit data.

Abstract: A method for providing data protection for data stored within a Random Access Memory element. The method comprises receiving data to be written to memory, dividing the received data into a plurality of data sections, applying error correction codes to the data sections to form codeword sections, interleaving the codeword sections to form an interleaved data codeword, and writing within a single clock cycle the interleaved data codeword to memory.

Abstract: At least one implementation herein enables interleaver and deinterleaver buffer modification during Showtime. That is, at least one implementation herein enables a multicarrier controller apparatus to reallocate interleaver and deinterleaver buffer memory to accommodate data rate changes in the upstream and downstream communication channels.

Abstract: A memory system includes a flash subsystem for storing data identified by page numbers. The memory system further includes a central processing unit (CPU), and a flash controller coupled to the CPU, the CPU being operable to pair a lower with an upper page. Further included in the memory system is a buffer including a page of data to be programmed in a block of the flash subsystem, wherein split segments of pages are formed and concatenated with split error correcting code (ECC), the ECC having a code rate associated therewith.

Abstract: An embodiment relates to a method for data processing that includes reading data, the data comprising overhead information and payload information, and determining a state of each portion of the data, wherein the state is one of a first binary state, a second binary state, and an undefined state. The method also includes decoding at least one portion of data that has an undefined state based on its location and based on the overhead information.

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract: A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.

Abstract: A memory management method and a memory controller and a memory storage apparatus using the same are provided. The method includes applying different detection biases to read data stored in physical pages of a rewritable non-volatile memory module and calculating the number of error bits according the read data. The method further includes estimating a value of a wearing degree of each physical page according to the calculated number of error bits and operating the rewritable non-volatile memory module according to the value of the wearing degree of each physical page. Accordingly, the method can effectively identify the wearing degree of the rewritable non-volatile memory module and operate the rewritable non-volatile memory module by applying a corresponding management mechanism, so as to prevent data errors.

Abstract: Methods and apparatus are provided for reading and writing data in q-level cells of solid-state memory, where q>2. Input data is encoded into codewords having N qary symbols, wherein the symbols of each codeword satisfy a single-parity-check condition. Each symbol is written in a respective cell of the solid state memory by setting the cell to a level dependent on the qary value of the symbol. Memory cells are read to obtain read signals corresponding to respective codewords. The codewords corresponding to respective read signals are detected by relating the read signals to a predetermined set of N-symbol vectors of one of which each possible codeword is a permutation.

Abstract: An apparatus includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of R-blocks. The controller is coupled to the non-volatile memory. The controller is configured to (i) write data using the R-blocks as a unit of allocation and (ii) perform recycling operations selectively on either an entire one of the R-blocks or a portion less than all of one of the R-blocks.

Abstract: Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be implemented using relatively inexpensive MLC Flash for an enterprise storage application.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: A storage module may include a NAND-type flash memory array and one or more controllers configured to increase gate bias voltage levels applied to gates in the memory array to overcome possible gate shorts and recover data identified as being uncorrectable. The increased gate bias voltages may be applied to gates of a single type of transistor or to different types of transistors in the memory array, including drain select transistors, source select transistors, or floating gate transistors.

Abstract: Provided is a flash memory controller and a method for transmitting data between flash memories. The method includes: implementing parallel processing in a manner of separating data transmission from error detection processing, and performing delayed acknowledgment on correctness of data transmitted to a target flash memory. In addition, an error detection unit performs correction processing on data in which an error occurs, and performs an update with correct data after correction and overwrites erroneous data in a buffer of the flash memory.

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A multiplexer is controlled to couple a DRAM (Dynamic Random Access Memory) to a buffer. A DMA (Direct Memory Access) controller is directed to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to a RAID-encoding (Redundant Array of Independent Disk-encoding) unit in multiple batches. After a first condition is satisfied, the processing unit controls the multiplexer to couple the RAID-encoding unit to the buffer and directs the RAID-encoding unit to output a vertical ECC (Error Correction Code) to the buffer through the multiplexer in at least one batch.

Abstract: A memory controller includes an encoder, a modulator, and a demodulator. A nonvolatile memory includes memory cells, each programmable to one of three or more levels. According to first encoded data, the modulator programs a first subset of the memory cells to a first of the levels and a second subset of the memory cells to a second of the levels. Measurable values of the first subset are characterized by a first probability density function having a first width. Measurable values of the second subset are characterized by a second probability density function having a second width. The first width is greater than the second width. The encoder generates the first encoded data based on input data such that the first subset is smaller than the second subset. The demodulator is configured to output second encoded data in response to measurable values of the memory cells.

Abstract: An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. After all messages within a RAID (Redundant Array of Independent Disk) group are programmed, it is determined whether a vertical ECC (Error Correction Code) within the RAID group has been generated. The processing unit directs a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical ECC to be programmed to the storage unit.

Abstract: A nonvolatile memory device includes a plurality of memory regions, and a memory controller that controls data transfer operations to and from the memory regions. When generating an error checking and correcting code (ECC) for data including a plurality of data units and writing the data and the ECC in at least one of a plurality of memory regions, the memory controller acquires ECC information and adjusts a size of the data units and a size of the ECC on the basis of the acquired ECC information, to form a plurality of data frames each including the data unit and the ECC for the data unit.

Abstract: Data that are stored in cells of a multi-bit-per cell memory, according to a systematic or non-systematic ECC, are read and corrected (systematic ECC) or recovered (non-systematic ECC) in accordance with estimated probabilities that one or more of the read bits are erroneous. In one method of the present invention, the estimates are a priori. In another method of the present invention, the estimates are based only on aspects of the read bits that include significances or bit pages of the read bits. In a third method of the present invention, the estimates are based only on values of the read bits. Not all the estimates are equal.

Abstract: A solid-state storage retention monitor determines whether user data in a solid-state device is in need of a scrubbing operation. One or more reference blocks may be programmed with a known data pattern, wherein the reference block(s) experiences substantially similar P/E cycling, storage temperature, storage time, and other conditions as the user blocks. The reference blocks may therefore effectively represent data retention properties of the user blocks and provide information regarding whether/when a data refreshing operation is needed.

Abstract: A data protecting method, a memory controller, and a memory storage device are provided. The data protecting method includes following steps. A first flush command and a first write command instructing to write a first data are received from a host system. A first error correcting code and a corresponding second error correcting code having different protection capabilities are generated according to the first data. A second write command instructing to write a second data is received. After the first write command is received, a second flush command is received from the host system, and the second error correcting code corresponding to the first data is then written into a rewritable non-volatile memory module. A second error correcting code corresponding to the second data is not generated or is generated but not written into the rewritable non-volatile memory module. Thereby, data from the host system is protected.

Abstract: A method includes a DSN access token module retrieving one or more sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with the computing device and/or the DSN access token module decoding the one or more sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function. The method continues with the computing device and/or the DSN access token module generating a plurality of sets of data access requests in accordance with the DS error coding function. The method continues with the computing device sending the plurality of sets of data access requests to the DSN memory.

Abstract: According to an embodiment, a memory system includes multiple nonvolatile memories to/from each of which data can be written/read independently of one another; and a controller configured to control writing of data to and reading of data from the nonvolatile memories. Each of the nonvolatile memories includes a data storage including a normal data storage area for storing the data and a redundant data storage area for writing the data avoiding defect positions in the normal data storage area; and a defect information storage configured to store defect information indicating information on a defect of the data storage included in another nonvolatile memory different from the present nonvolatile memory.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time.

Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device in response to a request from an external device, wherein the controller comprises a victim block setup unit suitable for setting a victim block for performing a merge operation, based on an error count, which is detected when a read operation of the nonvolatile memory device is performed, and for storing information of the victim block.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: A semiconductor device includes first and second memory cell arrays, each including a plurality of memory cells, each of which is connected between first and second terminals and is configured to be written to a first resistance state by applying a first current in a first direction between the first and second terminals and be written to a second resistance state by applying a second current in a second direction opposite to the first direction between the first and second terminals. The semiconductor device further includes an error-correction circuit and a control circuit. Additional apparatus and methods are disclosed.

Abstract: Some embodiments include apparatuses and methods having first memory cells, a first access line configured to access the first memory cells, second memory cells, and a second access line configured to access the second memory cells. One of such apparatuses can include a controller configured to cause data to be stored in a memory portion of the first memory cells, to cause a first portion of an error correction code associated with the data to be stored in another memory portion of the first memory cells, and to cause a second portion of the error correction code to be stored in the second memory cells. Other embodiments including additional apparatuses and methods are described.

Abstract: In some embodiments, a non-volatile memory device comprises an error correction component to re-program at least a portion of a non-volatile memory array at least in part in response to detection of one or more heat events and detection of one or more errors in contents of the at least a portion of the non-volatile memory array.

Abstract: Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.

Abstract: A custom decoding algorithm is introduced, in connection with a corresponding decoding structure, to resolve many complexity and large memory requirements of known decoders. A system. A variable node forms a confidence vector of four components, one component for each state of a memory cell, and passes the current primary component (e.g., the largest) to one or more check nodes. The check nodes calculate a temporary component and corresponding index based on all components received from the variable nodes, which they pass back to the respective variable nodes. The variable node updates the confidence vector based on the temporary nodes received from respective check nodes, and determines the correct state for corresponding memory cell based on which component in the confidence vector is currently the primary component.

Abstract: A method of writing data includes receiving a data page to be stored in a data storage device and initiating an encode operation to encode the data page. The encode operation generates first encoded data and a first portion of the first encoded data is stored to the first physical page of the data storage device. The method includes initiating storage of a second portion of the first encoded data to a second physical page of the data storage device. The method also includes initiating a decode operation to recover the data page. The decode operation uses a representation of the first portion of the first encoded data that is read from the first physical page without using any data from the second physical page.

Abstract: RAID storage systems and methods adapted to enable the use of NAND flash-based solid-state drives. The RAID storage system includes an array of solid-state drives and a controller operating to combine the solid-state drives into a logical unit. The controller utilizes data striping to form data stripe sets comprising data (stripe) blocks that are written to individual drives of the array, utilizes distributed parity to write parity data of the data stripe sets to individual drives of the array, and writes the data blocks and the parity data to different individual drives of the array. The RAID storage system detects the number of data blocks of at least one of the data stripe sets and then, depending on the number of data blocks detected, may invert bit values of the parity data or add a dummy data value of “1” to the parity value.

Abstract: Address error detection including a method that receives write data and a write address, the write address corresponding to a location in a memory. Error correction code (ECC) bits are generated based on the received write data. The write data is transformed at a computer based on the write address and the write data, to produce transformed write data. The transforming is configured to cause an ECC to detect an address error during a read operation to the write address in response to a mismatch between either the write address or the read address and data read from the location. The transformed write data and the ECC bits are written to the location in memory.

Abstract: A method for data storage includes assigning in a memory that includes one or more storage devices a first storage area for storage of user data, and a second storage area, which is separate from the first storage area, for storage of redundancy information related to the user data. Input data is processed to produce redundancy data, and the input data is stored in the first storage area using at least one first write command. The redundancy data is stored in the second storage area using at least one second write command, separate from the first write command.

Abstract: Techniques and mechanisms for handling data faults in a memory system which includes multiple integrated circuit (IC) dies, each die including a respective one of multiple memory arrays. In an embodiment, control logic monitors for a die failure of the multiple dies, and further monitors for a request to perform error correction for the multiple memory arrays. Each of the multiple memory arrays may store a respective vertical error correction code specific to data of that memory array. Another IC die may store a Bose, Ray-Chaudhuri, Hocquenghem (BCH) code of a horizontal codeword which spans the multiple memory arrays. In another embodiment, the BCH code is available to decode logic for data recovery operations in response to a die failure, where the BCH code is further available to the decode logic for error correction operations when all of the memory arrays are operative.

Abstract: A storage device is provided which includes a nonvolatile memory device and a controller configured to write meta information, indicating that a transfer of unit data is completed, in a buffer memory when the unit data is transferred to the buffer memory from the nonvolatile memory device.