Abstract: A method for transmitting a downlink message on a downlink between an access network and a plurality of terminals. The downlink message includes main data to be transmitted to a receiving terminal. Error detection data is generated from the main data. Main data and/or error-detection data are modified on the basis of an identifier of the receiving terminal, using a predefined reversible modification function. The modification is performed at a constant spectral width and for a constant duration with respect to the aforementioned main data and/or error-detection data. A downlink message including the main data and the error-detection data obtained after modification are transmitted. Also, a method for receiving the downlink messages.

Abstract: Systems and method for accessing data in a storage network include a processing module receives redundant array of independent disks (RAID) data to store determining which memories to utilize (e.g., a RAID memory, local and/or remote dispersed storage network (DSN) memory) based on one or more of the metadata, the RAID data, a vault lookup, a command, a message, a performance indicator, a predetermination, local DSN memory capabilities, remote DSN memory capabilities, RAID memory capabilities, and a comparison of requirements to capabilities of the RAID memory and local and/or DSN memory. The processing module saves the determination choice in a memory indicator that is stored in one or more of the RAID memory, the local DSN memory, the remote DSN memory, and a DSN user vault.

Abstract: An error correction code (ECC) decoder includes a finite state machine (FSM) controller and a shared logic circuit. The FSM controller generates a first control signal and a second control signal each corresponding to a certain state. The shared logic circuit includes a plurality of shared Galois field (GF) multipliers, a plurality of shared XOR arithmetic elements, and a plurality of shared multiplexers (MUXs), which are used for an operation selected between a syndrome operation, an error location polynomial operation, an error location operation and an error correction operation, in response to the first and second control signals.

Abstract: In a general aspect, a cryptography process performs modular operations, where the modulus is a non-Mersenne prime. In some aspects, an integer is obtained during execution of a cryptography protocol defined by a cryptosystem. A prime modulus is defined by the cryptosystem in terms of a set of constants. The set of constants includes at least a first constant and a second, distinct constant. A set of block coefficients is computed to represent the integer in a block form. The plurality of block coefficients includes a first block coefficient obtained by a first modular reduction modulo the first constant, and a second block coefficient obtained by a second modular reduction modulo the second constant. A reduced representation of the integer is computed based on the plurality of block coefficients, such that the reduced representation is less than the prime modulus.

Abstract: An integrated circuit may include a Reed-Solomon decoder that receives a transmitted code word and an associated bit mask and that generates a corresponding corrected message. The bit mask indicates an erasure pattern for the received code word. The Reed-Solomon decoder may include a syndrome generator, a multiplication circuit, a read-only memory (ROM) circuit, an address compressor, and an aggregation circuit. The syndrome generator may receive the transmitted code word and generate a corresponding syndrome. The address compressor may receive the bit mask and generate a corresponding unique address for accessing the ROM circuit. The ROM circuit may then output an inverse parity matrix based on the unique address. The multiplication circuit may multiply the syndrome by the retrieved inverse parity matrix to output corrected symbols. The aggregation circuit may then path the received code word with the corrected symbols to obtain the corrected message.

Abstract: Systems and methods are disclosed for a seeding mechanism for error detection codes. An error detection code may be generated using specifically modified seed input and stored to data sectors not containing valid data. A data storage device may determine if read attempts are directed to an invalid sector by analysis of the stored error detection code. In some embodiments, an apparatus may determine a first error detection code stored to a target data storage sector does not match a second error detection code calculated for the target data storage sector, compare the first error detection code to a modified error code value to determine whether the target data storage sector contains valid data, and return an indication that the target data storage sector does not contain valid data when the error detection code matches the modified error code value.

Abstract: Techniques to reduce the transmission overheads in a communication system are disclosed. In an embodiment, a method described herein relates to the elimination of redundant padding to realize an integer number of FEC code-words during the FEC-encoding process of transmission as well as the reduction/elimination of redundant padding to realize an integer number of transmission symbols during the subcarrier modulation mapping process of transmitting OFDM/ACMT/DMT symbols. The techniques are described in the context of a communication system based on the MoCA specification. Furthermore, techniques for channel-profiling, channel-estimation and bandwidth request/grant signaling that facilitate the realization of the method of reduction of transmission overheads in a MoCA system are also described.

Abstract: A memory refreshing circuit implemented on an integrated circuit comprising a memory circuit that stores original data and an algorithmic data generation circuit that generates write addresses and correct data such that the correct data is stored in the memory circuit at locations that are indicated by the write addresses to correct errors in the original data by overwriting the original data with the correct data during a random access mode of operation of the memory circuit.

Abstract: Apparatuses for error detection and correction for a semiconductor device are described. An example apparatus includes: at least one memory cell array including a plurality of memory cells; and a control circuit that receives read data from the plurality of memory cells, compares the read data with reference data, and further provides an error signal. The control circuit further provides the error signal when a number of bit errors detected is greater than or equal to a predetermined number, and suppresses providing the error signal when the number of bit errors detected is less than the predetermined number.

Abstract: An arrangement for decoding a data word using a Reed-Muller code, has: (1) N input terminals, (2) a first level of E>>D summing modules, each summing module being linked with F different input terminals and each input terminal being linked with E summing modules, (3) a first level of E decision modules, each of the D inputs of each decision module being linked respectively with an output from D different summing modules, (4) a second level of H summing modules, (5) a second level of G decision modules, (6) a third level of G summing modules, and (7) G output terminals. N signifies the code length and D signifies the minimum spacing of the code, E is equal to D-2, F is equal to N/D, G is the number of symbols of the data word that need to be corrected and is a natural number between 1 and E<<D.

Abstract: In a WLAN, a device generates a short training field and a long training field following the short training field. The device generates a first signal field following the long training field, and the first signal field includes a mode field for indicating a transmission mode of a frame to be transmitted and a check bit for protecting at least the mode field. The device transmits the frame including the short training field, the long training field, and the first signal field.

Abstract: A wireless interface device for at least one of wireless transmission from an electric analog audio device or wireless reception at an electric analog audio device of an audio signal, comprises an audio connector jack plug or jack socket in communication with a system that is at least one of a wireless internet system or a WLAN-enabled system and connectable to at least one of an audio connector jack plug of the electric analog audio device, or an audio connector jack socket of the electric analog audio device.

Abstract: An embodiment takes the form of a method carried out by a communication device. A binary data sequence is obtained at a communication device for transmission via a Bluetooth data link configured according to an audio-codec-based Bluetooth profile, wherein an audio codec is configured to receive a multi-bit data byte and output a single bit indicating whether the received multi-bit data byte is larger or smaller than a prior output reference byte, a multi-bit data byte sequence is generated based on the binary data sequence, the multi-bit data byte sequence is provided to the audio codec to induce the codec to generate a one-bit per-sample binary sequence representative of the binary data sequence, and, the generated one-bit per-sample binary sequence is transmitted via the Bluetooth data link.

Abstract: A computing device for correcting data errors may receive data stored by a memory device; calculate a syndrome associated with the data; initiate a calculation of error correction information for the data based on the syndrome; search for the error correction information in a cache based on the syndrome; discontinue the calculation of the error correction information when the error correction information is found in the cache before the error correction information is calculated; and correct an error associated with the data using the error correction information from the cache.

Abstract: According to various aspects of the present disclosure, medium access control (MAC) sublayer logic of a device or a system may generate and implement a preamble structure of a data unit including a signal field which includes a four-bit cyclic redundancy check sequence providing a Hamming distance of two. The signal field portion of the preamble structure may include information related to a plurality of physical layer parameters used for wireless communication of the data unit. The preamble structure may be stored on a machine-accessible medium. The preamble may be generated by a data unit builder of the device, which may further receive a frame including a data payload, and encapsulate the frame with the preamble portion to generate the data unit. A transmitter coupled with the data unit builder may then wirelessly transmit the data unit using an antenna array.

Abstract: An encoder generates a compressed data sequence from an original data sequence using many-to-one mapping independently of a source model associated with the original data sequence and without extracting the source model. A decoder uses both the source model associated with the original data sequence and the mapping applied during compression that is devoid of, in substance, the source model, to regenerate, at least in part, the original uncompressed data sequence from the compressed data sequence that does not include a significant portion of the source model.

Abstract: A data communication device includes a storage unit configured to store transmission data in a transmission ring buffer area; a read-out processing unit configured to read out the transmission data from the storage unit; and a transmission and reception processing unit configured to transmit the read-out transmission data to an external network and receive a reception confirming notification for the transmitted transmission data. The transmission and reception processing unit is configured to control the read-out processing unit so that the transmission data to be transmitted is read out based on a storage position of last data of the transmission data stored in the transmission ring buffer area and a storage position of last data of the transmitted transmission data indicated by the reception confirming notification.

Abstract: The invention discloses a method for enhancing stability of communication between a contactless card and a card reader, relating to communication field.

Abstract: Double consecutive error correction is described. An integrated circuit with double consecutive error correction logic includes a data storage structure operative to store a set of data and a first error correction code that corresponds to the set of data. The set of data includes multiple data bits. The first error correction code was generated using a generator matrix having multiple bit groups, each bit group including a unique set of bit positions. The integrated circuit also includes an error correction code generator operative to generate, using the generator matrix, a second error correction code that corresponds to the set of data. The integrated circuit further includes a comparator operative to generate a comparison result of the first error correction code and the second error correction code. The integrated circuit includes a data corrector operative to correct two consecutive data bits of the set of data.

Abstract: Diverse erasure encoded fragments, that is, fragments produced by different erasure encoding schemes, may be used to reconstruct a data file. The diverse erasure encoded fragments for the data file are collected and the erasure encoding schemes used to generate the fragments are identified. A fragment matrix is generated from these fragments. An expanded encoding matrix is generated based upon the identified erasure encoding schemes. One or more rows may be removed from the expanded matrix to generate a square matrix. If the square matrix is invertible then it is inverted to provide a decoding matrix. One or more corresponding rows may be removed from the collected fragment matrix. The decoding matrix and the collected fragment matrix are multiplied to recover the data file. Padding symbols may be added to one or more fragments so that all fragments have the same number of symbols per fragment.

Abstract: A method, including factoring an order of a multiplicative group of a Galois Field to produce a first integer factor p and a second integer factor q, wherein the multiplicative group includes (2m?1) elements, m a non-negative integer, so that 2m?1=pq. The method further includes receiving an element x of the Galois Field expressible as ?(qi+j), where ? is a primitive element of the group, i is a first non-negative integer less than p, and j is a second integer less than q. An inverse or a logarithm of the element x is calculated as a function of qi and j.

Abstract: The present disclosure illustrates a BCH decoding method and a decoder thereof. In this BCH decoding method, the BCH decoder receives an encode data at first, then calculates a syndrome of the encode data. After calculating the syndrome of the encode data, the BCH decoder calculates at least one error location of the encode data in response to the syndrome. Next, the BCH decoder detects at least one determining bit which a first bit string of the encode data comprises. The determining bit is configured for operatively determining whether to continue decoding the encode data. Finally, when the determining bit is detected, an error correction is then performed based upon the error location, such that the BCH decoder outputs decode data.

Abstract: A method for non-uniform multiple dimensional decoding, the method may include receiving or generating a multiple dimensional encoded data unit; and decoding by a processor the multiple dimensional encoded data unit to provide a decoded data unit; wherein the multiple dimensional encoded data unit comprises multiple component codes associated with multiple dimensions; wherein the multiple dimensions comprise a plurality of non-uniform dimensions; wherein at least two component codes of each non-uniform dimension differ from each other by encoding rate; wherein the decoding is responsive to encoding rates of component codes of the plurality of non-uniform dimensions.

Abstract: A circuitry for error correction includes a plurality of subcircuits for determining intermediate values Zw0, Zw1, Zw2, Zw3 to be used as coefficients in an error correction expression (z1i, z2i, . . . , zmi)=Zw3·?3ji+Zw2·?2ji+Zw1·?ji+Zw0. The intermediate values Zw0, Zw1, Zw2, Zw3 are determined depending on subsyndromes s1, s3, s5 so that in case of a 1-bit, 2-bit, or 3-bit error zi=(z1i, z2i, . . . , zmi)=(0, 0, . . . , 0) when an error occurred in the bit position i, and zi=(z1i, z2i, . . . , zmi)?(0, 0, . . . , 0) when no error occurred in the bit position i. A correction value ?vi= for the bit position i may then be determined on the basis of the error correction expression evaluated for ?ji.

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract: According to one embodiment, a processing device for multiplying a first polynomial with a second polynomial is described including a first memory storing a representation of the first polynomial, a controller configured to separate the first polynomial into parts, a second memory storing pre-determined results of the multiplications of the second polynomial with possible forms of the parts of the first polynomial, a third memory for storing the result of the multiplication, an address logic, configured to determine, for each part of the first polynomial, a start address of a memory block of the second memory based on the form of the part and the location of the part within the first polynomial and an adder configured to add, for each determined address of the memory block of the second memory, the content of the memory block of the second memory at least partially to the contents of the third memory, wherein the data element of the third memory to which the content of a data element of the memory block of th

Abstract: Cyclic redundancy check (CRC) circuitry of a given input data path width is provided to perform CRC on data packets with fixed/variable word length where either the start of packet or the end of packet or both don't need to be aligned with the last and first word or bit of the CRC circuitry's input data path. The CRC circuitry is organized in a hierarchical configuration. A first level performs partial cyclic redundancy checks which are then combined in a second level to perform the cyclic redundancy check from all received data words or bits independent of the start of packet and end of packet positions. The hierarchical configuration enables the increase of the input data path width without incurring the significant increase in area observed for conventional CRC circuitry. This also decreases the number and length of interconnects compared to conventional CRC circuitry, and thus facilitates timing closure.

Abstract: The present invention discloses a method for transmitting uplink control signaling in a Physical Uplink Shared Channel (PUSCH). The method includes: when two transport blocks/codewords are transmitted in the PUSCH, mapping uplink control signaling to the layer corresponding to one of the two transport blocks/codewords to transmit. The present invention also discloses an apparatus for transmitting uplink control signaling in the PUSCH. The apparatus includes: a mapping unit, used for mapping uplink control signaling to the layer corresponding to one of two transport blocks/codewords when the two transport blocks/codewords are transmitted in the PUSCH; and a transmission unit, used for transmitting the uplink control signaling. The present invention effectively solves the problem of transmitting uplink control signaling in the PUSCH when the PUSCH uses spatial multiplexing in an LTE-A system.

Abstract: The technology may include: a first error detection operation unit configured to perform a serial error detection operation on a data signal which is inputted in sequence through each of multiple input/output pads, and to generate multiple pieces of preliminary information; and a second error detection operation unit configured to perform a parallel error detection operation on the multiple pieces of preliminary information, and to generate an error detection code.

Abstract: An AD converter includes a delta-sigma AD converter configured to receive an analog signal through an input terminal and obtain a higher-order bit conversion result, a first cyclic AD converter configured to receive a residual signal resulting from removal of a higher-order bit or bits, and performs a conversion process having a amplification factor of one to obtain a 1.5-bit conversion result, a second cyclic AD converter configured to perform a conversion process having an amplification factor of two to obtain a lower-order bit conversion result, and a shift register and a digital accumulator circuit that are configured to receive a higher-order bit, a 1.5-bit, and a lower-order bit conversion result and output an AD conversion value.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance performance of error control encoding. The method includes receiving information data and generating parity information based on an m×k parity matrix comprising an array of b×b circulant sub-matrices, including m columns of said sub-matrices, each column comprising k said sub-matrices. The method further includes dividing the information data into a plurality of b-sized trunks and generating m parity segments. Each parity segment consists of b bits, and each parity segment is generated by multiplying each of the k b×b circulant sub-matrices in a respective column of the parity matrix by a corresponding trunk of information data, where each multiplication of a b×b circulant sub-matrix by a corresponding trunk comprises b2 concurrent computations. The method further includes generating a codeword based on the information data and the m parity segments.

Abstract: Techniques and apparatus are provided for conditional offload of one or more LLRs or decoded bits. An exemplary electronic device (ED) method includes receiving a transmission of a physical downlink shared channel (PDSCH) having a transport block (TB) comprising at least one code block (CB), performing a cyclic redundancy check (CRC) of the at least one CB, in a memory external to a modem core of the ED, storing a subset of log-likelihood ratios (LLRs) associated with the at least one CB if the at least one CB failed the CRC or decoded bits associated with the at least one CB if the at least one CB passed the CRC, wherein the subset is based on an LLR range of the transmission relative to an LLR range of one or more previous transmissions, and using the stored subset of LLRs or decoded bits to process a re-transmission of the PDSCH.

Abstract: Systems and methods for charging multiple rechargeable energy storage systems (“RESSs”) included in one or more vehicles using a single charging system are presented. In some embodiments, a method for charging one or more RESSs may include receiving an indication that one or more charging ports of a plurality of charging ports included in a charging system have RESSs coupled thereto. Based on the indication, a charging map may be generated. One or more charging parameters may be determined based on the generated charging map. Based on the charging parameters, a switching mechanism included in the charging system may be selectively actuated to provide electrical power from a charging power source to charging ports coupled to RESSs.

Abstract: A first digital signal sequence including I and Q digital signal sequences is obtained, the first digital signal sequence being obtained by multiplying each bit of an I-sequence and a Q-sequence in a digital signal sequence system by a first code among codes constituting n-th order (n is an integer) orthogonal codes. A second digital signal sequence is obtained by multiplying I and Q digital signal sequences by a first coefficient greater than 1, the I and Q digital signal sequences being obtained by multiplying each of the bits in the I-sequence and the Q-sequence in the digital signal sequence system by a first code among codes constituting 2n-th order orthogonal codes. The first digital signal sequence and the second digital signal sequence are added on a bit-by-bit basis to create one digital signal sequence, and the one digital signal sequence is transmitted from a single antenna.

Abstract: The various implementations described herein include systems, methods and/or devices for enhancing the performance of error control decoding. The method includes receiving at an LDPC decoder data from a storage medium corresponding to N variable nodes. The method further includes: updating a subset of the N variable nodes; updating all check nodes logically coupled to the updated subset of the N variable nodes; and generating check node output data for each updated check node including at least an updated syndrome check. Finally, the method includes: stopping decoding of the read data in accordance with a determination that the syndrome checks for all the M check nodes are valid syndrome checks or initiating performance of the set of operations with respect to a next subset of the N variable nodes in accordance with a determination that the syndrome checks for all the M check nodes include one invalid syndrome check.

Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

Abstract: A method begins by a processing module of a dispersed storage network (DSN) receiving data in a redundant array of independent disks (RAID) format and converting from the RAID format to an original format of the data. The method continues with the processing module dispersed storage error encoding a data segment of the data in the original format to produce a set of encoded data slices, where a set of encoded data slices includes a decode threshold sub-set of encoded data slices and an error correcting sub-set of encoded data slices. The method continues with the processing module converting the decode threshold sub-set of encoded data slices into a RAID formatted data segment, storing the RAID formatted data segment in RAID memory, and storing at least the error correcting sub-set of encoded data slices in DSN memory.

Abstract: An apparatus is disclosed. In this apparatus, at least one coder block has a parity check matrix. The parity check matrix comprises each element of an H matrix expanded by a Progressive Edge Growth (“PEG”) expansion factor and an Approximate Cycle Extrinsic Message Degree (“ACE”) expansion factor.

Abstract: According to one embodiment, a memory controller includes an encoding unit that executes an error correction coding process on input-data and generates a code word, a calculation control unit that controls whether to execute a multiplication calculation of a multiplication circuit, and a memory interface unit that controls writing of the code word to the memory and reading of the code word from the memory, and the encoding unit includes a remainder circuit that performs a remainder calculation on the input-data using a first generator polynomial and generates a first code word having a first error correction capability and a first multiplication circuit that performs a multiplication calculation on the first code word using a second generator polynomial and performs a multiplication calculation of generating a second code word having a second error correction capability.

Abstract: The present invention relates to an error control technology in the communication system and discloses a method and an apparatus for implementing Cyclic Redundancy Check (CRC) codes to improve the operation performance of the system significantly and satisfy operation requirements when processing high-rate CRC data. The method includes: performing at least one XOR operation for information bits input in parallel to obtain a first result, where at least one pipeline is added during the XOR operation; performing an XOR operation for a previously obtained CRC code to obtain a second result; and performing an XOR operation for the second result and the first result to obtain a current CRC code. The present invention is applicable to any field that needs to implement CRC codes by means of hardware.

Abstract: A method and apparatus to optimize each of the plurality of reduction stages in a Cyclic Redundancy Check (CRC) circuit to produce a residue for a block of data decreases area used to perform the reduction while maintaining the same delay through the plurality of stages of the reduction logic. A hybrid mix of Karatsuba algorithm, classical multiplications and serial division in various stages in the CRC reduction circuit results in about a twenty percent reduction in area on the average with no decrease in critical path delay.

Abstract: A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction by storing the n-bit polynomial in one of two operands.

Abstract: The present invention discloses a method and apparatus for processing and error correction of a GFP-T superblock, where the 64 bytes of payload data of a first superblock are buffered in the first page of a two-page buffer. The flag byte is buffered in a separate buffer, and a CRC operation is performed in a separate logic element. The result of the CRC operation is checked against a single syndrome table which may indicate single- or multi-bit errors. As the payload data of the first superblock is processed and read out of the first page of the two-page buffer, the payload data of a second superblock is written into the second page of the two-page buffer to be processed and corrected.

Abstract: Exemplary embodiments for providing multi-bit error correction based on a BCH code are provided. In one such embodiment, the following operations are repeatedly performed, including shifting each bit of the BCH code rightward by 1 bit while filling the bit vacated due to the rightward shifting in the BCH code with 0, calculating syndrome values corresponding to the shifting of the BCH code, and determining a first error number in the BCH code under the shifting based on the syndrome values corresponding to the shifting of the BCH code. In the case where the first error number is not equal to 0, modified syndrome values are calculated corresponding to the shifting of the BCH code. The modified syndrome values are those corresponding to the case that the current rightmost bit of the BCH code under the shifting is changed to the inverse value. Additional operations are performed as described herein.

Abstract: In an arrangement of the disclosed systems, devices, and methods, a codeword encoded with a first number of check symbols is received and asymmetrically processed according to a second number of check symbols, where the second number of check symbols is less than the first number of check symbols, to produce an error locator polynomial and an error evaluator polynomial. A derivative of the error locator polynomial is produced by outputting a first polynomial term and a second polynomial term, wherein the second polynomial term is a constant. The derivative of the error locator polynomial is produced using a variable finite-field multiplier and without use of a divider.

Abstract: In a method for generating a physical layer (PHY) data unit for transmission via a communication channel, a plurality of information bits to be included in the PHY data unit are received, and a number of orthogonal frequency division multiplexing (OFDM) symbols that are needed to include the plurality of information bits after encoding with a low density parity check (LDPC) encoder is determined. One or more of a, b, c, and d are performed according to a set of rules so that a receiving device can determine a number of information bits in the PHY data unit based on i) an indication of the number of OFDM symbols, and ii) the set rules: a) adding padding bits and/or shortening bits prior to encoding with the LDPC encoder, b) removing shortening bits after encoding with the LDPC encoder, c) removing parity bits after encoding with the LDPC encoder, d) repeating information and/or parity bits after encoding with the LDPC encoder. The plurality of information bits are encoded using the LDPC encoder.

Abstract: There is provided a method of encoding and decoding data using an error control code having a codebook G. The codebook G is a sub-codebook of a codebook P. Each codeword g in the sub-codebook G has an autocorrelation amplitude that is different from and higher than each correlation amplitude between g and each of the other codewords in the sub-codebook G. In one specific embodiment in which the codebook P is that of a Reed-Muller code, using G instead of P reduces the likelihood of the presence of more than one maximum correlation amplitude when computing the non-coherent decision metric during decoding.

Abstract: A method for encoding multiple data symbols, the method may include receiving or calculating, by a computerized system, multiple (k) input data symbols; wherein the multiple input data symbols belong to a finite field F of order q; q being a positive integer that may exceed n; mapping the multiple input data symbols, by an injective mapping function, to a set of encoding polynomials; wherein the set of encoding polynomials comprises at least one encoding polynomial; and constructing a plurality (n) of encoded symbols that form multiple (t) recovery sets by evaluating the set of encoding polynomials at points of pairwise disjoint subsets (A1, . . . , At) of the finite field F; wherein each recovery set is associated with one of the pairwise disjoint subsets of the finite field F.

Abstract: According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than “2”, by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1<=s<t). The search processing unit calculates the root of the error position polynomial, with a concurrency of computation being “1”, when the number of error bits exceeds the predetermined value s.

Abstract: A decoder, a method of decoding and systems implementing the same are disclosed. In one example, the method includes calculating syndrome values from input codewords, generating an error location polynomial about the codewords using the syndrome values, determining an error count in the codewords using the error location polynomial, and adjusting power consumption of a circuit in response to the determined error count in the codewords. In one example, a frequency of a clock signal to be provided to a search circuit may be determined based on the error count, and the clock signal may be provided having the determined frequency to a search circuit, such as a Chien search circuit.