Abstract: Systems and methods for adaptively operating a storage device are provided. A level of integrity of storing data in the storage device is determined. A coding scheme is selected based on the determined level of integrity of the storage device. An operation is performed on the storage device using the selected coding scheme.

Abstract: A storage device includes a non-volatile memory device outputting read data from a source area and a memory controller configured to execute an ECC operation on a plurality of vectors in the read data and to write the error-corrected read data into target area of the non-volatile memory device. The memory controller declares that a vector corresponding to a clean area is decoding pass without using a flag bit among the plurality of vectors during the error correction operation.

Abstract: A CRC code is generated from original data, a BCH code is generated based on the original data and CRC code; the original data, CRC code, and BCH code are recorded in pages from different planes of plural memory chips. An RS code is generated from the original data across pages, a CRC code is generated based on the RS code, a BCH code is generated based on the RS code and the CRC code; the RS, CRC, and BCH codes are recorded in a different memory chip than the original data. When reading data, error correction is performed on the original data using the BCH code, then CRC is calculated. If the number of errors is correctable by erasure correction using the RS code, the original data is so corrected. Otherwise, normal error correction using the RS code and further error correction using the BCH code are performed.

Abstract: A method and apparatus are provided for determining bits in a convolutionally decoded output bit stream to be marked for erasure. K-bits and p-bits of the convolutionally encoded output bit stream may be compared with a corresponding k-bits and p-bits of a delayed version of the input bit stream. For each bit of the k-bits (p-bits) in the convolutionally encoded output bit stream and in the corresponding k-bits (p-bits) of the delayed version of the input bit stream, a number of or pattern of conflicting bits and whether the number of conflicting bits exceeds a threshold number or pattern of conflicting bits may be determined. The output bit stream may be sent to a block decoding component for decoding with the k-bit streams marked for erasure.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to techniques for accurately determining a number of data symbols in a data packet. The techniques provided herein may allow a receiving terminal to correct number of symbol calculations based on such ambiguous length field values.

Abstract: Coding circuitry for difference-based data transformation in an illustrative embodiment comprises a difference-based encoder having a plurality of processing stages, with the difference-based encoder being configured to generate respective orders of difference from a sequence of data samples and to output encoded data determined based on at least a selected one of the orders of difference. The coding circuitry may be configured to implement lossless, linear compression of the sequence of data samples. The coding circuitry may additionally or alternatively comprise a difference-based decoder having a plurality of processing stages, with the difference-based decoder being configured to process encoded data comprising selected ones of a plurality of orders of difference and to reconstruct a sequence of data samples based on the selected orders of difference.

Abstract: According to one embodiment, a data storage apparatus comprises a channel controller, an encoding module, and a data controller. The channel controller configured to control data input and output to and from nonvolatile memories for channels. The encoding module configured to generate encoded data for an interchannel error correction process, using data stored in each of the nonvolatile memories. The data controller configure to manage the encoded data in units of logical blocks when the channel controller writes the encoded data in parallel to the channels, and to allocate parity data contained in the encoded data to planes of the same channel in each logical block.

Abstract: A system, method and program product, the system in embodiments comprising: one or more computers operably connected to one or more computer-readable storage media comprising computer-readable program code to perform steps: associating a first plurality of data disk blocks; generating checksum data on a second plurality of checksum disk blocks, using an m-out-of-n encoding algorithm; generating a third plurality of redundant storage disk blocks, using an 1-out-of-n encoding algorithm that allows for reconstruction using a second recovery algorithm of a selected disk block by reading a proper subset of remaining data disk blocks, reconstructing a single one of the data disk blocks when one or more reconstruction criteria are met, using the second recovery algorithm; reconstructing, when two or more of the data disk blocks are lost, the two or more of the data disk blocks and/or checksum disk blocks that are lost, using the first recovery algorithm.

Abstract: A non-binary low density parity check data decoder comprises a variable node processor operable to update variable node symbol values according to a plurality of elements in a non-binary Galois Field, a check node processor connected to the variable node processor and operable to perform parity check calculations, and a controller operable to perform symbol flipping and to control decoding iterations in the variable node processor and the check node processor.

Abstract: Circuitry for generating a first number of Reed-Solomon check symbols from a second number of input data symbols includes storage for a plurality of generator coefficients, a plurality of multipliers, each of the multipliers having a data symbol input, and a coefficient input connected to the storage, and having an output. The circuitry also includes accumulator circuitry that accumulates outputs of the multipliers to generate the check symbols. The circuitry can be provided in fixed logic, or configured in a programmable integrated circuit device, such as a programmable logic device.

Abstract: A DTV transmitting system includes an encoder, a randomizer, a block processor, a group formatter, a deinterleaver, and a packet formatter. The encoder codes enhanced data for error correction, permutes the coded data, and further codes the permuted data for error detection. The randomizer randomizes the coded enhanced data, and the block processor codes the randomized data at an effective coding rate of 1/H. The group formatter forms a group of enhanced data having data regions, and inserts the coded enhanced data into at least one of the data regions. The deinterleaver deinterleaves the group of enhanced data, and the packet formatter formats the deinterleaved data into corresponding data bytes.

Abstract: Coded video data may be transmitted between an encoder and a decoder using multiple FEC codes and/or packets for error detection and correction. Only a subset of the FEC packets need be transmitted between the encoder and decoder. The FEC packets of each FEC group may take, as inputs, data packets of a current FEC group and also an untransmitted FEC packet of a preceding FEC group. Due to relationships among the FEC packets, when transmission errors arise and data packets are lost, there remain opportunities for a decoder to recover lost data packets from earlier-received FEC groups when later-received FEC groups are decoded. This opportunity to recover data packets from earlier FEC groups may be useful in video coding and other systems, in which later-received data often cannot be decoded unless earlier-received data is decoded properly.

Abstract: An ERSEC system that applies a level of error correction that is inversely related to susceptibility to error as indicated by a signal-to-noise ratio (SNR) profile of a channel. The SNR profile is estimated, detected or retrieved from an external source. The ERSEC system is used with any channel for which the SNRs can vary spatially, temporally or both.

Abstract: An accelerated erasure coding system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The processing core, storage medium, and computer instructions are configured to implement an erasure coding system, which includes: a data matrix for holding original data in the main memory; a check matrix for holding check data in the main memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the check data; and a thread for executing on the processing core. The thread includes: a parallel multiplier for concurrently multiplying multiple entries of the data matrix by a single entry of the encoding matrix; and a first sequencer for ordering operations through the data matrix and the encoding matrix using the parallel multiplier to generate the check data.

Abstract: The embodiments of the invention disclose a method and a device for decoding an RS code, the method comprising: receiving bit reliability information of the RS code output by a channel, performing a hard decision on the bit reliability information to obtain a hard-decision result value sequence; determining a type of an error of the hard-decision result value sequence according to an initial check array corresponding to an encoding mode of the RS code; according to preset corresponding relationships between types of errors of the hard-decision result value sequence and error-correcting modes capable of correcting the errors, determining an error-correcting mode corresponding to the type of the error of the hard-decision result value sequence, and performing a bit error correction on the hard-decision result value sequence according to the determined error-correcting mode; outputting the hard-decision result value sequence after the bit error correction as a decoding result.

Abstract: The subject matter disclosed herein provides a mechanism for identifying packet boundaries in a data table, such as a Reed-Solomon table. The method may include receiving one or more packets for insertion into a table. A first indicator may be inserted into the table. The first indicator may be associated with one or more rows of the table and may identify whether each of the one or more rows includes one or more fragments (e.g., a packet beginning, a packet ending, and the like). In each of the rows identified by the first indicator as including one or more fragments, a second indicator may be inserted. The second indicator may represent a length in bytes of at least one of the corresponding packet fragments. Related systems, apparatus, methods, and/or articles are also described.

Abstract: Disclosed are a decoding method and device for concatenated code, for the decoding of concatenated code composed of low density parity code (LDPC) and Reed-Solomon (RS) code. The method includes carrying out LDPC soft decision iterative decoding on bit de-interleaved data flow, and carrying out check decision on LDPC codeword obtained from decoding by using a check matrix; carrying out de-byte-interleave on an information bit of the LDPC codeword obtained from decoding and converting check information of the LDPC codeword into puncturing information of RS codeword; selecting a decoding mode according to the puncturing information of the RS codeword to carry out RS decoding. By way of the solution of the present invention, the RS decoding performance can be improved without increasing the computation complexity, thus greatly improving the receiving performance of the CMMB terminal as compared to the conventional method.

Abstract: In one embodiment, a block code decoder is provided. The block code decoder includes a first decoder configured to decode Bose-Chaudhuri-Hochquenghem (“BCH”) coded data packets and a second decoder configured to receive and decode Reed-Solomon (“RS”) encoded data from the first decoder. The first decoder includes a first buffer configured to receive BCH encoded data and one or more BCH decoder circuits coupled to the first buffer. Each BCH decoder circuit decodes a plurality of BCH encoded bits in parallel. A second buffer is arranged to store the decoded BCH data. The second decoder includes a third buffer, arranged to receive the RS encoded data from the first decoder, one or more RS decoder circuits configured to decode a plurality of RS encoded bits in parallel, and a fourth buffer arranged to store RS payload data decoded by the RS decoder circuits.

Abstract: In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC? pattern to obtain a RS packet align boundary.

Abstract: The present invention discloses a receiving system and a method of processing data to receiving and processing mobile service data. The receiving system may include a signal receiving unit, a demodulating unit, a data processor, and a middleware engine. The signal receiving unit receives a broadcasting signal, which includes IP packets, payload of the IP packets including a DSM-CC module data part and a DSM-CC header, the DSM-CC module data part including a plurality of DSM-CC objects, and the DSM-CC header including identification information for identifying the DSM-CC module. The demodulating unit demodulates the received broadcasting signal including IP packets. The data processor extracts a plurality of DSM-CC objects of a corresponding payload with reference to DSM-CC header information of the IP packets demodulated by the demodulating unit and configuring a DSM-CC module, which includes identification information and the extracted DSM-CC objects.

Abstract: A digital broadcast system and a method of processing data are provided. The transmitting system of the digital broadcast system includes an encoder for encoding mobile data for FEC to build RS frames, a signaling encoder for encoding TPC data including the RS frame mode information, a divider for dividing at least one of the RS frames into a plurality of portions, a block processor for converting one portion to a plurality of SCCC blocks, a converter for converting the SCCC blocks to data blocks, a group formatter for forming data groups, a packet formatter for forming data packets including data in the data groups, a multiplexer for multiplexing main data packets including main data and the data packets, a trellis encoder for performing trellis encoding on data in the multiplexed data packets and a transmission unit for transmitting the broadcast signal including a parade of the data groups.

Abstract: Systems, methods, and other embodiments associated with decoder based data recovery are described. According to one embodiment, an apparatus includes a decoder configured to perform a decoding process on codewords to verify that the codewords meet coding constraints. The decoder includes a recovery unit configured to store recovery instructions for performing a modified decoding process. The recovery unit is further configured to execute the stored recovery instructions when a decoded codeword fails to meet the coding constraints.

Abstract: An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within the first test error pattern is flipped to obtain a second test error pattern, wherein i?j.

Abstract: A method and apparatus are provided for determining bits in a convolutionally decoded output bit stream to be marked for erasure. K-bits and p-bits of the convolutionally encoded output bit stream may be compared with a corresponding k-bits and p-bits of a delayed version of the input bit stream. For each bit of the k-bits (p-bits) in the convolutionally encoded output bit stream and in the corresponding k-bits (p-bits) of the delayed version of the input bit stream, a number of or pattern of conflicting bits and whether the number of conflicting bits exceeds a threshold number or pattern of conflicting bits may be determined. The output bit stream may be sent to a block decoding component for decoding with the k-bit streams marked for erasure.

Abstract: A method includes a first encoding operation associated with a first algebraic error correcting code generating a first set of first parity bits corresponding to a first set of information bits and a second set of first parity bits corresponding to a second set of information bits. A second encoding operation associated with a second algebraic error correcting code generates a first set of second parity bits corresponding to the first set of information bits and a second set of second parity bits corresponding to the second set of information bits. A third encoding operation generates a set of joint parity bits. The first set of information bits, the second set of information bits, the first set of first parity bits, the second set of first parity bits, and the joint parity bits may be stored in a data storage device as a single codeword.

Abstract: A method for integrating data and header protection in tape drives includes receiving an array of data organized into rows and columns. The array is extended to include one or more headers for each row of data in the array. The method provides two dimensions of error correction code (ECC) protection for the data in the array and a single dimension of ECC protection for the headers in the array. A corresponding apparatus is also disclosed herein.

Abstract: An encoder creates an (p,k,n) n-state codeword with p n-state symbols of which k n-state symbols are data symbols, an n-state symbol being represented by a signal with n>2, p>2 and k>(p-k). Intermediate states of an encoder in forward and in reverse direction are provided in a comparative n-state expression and implemented on a processor. A plurality of signals representing a codeword with at least one n-state symbol in error is processed by the processor by evaluating the comparative n-state expression. A partial result of an expression is determined after a symbol has been received. An error location and an error magnitude are determined. The error is corrected by the processor.

Abstract: Disclosed herein is a decoding apparatus that performs soft-decision decoding on a linear block code, the apparatus including a hard-decision decoder configured to perform hard-decision decoding on a received word using a hard-decision decoding algorithm; and a soft-decision decoder configured to perform, using a soft-decision algorithm, soft-decision decoding merely on a received word for which the hard-decision decoder has failed in the hard-decision decoding.

Abstract: Received communication signals may be decoded according to a combined, iterative inner code—outer code decoding technique. The inner code decoding is based on information produced by the outer code decoding.

Abstract: According to one embodiment, a storage device performs error correction processing of a code of which the maximum correction performance is T bits, the decoding device including an error correction processor for performing error correction processing using calculating devices capable of handling errors of J bits (J is an integer equal to or more than one and less than T), wherein an initial value of an error number expectation value is set to I (I is an integer equal to or more than one and less than T), and execution of increment of the error number expectation value and execution of the error correction processing is repeated until no error is detected or the error number expectation value becomes T bits.

Abstract: Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. Reduced complexity error detection and correction hardware and/or routines detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array. The ECC code is distributed throughout the stored data in the memory segment.

Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

Abstract: A method includes calculating a first syndrome of a codeword read from a memory location under a first set of conditions and calculating a second syndrome of the codeword read from the memory location under a second set of conditions. The method also includes analyzing the first and second syndromes and applying one of the first and second syndromes to the codeword to find the codeword having a minimum number of errors.

Abstract: Memory devices and methods are described such as those that mix data and associated error correction code blocks between multiple memory device locations. Examples include mixing between multiple memory blocks, mixing between memory pages, mixing between memory chips and mixing between memory modules. In selected examples, memory blocks and associated error correction code are mixed between multiple levels of memory device hierarchy.

Abstract: A method and a system of multidimensional encoding and/or decoding to be processed by a computer or a digital hardware system. The method utilizes an error correcting code which is chosen from the group comprising RS, BCH, BCH algebraic, RM (Reed-Muller), among others. The method is carried out by the steps of attribution of a dimension for each bit in the symbols set of a message, with symbols with at least two bits, so the error correcting code will be performed over the dimensions and not over the symbols; grouping of the dimensions in the same position of the origin symbols in a new symbol, so the symbols will be treated as symbols in both stages of the code, in that the error correcting code is performed in every dimension; and processing of each dimension in parallel or in an independent manner, using an error correcting code.

Abstract: Methods and apparatus are presented to allow one receiver architecture to be used for the reception of two different SDARS signals. Common receiver functions can be utilized to process each signal, thereby obviating the need to duplicate hardware elements. For example, it can be assumed that both signals will not be received at the same time, thus allowing for considerable hardware reuse and lowering the cost of an interoperable receiver.

Abstract: Systems and methods are provided for recovering data stored in memory. A group of data is encoded using a first layer of code to form a first encoded group of data. Individual portions of the first encoded group of data are then encoded using a second layer of code to form a second encoded group of data. A processor may request access to an individual portion of the group of data. The encoded version of the requested individual portion is retrieved from memory and decoded using the second layer of code to recover the requested individual portion. If the recovery of the requested individual portion fails, the remaining encoded portions of the group are retrieved from memory and decoded using the first layer of code to recover the requested individual portion.

Abstract: Circuitry for, in p parallel streams, searching a codeword having n symbols for roots of a cyclic code polynomial having a number of terms includes a plurality of multipliers, a source of constants derived from roots of the polynomial, and at least one counter that supplies an index. For each received symbol of the codeword, the multipliers multiply respective terms of the polynomial for a previous received symbol by constants from the source of constants, the counter advances to select respective products of the constants and the respective terms for the previous received symbol.

Abstract: LDPC coding systems for 60 GHz millimeter wave based physical layer extension. LDPC (Low Density Parity Check) encoding in cooperation with sub-carrier interleaving, in the context of orthogonal frequency division multiplexing (OFDM), and appropriate symbol mapping is performed in accordance with transmit processing as may be performed within a communication device. In a receiving communication device, receive processing may be performed on a received signal based on the type of LDPC, sub-carrier interleaving, and symbol mapping thereof. The LDPC code employed in accordance with such LDPC encoding may have a partial-tree like structure. In addition, appropriate manipulation of the bits assigned to respective sub-carriers may be performed to ensure that the bits emplaced in the MSB (Most Significant Bit) location of various symbols has some desired diversity (e.g., from different codewords, from appropriately different locations within a given codeword, etc.).

Abstract: A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities can be performed.

Abstract: The non-volatile memory system includes a non-volatile memory and a controller. The non-volatile memory includes a data region including a sector region for storing sector data, and an uncorrectable information region for storing uncorrectable sector information on the sector region. The controller includes an information generation unit for generating the uncorrectable sector information that indicates whether the sector region is assigned to an uncorrectable sector region, according to a command output from a host.

Abstract: Devices and methods for processing wireless high definition video data to be communicated in an uncompressed format over a wireless medium is disclosed. In one embodiment, an encoder includes a first outer encoder that encodes a first portion of a video data stream. A second outer encoder encodes a second portion of the video data stream. A first parser parses the first encoded data stream into first sub-video data streams. A second parser parses the second encoded data stream into second sub-video data streams.

Abstract: Described herein are an apparatus, system, and method for encoder assisted decoding of linear systematic block codes. The apparatus comprises a first logic unit to receive a codeword from a memory, the codeword having a data portion and a corresponding parity portion; an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword; a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder; and a correction unit to correct the data portion of the codeword via the generated first parity portion.

Abstract: A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.

Abstract: Systems and methods are provided for enhancing the performance and throughput of a low-density parity check (LDPC) decoder. In some embodiments, the enhanced performance and throughput may be achieved by detecting and correcting near-codewords before the decoder iterates up to a predetermined number of iterations. In some embodiments, a corrector runs concurrently with the decoder to correct a near-codeword when the near-codeword is detected. In alternate embodiments, the corrector is active while the decoder is not active. Both embodiments allow for on-the-fly codeword error corrections that improve the performance (e.g., reducing the number of errors) without decreasing the throughput of the decoder.

Abstract: Apparatus and methods for selective decoding of received code blocks are disclosed. An example method includes receiving a code block, determining a code block quality indicator for the received code block, and attempting to decode the received code block if the code block quality indicator is greater than or equal to a threshold. If the code block quality indicator is less than the threshold, the received code block is discarded without decoding attempts. The threshold may be a static or dynamic threshold.

Abstract: A digital broadcasting receiving system and method, where the digital broadcasting receiving system includes: a demodulator receiving and demodulating a dual transmission stream including a turbo stream and a normal stream; an equalizer equalizing the demodulated dual transmission stream; a first processor restoring normal stream data from the equalized dual transmission stream; and a second processor restoring turbo stream data from the equalized dual transmission stream and eraser decoding the turbo stream data. Thus, the reception sensitivity of a transmission stream including a turbo stream can be improved.

Abstract: A reception system and a method for processing data in the reception system are disclosed. The reception system includes a baseband processor receiving a broadcasting signal including mobile service data and main service data, the mobile service data including first service data and second service data having a format different from that of the first service data, the second service data configuring a Reed Solomon (RS) frame, and the RS frame including a table which describes the second service data and signaling information of the second service data, a table handler parsing the table from the RS frame and extracting the signaling information of the second service data, and service handlers parsing the second service data from the RS frame on the basis of the extracted signaling information of the second service data. Accordingly, it is possible to transmit/receive service data having a format different from that of the existing method in a single MH system.

Abstract: A system is used to predict when a decoding process will fail to correct an error burst within a transmission. A decoder receives an input bit stream and processes it to produce an output bit stream, which is convolutionally encoded. K-bits of the convolutionally encoded output bit stream are compared with a corresponding k-bits of a delayed version of the input bit stream, with the k-bits starting at a first bit and ending at first bit+k. For each bit of the k-bits in the convolutionally encoded output bit stream and in the corresponding k-bits of the delayed version of the input bit stream, a number of conflicting bits and whether the number of conflicting bits exceeds a threshold number of conflicting bits is determined. The output bit stream is sent to a block decoding component for decoding with the bits marked for erasure.