Abstract: Apparatus having corresponding methods and storage devices comprise: an iterative decoder configured to generate codewords based on input samples, wherein the iterative decoder is further configured to perform a number of decoding iterations for each codeword, wherein the number of decoding iterations is an integer greater than zero, and wherein the number of decoding iterations does not exceed a limit number; and a sensor configured to generate one or more measurements of a physical variable, wherein the limit number is set in accordance with the one or more measurements generated by the sensor.

Abstract: Provided is a receiver for processing VSB signal. The receiver includes a first equalizer/decoder unit and a second equalizer/decoder unit. The first equalizer/decoder unit performs a first equalizing operation, first TCM decoding and first RS decoding on a received symbol to output a first dibit. The second equalizer/decoder unit performs a second equalizing operation, second TCM decoding and second RS decoding on the received symbol to output a transport stream. The first dibit is provided as a priori information for a soft-decision operation of the second TCM decoding.

Abstract: A system and method for determining a transport format of a transport channel is described. A guiding stream is received on a guiding transport channel and a guided stream is received on a guided transport channel. The guided stream is convolutionally decoded to produce a plurality of Viterbi path metrics. A transport format for the guided transport channel is selected from possible transport formats. The possible transport formats are determined by information provided on the guiding transport channel. The selection of the transport format is based at least in part on a metric computed from a combination of the Viterbi path metrics.

Abstract: A digital communication receiver generates soft decision values at the output of a maximum likelihood sequence estimator module. The values are fed into a following forward error correction module that uses the soft-decision input signal to improve error correction performance. The disclosed techniques can be used for receiving optical signals in an optical communication network.

Abstract: An apparatus and a method for decoding bits of a received signal in a communication system are provided. The method includes determining path metrics of respective states in a trellis corresponding to the received signal, selecting a start state in the trellis for a traceback in a last window of the trellis, repeating the traceback at least twice within the last window, and when the repeating of the traceback is completed, determining the decoded bits of the received signal using a survived path of a last traceback.

Abstract: A trellis encoding device includes a plurality of trellis encoders to perform trellis-encoding of a transport stream into which a supplementary reference signal (SRS) has been inserted, and performs a memory reset in a region that precedes an SRS; and a parity compensation unit to compensate for parities of the transport stream in accordance with values stored in memories included in the trellis encoders. The plurality of trellis encoders may be implemented in diverse types. The trellis encoding device can perform a memory reset selectively using the stored value of the memory and the inverted value thereof, or selectively using the stored value of the memory and a fixed value. By properly resetting the memory in processing the transport stream into which the SRS has been inserted, DC offset can be reduced.

Abstract: A method for forward error correction decoding. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword.

Abstract: Methods, system and apparatuses for carrier frequency offset estimation are disclosed. The method includes: receiving a preamble sequence rn with a correlator and correlating the preamble sequence with a locally stored Barker code bn to obtain a correlation result cn; extracting peak values from every L points in cn to form a peak value sequence xn, L being a length of a Barker code that corresponds to the sampling rate; performing frequency offset estimation to xn by using at least two frequency offset estimation apparatuses, the at least two frequency offset estimation apparatuses adopting different delay parameters D; and inputting the results output from the at least two frequency offset estimation apparatuses into a frequency offset combination module to calculate a final carrier frequency offset estimate, whereby accurate frequency estimation can be achieved and an appropriate acquisition range of frequency offset can be ensured.

Abstract: Entities implement a phase of communicating data conveyed by a plurality of transport channels, the data of the transport channels being multiplexed into at least one multiplexing frame. The data is rate-matched by transforming an input data block of an initial size into an output data block of a final size. A method includes calculating, by one of the entities, the final size, according to the initial size, a first parameter, a second parameter and a maximum payload of the multiplexing frame. The first parameter is an integer relating to a rate matching ratio of the final size to the initial size. The second parameter is a non-dimensional number corresponding to a maximum percentage of bits to be punctured and is predefined before the calculating. The method further includes executing, by the one of the entities, a transformation of the input data block into the output data block.

Abstract: Various embodiments of the present invention provide apparatuses, systems and methods for data detection in a detector with soft pruning. For example, a data detector is disclosed that includes a branch metric calculator operable to calculate branch metrics for transitions between states in a trellis for the data detector, and a branch metric offset circuit operable to apply branch metric offsets to the branch metrics to yield soft pruned branch metrics. The branch metric offsets comprise a range of probability values from zero percent to one hundred percent.

Abstract: Methods for programming, memory devices, and methods for reading are disclosed. One such method for programming a memory device (e.g., an SLC memory device) includes encoding a two level data stream to a three level stream prior to programming the memory.

Abstract: A method for forward error correction decoding. The method generally includes steps (A) to (D). Step (A) may calculate a plurality of metrics of a codeword using a forward error correction process on a trellis having a plurality of stages. Step (B) may update the metrics over each of the stages. Step (C) may permute the metrics in each of the stages. Step (D) may generate a signal carrying a plurality of decoded bits of the codeword.

Abstract: An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to determine a first set of soft outputs, hard decisions and reliability indicators for a read channel data signal, to determine a second set of soft outputs, hard decisions and reliability indicators based at least in part on the first set of soft outputs, hard decisions and reliability indicators, and to perform an iterative decoding process to decode the read channel data signal based at least in part on the second set of soft outputs, hard decisions and reliability indicators. The first set of soft outputs, hard decisions and reliability indicators are used to determine a reduced-state trellis for determining the second set of soft outputs, hard decisions and reliability indicators.

Abstract: A method for performing data shaping is applied to a controller of a Flash memory, where the Flash memory includes a plurality of blocks. The method includes: performing a program optimization operation according to original data and a plurality of shaping codes, in order to generate trace back information corresponding to a Trellis diagram and utilize the trace back information as side information; and dynamically selecting at least one shaping code from the shaping codes according to the side information to perform data shaping on the original data.

Abstract: A method of detecting a bit sequence, includes estimating parameters to be used to determine a probability distribution of a present signal in each of states of a present time, and calculating metrics of the respective states based on the parameters. The method further includes selecting survivor states from the states based on the metrics, and detecting the bit sequence based on a path to each of the survivor states.

Abstract: Encoding method (1) and device associating p redundancy data bits with k information data bits to determine code words with a block length of n=p+k data bits. The code words are of tail-biting trellis low density parity check type. The method and the device implement a degree distribution profile of the n data bits defining a base code word including multiple replicas of the n data bits with respect to the degree distribution. This base code is represented by a two-states trellis formed of sections with positions accommodating data bits of the base code whereby the number of positions of a section is denoted as the degree of the section. The method and the device makes (2) a partition of the base code trellis into p intersecting regular parts of triple sections representing p parity check equations.

Abstract: Various embodiments of the present inventions provide a symbol flipping LDPC decoding system. For example, a symbol flipping data processing system is disclosed that includes a low density parity check decoder operable to decode codewords and to identify unsatisfied parity checks, a symbol flipping controller operable to change values of at least one symbol in the codewords based on the unsatisfied parity checks to assist the low density parity check decoder to decode the codewords, a scheduler operable to control a decoding and symbol flipping mode in the low density parity check decoder and the symbol flipping controller, and a hard decision queue operable to store hard decisions for converged codewords from the low density parity check decoder.

Abstract: Good transmission characteristics are achieved in the presence of fading with a transmitter that employs a trellis coder followed by a block coder. Correspondingly, the receiver comprises a Viterbi decoder followed by a block decoder. Advantageously, the block coder and decoder employ time-space diversity coding which, illustratively, employs two transmitter antennas and one receiver antenna.

Abstract: Methods are disclosed for improving communications on feedback transmission channels, in which there is a possibility of bit errors. The basic solutions to counter those errors are: proper design of the CSI vector quantizer indexing (i.e., the bit representation of centroid indices) in order to minimize impact of index errors, use of error detection techniques to expurgate the erroneous indices and use of other methods to recover correct indices.

Abstract: A method for accessing extrinsic information in a turbo decoder is disclosed. Operation phases for Forward State Metric Calculators (FSMCs) and Reverse State Metric Calculators (RSMCs) in multiple maximum a posteriori probability (MAP) decoders are misaligned differently based on whether a current half iteration is even or odd. First extrinsic information is read from a memory into the FSMCs and RSMCs using the misaligned operation phases. Second extrinsic information is determined using the MAP decoders. Each row of the second extrinsic information is stored to a different bank in the memory using the misaligned operation phases.

Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

Abstract: Coding circuitry for difference-based data transformation in an illustrative embodiment comprises a difference-based encoder having a plurality of processing stages, with the difference-based encoder being configured to generate respective orders of difference from a sequence of data samples and to output encoded data determined based on at least a selected one of the orders of difference. The coding circuitry may be configured to implement lossless, linear compression of the sequence of data samples. The coding circuitry may additionally or alternatively comprise a difference-based decoder having a plurality of processing stages, with the difference-based decoder being configured to process encoded data comprising selected ones of a plurality of orders of difference and to reconstruct a sequence of data samples based on the selected orders of difference.

Abstract: Techniques to decode tail biting convolutional code are disclosed. A plurality of sets for a trellis may be determined. Each set may include a first stage and a second stage of the trellis. Path metrics for each state in a set may be determined when the first stage and the second stage have a same state. The path metrics may be compared to determine a state with a minimum path metric. Bits from the state with the minimum path metric may be output. Other embodiments are described and claimed.

Abstract: Apparatus and methods are disclosed for decoding data stored on a data storage medium. A disclosed decoding method and decoder include a radial incoherence (RI) detector that increases the probability of detecting RI and improves the decoding performance in terms of the bit error rate of the decoded signal. RI is detected by comparing an input signal to the decoder against a RI threshold value and generating a RI-type signal. The RI detector may include a filter for filtering out noise and error in the RI-type signal, an adaptive threshold unit that adjusts the RI threshold value based upon the RI-type signal, a transition-based threshold unit that adjusts the RI threshold value based upon each transition in the input signal, or a path-based threshold unit that adjusts the RI threshold value based upon a best surviving path corresponding to the input signal, in combination or alone.

Abstract: A modified soft output Viterbi algorithm (SOVA) detector receives a sequence of soft information values and determines a best path and an alternate path for each soft information value and further determines, when the best and alternate paths lead to the same value for a given soft information value, whether there is a third path departing from the alternate path that leads to an opposite decision with respect to the best path for a given soft information value. The SOVA detector then considers this third path when updating the reliability of the best path. The modified SOVA detector achieves max-log-map equivalence effectively through the Fossorier approach and includes modified reliability metric units for the first N stages of the SOVA detector, where N is the memory depth of a given path, and includes conventional reliability metric units for the remaining stages of the detector.

Abstract: A method and apparatus for increasing the data rate and providing antenna diversity using multiple transmit antennas utilize a set of bits of a digital signal to generate a codeword. Delay elements may be provided in antenna output channels, or, with suitable code construction, delay may be omitted. n signals represent n symbols of a codeword are transmitted with n different transmit antennas. At the receiver, the noisy received sequence is decoded. The parallel transmission and channel coding enables an increase the data rate over previous techniques, and recovery even under fading conditions. The channel coding may be concatenated with error correction codes under appropriate conditions.

Abstract: Systems, methods, devices, and computer program products are described for Turbo decoding in a wireless communication system. Turbo encoded wireless signals may be received and demodulated, and forwarded to a branch metric calculator. The branch metric calculator may calculate a set of branch metrics for the demodulated signal. A state metric unit may receive the set of branch metrics and a previously calculated set of state metrics. The state metric unit may perform various comparisons of the set of state metrics before the received set of branch metrics is added to a portion of the state metrics identified through the comparisons.

Abstract: A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.

Abstract: A method includes, during a first iteration of a first decoder for decoding convolutionally encoded data elements, determining a first value of a first path metric. The method also includes, during a second iteration of the first decoder, determining a second value of the first path metric by using the first value of the first path metric as an initial value of the first path metric.

Abstract: A method and apparatus are disclosed for performing joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations. An RSSE scheme is disclosed that cancels the intrasymbol interference caused by other symbol components within the same multidimensional code symbol. The disclosed RSSE technique for multidimensional codes applies where the number of trellis code dimensions exceeds the number of channels. The disclosed RSSE decoder computes the intersymbol interference caused by previously decoded multidimensional code symbols and subtracts the intersymbol interference from the received signal. In addition, a branch metrics unit compensates for the intrasymbol interference caused by other symbol components within the same multidimensional code symbol.

Abstract: In an aspect, in general, a forward error correction algorithm (FEC) utilizes an FEC block structure in a manner that extends the effective error correction such that it can approach an “infinite” length to obtain benefits typical of very large FEC block size without the commensurate computation cost.

Abstract: Various embodiments of the present invention provide apparatuses, systems and methods for data detection in a detector with a pruning control system. For example, a data detector is disclosed that includes a first set of counters operable to distinguish prunable data from non-prunable data in the data detector, a second set of counters operable to generate initial values for the first set of counters, and a prune control signal generator operable to generate a prune control signal based on the first set of counters. The second set of counters is operable to generate the initial values at least in part before a syncmark is detected in a data sector. The initial values are used to initialize the first set of counters when the syncmark is detected in the data sector. The prune control signal controls whether the data detector is allowed to prune a trellis.

Abstract: An extensive use of look-up table (LUT) and single instruction multiple data (SIMD) in different algorithms in a software-defined radio (SDR) system is described. In particular, the LUT is used during spreading modulation, mapping and spreading, scrambling, de-scrambling, soft demapping, and the like. The SIMD is executed by a multi-core processor during implementation of a “min” operation to find an optimal path in a Trellis diagram for a Viterbi decoder.

Abstract: Systems and methods for processing and decoding TCM/BCM-coded signal vectors. A multi-dimensional signal vector is received by, for example, a TCM or BCM decoder. The TCM/BCM decoder identifies the closest signal points in the signal constellation set, or “nearest neighbors,” for each dimension of the received signal vector. The TCM/BCM decoder then forms a test set that includes a plurality of multi-dimensional test vectors, where each dimension of each test vector is based on an identified nearest neighbor. In particular, each test point in the test set is based on a different combination of the nearest neighbors. The TCM/BCM decoder can compute branch metrics based on only the test points in the test set, and can make detection decisions using the computed branch metrics.

Abstract: An A/D conversion unit performs an A/D conversion operation twice during a hold period of an analog value. In a first conversion operation, the A/D conversion unit compares the analog value with a first reference voltage and outputs a comparison result as first converted data. In a second conversion operation, the A/D conversion unit compares the analog value with a second reference voltage and outputs a comparison result as second converted data. The second reference voltage is a voltage obtained by adding or subtracting a minimum resolution voltage to or from the first reference voltage. A digital processing unit averages errors of the first and second converted data by digital processing to detect an A/D conversion error, and feeds back a detection result to the A/D conversion unit as a control value to perform voltage control.

Abstract: Various embodiments of the present invention provide systems and methods for evaluating and debugging a data decoder. For example, a data decoder circuit is discussed that includes an input memory, a data decoder operable to decode data from the input memory in one or more iterations, an output memory operable to store decoded data from the data decoder, and a test port operable to provide access to the input memory, the data decoder and the output memory.

Abstract: Systems and methods are provided for generating error events for decoded bits using a Soft output Viterbi algorithm (SOVA). A winning path through a trellis can be determined and decoded information can be generated. Path metric differences can be computed within the trellis based on the winning path. A plurality of error event masks and error event metrics can be generated based on the decoded information and the path metric differences.

Abstract: A method for soft remodulation in a receiver of transmissions over a wireless telecommunication system, the method including obtaining from a FEC decoder a-posteriori LLR values, converting the a-posteriori LLR values into bit probabilities and computing improved soft symbols estimates as expected values using the bit probabilities in a recursive algorithm. Preferably, the step of converting is implemented using a pre-computed Look Up Table (LUT). Preferably, the step of computing is implemented in a Multiplier-Accumulator having a SIMD structure.

Abstract: The invention relates to a method for correcting a message the generation of which involves transforming an initial message and inserting bit stuffing into the transformed message, which method comprises providing an observation sequence containing the message to be corrected. A number of path hypotheses are generated via a trellis diagram associated with the transformation. The nodes of the trellis diagram each represent a state of a finite-state machine capable of transforming the initial message and the branches represent the possible transitions between nodes. Among the branches of the trellis diagram, certain represent conditional transitions that may be made only when bit stuffing is present. During the generation of a path hypothesis, bit stuffing is detected and the branches taken are those associated with the detected bit stuffing. The most likely path hypothesis relative to the observation sequence is finally retained.

Abstract: A memory efficient, accelerated implementation architecture for BCJR based forward error correction algorithms. In this architecture, a memory efficiency storage scheme is adopted for the metrics and channel information to achieve high processing speed with a low memory requirement. Thus, BCJR based algorithms can be accelerated, and the implementation complexity can be 5 reduced. This scheme can be used in the BCJR based turbo decoder and LDPC decoder implementations.

Abstract: The method according to the invention relates to the decoding of a sequence of symbols, the sequence of symbols having been generated by: calculating a CRC value for an initial message; combining the initial message and the CRC value so as to produce a transformed message; and, encoding the transformed message. The decoding comprises: generating a number of path hypotheses via a trellis diagram corresponding to the trellis diagram of a finite-state machine comprising the encoder and the CRC generator, in which the encoder and the CRC generator are supplied with the same input. According to a preferred embodiment of the method, the trellis diagram is adapted to take into account bit stuffing possibly inserted in the transformed message before encoding.

Abstract: An apparatus for trellis-based detection in a communication system including a processor and memory having computer program code configured to construct a trellis representing a transmitted signal formed from a plurality of symbols, each having a constellation size, transmitted by a number of transmit antennas, and form a log likelihood ratio at nodes of the trellis as a log-sum of a number of exponential terms corresponding to a hypothesized transmitted bit value of the plurality of symbols. The number of exponential terms is limited by a number of most likely paths of the trellis extending from each node of the trellis and the constellation size. The processor and memory including computer program code are further configured to form a list at each node of the trellis of a size limited to the number of the most likely paths of the trellis extending from each node of the trellis.

Abstract: A digital television transmitting system includes a pre-processor, a packet generator, an RS encoder, and a trellis encoder. The pre-processor pre-processes enhanced data by coding the enhanced data for first forward error correction and expanding the FEC-coded enhanced data. The packet generator generates enhanced data packets including the pre-processed enhanced data and main data packets and multiplexes the enhanced and main data packets. Each enhanced data packet includes an adaptation field in which the pre-processed enhanced data are inserted. The RS encoder performs RS encoding on the multiplexed data packets for second forward error correction, and the trellis encoder performs trellis encoding on the RS-coded data packets.

Abstract: A digital television (DTV) transmitter and a method of processing data in the DTV transmitter/receiver are disclosed. In the DTV transmitter, a pre-processor pre-processes the enhanced data by coding the enhanced data for forward error correction (FEC) and expanding the FEC-coded data. A packet formatter generates one or more groups of enhanced data packets, each enhanced data packet including the pre-processed enhanced data and known data, wherein the data formatter adds burst time information into each group of enhanced data packets. And, a packet multiplexer generates at least one burst of enhanced data by multiplexing the one or more groups of enhanced data packets with at least one main data packet including the main data, each burst of enhanced data including at least one group of enhanced data packets.

Abstract: An iterative decoder for decoding a code block comprises a computation unit configured to perform forward and backward recursions over a code block or a code sub-block in each decoding iteration. A first forward/backward decoding scheme is used in a first iteration and a second forward/backward decoding scheme is used in a second iteration. The first and second decoding schemes are different in view of forward and backward processing.

Abstract: Building and using sub-sets of configurations sets are provided to compute the check-nodes update by using a particular representation of the input messages, called here-after trellis-EMS (T-EMS). In a main aspect, the system provides a decoding method to compute dc output vectors of a non-binary parity-check (NBPC) equation decoding unit used for LDPC check codes defined in a NB space.

Abstract: An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

Abstract: An error detection module includes a known-syndrome computing unit, an unknown-syndrome computing unit, and an error detection unit. The known-syndrome computing unit is operable to convert a received signal into a target signal, to obtain known syndromes based upon the target signal, and to generate an errata-locator polynomial based upon an erasure-locator polynomial and the known syndromes. The unknown-syndrome computing unit is operable to compute unknown syndromes based upon the errata-locator polynomial and the known syndromes. The error detection unit is operable to obtain a syndrome set that includes the known syndromes and the unknown syndromes, to obtain an error detection signal according to the syndrome set, and to provide an error correction module coupled thereto with the syndrome set and the error detection signal for enabling the error correction module to correct an error of the received signal.

Abstract: An embodiment of a method for decoding is disclosed. For this embodiment of the method, a decoder is limited to a set number of iterations for a decoding sequence. The set number of iterations is selected to be less than an optimal number of iterations for an optimal bit error rate (“BER”) resulting in a BER penalty. Inner loop decoding operations are performed within the decoder for the set number of iterations. Reliability information is output from the decoder to a data slicer. A symbol stream is output from the data slicer responsive to the reliability information.

Abstract: A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.