Abstract: A method and apparatus for encoding and decoding linear block codes while using limited working storage is disclosed. For decoding, the error syndromes are calculated incrementally as each encoded symbol is received. That is, as each symbol, ri of the code word is received, the received symbol, ri is multiplied by the entries in the “ith” column of a decoding matrix, resulting in intermediate syndrome components. The intermediate syndrome components are added to the appropriate entry in a syndrome vector. Once all symbols ri are received, the syndrome vector contains the error syndromes si for the received code word.

Abstract: A method and apparatus for decoding a linear block encoded string of information bits comprising: converting the string into a plurality of codewords. Performing hard and soft decisions on each codeword to generate a hard and soft decision vector. Computing the syndrome and finding the location of the two minimum values by Galois Field Arithmetic. Designating these values LOW1 and LOW2 and xoring with a Nc1, thus generating Nc2. Swapping Nc1 with Nc2 and determining the lowest soft decision value, Min1 and a next lowest value, Min2. The two bit locations creating Min1 are designated as MinA and MinB. MinA being replaced with Min2 minus the value MinA. MinB being replaced with Min2 minus the value at MinB. Generating an output codeword by subtracting Min1 from all other bit locations values and 2's complementing all soft values with 0 in their location. Creating the new soft value vector.

Abstract: A syndrome assisted iterative decoder (173) uses iterative processing to decode an input sequence. A syndrome-assisted decoder (216), which may operate independently of a soft-output decoder, provides a stopping algorithm for the soft output decoder (240). When the syndromes s0 and s1 generated for sequence v0 and v1, respectively, both equal 0, the soft output decoder is finished decoding the sequence of data. Additionally, the syndrome-assisted decoder can generate a modified error trellis used by the soft output decoder whereby the soft-output decoder operates on a simplified trellis providing improved decoder performance.

Abstract: An error correction and detection technique provides a correction code for correcting single bit errors as well as detecting but not correcting two adjacent bits in error. A received word, which may contain errors, is multiplied by a parity check matrix to produce a syndrome corresponding to one of first and second mutually exclusive sets of syndromes if the received word contains at least one error, each single bit error in the received bit word corresponding one-to-one with a member of the first of the sets of syndromes and each two bit adjacent error corresponding non-uniquely to a member of the second of the sets of syndromes. A syndrome containing all zeros is produced if the received word contains no errors. One bit data errors in the received word are corrected, two bit errors are reported, and no action is taken if the word contains no errors.

Abstract: A coset analyzer is used for analyzing time-varying error correction codes in data communications. The time-varying error correction code has cosets, and each coset has a coset leader and a syndrome. The analyzer comprises a coset representation unit for representing a coset of the code as a time-varying error trellis and an error trellis searcher for searching the error trellis. Each member of the coset corresponds to a path through the error trellis. A lossless data sequence compressor and decompressor are also discussed.

Abstract: It is proposed to use channel coding involving a plurality of concatenated coders and decoders in series and in parallel for coded transmission in which the efficiency can be adapted as a function of the requirements of a system and an application. The coders of the invention are convolutional self-orthogonal code (CSOC) coders. It is shown that this enables perfect adaptation with circuits whose complexity and cost are low and which therefore support high bit rates.

Abstract: A method for decoding received data in a decoder which receives data from an encoder varying a length of a Walsh code according to a coding rate of transmission data, and has maximum IFHT (Inverse Fast Hadamard Transform) stages capable of decoding even the data encoded by a Walsh code with a maximum length. The method comprises selecting at least one IFHT stage among the maximum IFHT stages according to a length of the Walsh code used for the received data; and performing inverse fast Hadamard transform on the received data by the selected IFHT stage.

Abstract: Disclosed is method and apparatus for error code correction using product code. The method includes: (a) reading a data frame and associated check bytes from a media; (b) generating an error correction model for the data frame and associated check bytes, where the error correction model is defined by non-zero syndromes in the check bytes of Q dimension code words and P dimension code words of the data frame; (c) examining the generated error correction model; and (d) correcting the data frame using a combination of error correction systems that are selected based on the examining of the generated error correction model.

Abstract: A computation circuit for evaluating an error locator polynomial corresponding to a t-error correcting n-symbol code is described. In a first mode of operation, the computation circuit computes r syndromes in response to code word inputs. In a second mode of operation, the computation circuit is provided as inputs the coefficients of the error locator polynomial and evaluates the error locator polynomial for r location values in t+1 clock cycles. For each additional r location values, the inputs are the coefficients multiplied by a finite field element. The power of the finite field element is a multiple s of r. The value of the multiple s is initialized to one. After each next consecutive r location values are computed, sr+r is compared to n−1 and s is incremented prior to computing the next consecutive r location values if sr+1<n−1. If sr+r is ≧n−1, then no further computation of r location values is required.

Abstract: A self orthogonal decoding circuit and a method thereof, can be realized with simple circuit construction and can significantly improve error correction performance. The self orthogonal decoding circuit performing decoding for self orthogonal code repeats decoding for the self orthogonal code for a plurality of times.

Abstract: A stream of channel bits, of a signal relating to a binary channel, is decoded into a stream of source bits, of a signal relating to a binary source. This binary channel includes a main channel and a secondary channel. This secondary channel is embedded in the main channel. Errors in the stream of secondary channel bits are corrected using a stream of corrected main channel bits. This stream of corrected main channel bits is reconstructed from a stream of corrected source bits. The secondary channel can be embedded in the main channel in different manners, e.g. via multi-level coding or via merging-bit coding.

Abstract: A stopping criterion improvement for a turbo decoder that does not require division by a variable quantity. The stopping criterion improved upon generates a signal-to-noise ratio based on the mean and variance of soft-output estimates. The decoding process is aborted based on a comparison of the generated signal-to-noise ratio to a predetermined threshold.

Abstract: The present invention provides a method, computer medium, firmware, and device for minimizing memory requirements for computations for decoding using Maximum Likelihood Probability MAP-based decoding. The method includes the steps of: computing corresponding alpha &agr; values and beta &bgr; values simultaneously and storing in memory said alpha &agr; values and beta &bgr; values computed for &agr; at time k=1,2, . . ., N/2 and &bgr; at time k=N, . . . , (N/2)+1; and computing soft output data for alpha at time k=(N/2)+i and beta at time (N/2)−i+1, i being a positive integer, for N≧&agr;>N/2 and 1≦&bgr;≦N/2, wherein &agr; and &bgr; are parameter values computed by forward and backward recursion, respectively, based on transition probabilities of a selected channel and on input binary data at discrete time k and a parity bit corresponding to one of: a first recursive systematic convolutional encoder and a second recursive systematic convolutional encoder.

Abstract: The invention relates to a method of encoding a data block comprising first and second zones, the method being of the type consisting in applying product encoding to the block. It comprises first block encoding applied to the first zone, second block encoding applied to the second zone, and third block encoding applied to the data obtained by the first two encodings, but in a direction orthogonal to the first two codes, the three encodings being performed using BCH codes, the first zone being protected by a code that is more powerful than the second zone. The block is constituted by an ATM cell, the first zone corresponding to the header of the ATM cell, and the second zone corresponding to the payload data field of said ATM cell.

Abstract: An encoder and decoder for generating and decoding convolutional codes of improved orthogonality. In an exemplary embodiment the encoder includes a K-bit length shift register for receiving an input serial stream of information bits and providing for each input bit a K-bit parallel output to a self-doubly orthogonal code sequence generator. The encoded symbol stream is threshold decoded iteratively using the inversion of the convolutional self-doubly orthogonal parity code generators.

Abstract: The bits transmitted are coded according to the product of at least two systematic block codes. Iterative decoding is applied in order to determine, at each code word search step, a data matrix ({R}) and a decision matrix ({D}) used for the following step. The new decision matrix is determined at each step by decoding the lines or columns of the input matrix, and the new data matrix is determined taking into account the correction terms which increase the reliability of the decoding on each iteration. The coding and decoding circuits (17) are rendered programmable by a shortening technique allowing selection of the number k-X of non-redundant information bits per block to be coded. Known values are assigned to the other bits, the positions of which are uniformly distributed according to each dimension of the matrices.

Abstract: In a communication network, a method for channel quality estimation, without the need for a reference (uncorrupted) signal, comprises the steps of: processing a received signal utilizing a non-redundant error correction scheme to observe at least one symbol; producing an error signal in response to the observation; and counting a quantity of the error signal during a predetermined time interval to provide a symbol error count. A device for channel quality estimation, without the need for a reference (uncorrupted) signal, is also described.

Abstract: The bits transmitted are coded according to the product of at least two systematic block codes. Iterative decoding is applied in order to determine, at each code word search step, a data matrix ({R}) and a decision matrix ({D}) used for the following step. The new decision matrix is determined at each step by decoding the rows or columns of the input matrix, and the new data matrix is determined taking into account the correction terms which increase the reliability of the decoding on each iteration. The coding and decoding circuits (17) are rendered programmable by a puncturing technique allowing selection of the number of bits transmitted per coded block, the punctured bits preferably having uniformly distributed positions according to each dimension of the matrices.

Abstract: A method and apparatus decodes a data packet in a communication system utilizing an error correcting code. Channel symbols are received (302), and channel symbol reliability weights are determined (306) for each. A code word symbol is formed (308) from the channel symbols, and the channel symbol reliability weights are mapped (312) into a code word symbol reliability weight, which is set equal to the minimum channel symbol reliability weight mapped for the code word symbol. The method and apparatus continues (318) to similarly process additional channel symbols until the data packet is completely collected. Then, a predetermined number of code word symbols having the lowest code word symbol reliability weights in the data packet are marked (320) as erasures, after which the data packet is decoded (322) by utilizing a soft decision decoding technique.

Abstract: A novel circuit arrangement decodes Miller-squared (M.sup.2) encoded signals using Class II partial response (PR2) equalization techniques. The circuit arrangement utilizes a maximum-likelihood sequence estimator (detector) implemented by the Viterbi algorithm to minimize the probability of bit errors in a digital storage or transmission channel that employs M.sup.2 encoding in combination with PR2 equalization. The PR2 equalization channel is preferably modeled by a finite impulse response (FIR) filter which, in turn, is modeled by a finite-state trellis diagram. This allows creation of a modified trellis when M.sup.2 encoding is applied to the PR2 channel with the modified trellis providing the basis for implementing the detector according to the invention.