Fault-tolerant Routing (epo) Patents (Class 714/E11.011)
  • Patent number: 11502934
    Abstract: With the advent of manycore architecture, on-chip interconnect connects a number of cores, caches, memory modules, accelerators, graphic processing unit (GPU) or chiplets in one system. However, on-chip interconnect architecture consumes a significant portion of total parallel computing chip power. Power-gating is an effective technique to reduce power consumption by powering off the routers, but it suffers from a large wake-up latency to resume the full activity of routers. Recent research aims to improve the wake-up latency penalty by hiding it through early wake-up techniques. However, these techniques do not exploit the full advantage of power-gating due to the early wake-up. Consequently, they do not achieve significant power savings. The present invention provides a new router architecture that remedies the large wake-up latency overheads while providing significant power savings. The invention takes advantage of a simple switch to transmit packets without waking up the router.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 15, 2022
    Assignee: The George Washington Univesity
    Inventors: Hao Zheng, Ahmed Louri
  • Publication number: 20100306574
    Abstract: The processing load of a path control message on a node due to a link fault is reduced, a normal routing operation is assured, and the stable continuity of a network is realized. The node having received the path control message transmits the path control message to the adjacent node having transmitted the path control message and at least one or more adjacent nodes on an alternate path.
    Type: Application
    Filed: November 26, 2008
    Publication date: December 2, 2010
    Inventors: Takaaki Suzuki, Tomohiko Yagyu, Kazuya Suzuki
  • Publication number: 20100058147
    Abstract: Methods and apparatuses to model the relation between the delay samples and congestion losses and to protect media flows against congestion losses are disclosed. In one embodiment, the method comprises measuring congestion by delay samples, and performing a dynamic FEC algorithm that uses convex hull clustering for loss-event classification, including determining an FEC rate according to the loss-event classification. In another embodiment, the method comprises measuring congestion by delay samples, modeling loss events associated with the delay samples by grouping loss events as unions of convex hulls to identify a period of potentially increased congestion, dynamically changing the FEC rate based on the modeling, and applying FEC protection to the media flow during the period based on the FEC rate.
    Type: Application
    Filed: July 23, 2009
    Publication date: March 4, 2010
    Inventors: Hulya Seferoglu, Ulas C. Kozat, M. Reha Civanlar, James Kempf