Abstract: Apparatuses, methods, systems, and program products are disclosed for endpoint-based security. An apparatus includes a network module that is configured to receive, at an end user device, a request for content from a network source. An apparatus includes a policy module that is configured to compare a network source of requested content against a policy that is stored on an end user device prior to the content being allowed on the end user device. An apparatus includes an action module that is configured to replay at least one header of the request for content at a remote device where the requested content is further analyzed based on the comparison between the network source of the requested content and the policy.

Abstract: A critical data path of an integrated circuit includes a flip flop configured to receive a data input and provide a latched data output. A monitoring circuit includes a delay generator configured to receive the data input and provide a plurality of delayed data outputs corresponding to delayed versions of the data input with increasing amounts of delay, a selector circuit configured to select one of the plurality of delayed outputs based on a programmable control value, and a shadow latch coupled to an output of the selector circuit and configured to latch a value at its input to provide as a latched shadow output. A comparator circuit provides a match error indicator based on a comparison between the first latched data output and the latched shadow output, and an error indicator is provided which indicates whether or not an impending failure of the critical data path is detected.

Abstract: A memory circuit includes a first memory array and a second memory array. The first memory array and the second memory array are independent. The first memory array includes a plurality of general bits and the second memory array includes a plurality of spare bits. An address of defective bit in the first memory array is stored in the second memory array, and the memory circuit repairs the defective bit by one of the spare bits according to the address.

Abstract: A method is provided for checking invariants in parallel programs using dynamic instrumentation. Invariants are provided in the source code as conventional functions and can be activated or deactivated by a user. The program is instrumented prior to or during execution of the program to allow interception of an access to the main memory unit. The addresses of the memory locations on which an invariant is dependent are automatically recorded to allow a determination of changes to the addresses. A central data structure stores an invariant for each thread, associated memory address locations, and a Boolean value indicating whether the recording process is active. A corresponding library function is requested for each load command and each storage command via the instrumentation, records the respective addresses in the event of loading commands as long as the recording process is activated, and checks the respective invariants in the event of storage commands.

Abstract: An example implementation includes a system having one or more processors, a definition module, a data store, and a workflow module. The definition module is executable by the one or more processors to determine a first semantic element for a first operation included in a first application interface representing a first service and a second semantic element for a second operation included in a second application interface representing a second service, such as an enterprise service bus. The definition module may further determine a mapping of the first semantic element with the second sematic element. The data store is configured to store the mapping of the first semantic element with the second sematic element by the definition module. The workflow module is executable by the one or more processors to integrate the first application interface with the second service based on the mapping.

Abstract: Some embodiments provide an integrated circuit (“IC”) with a primary circuit structure. The primary circuit structure is for performing multiple operations that implement a user design. The primary circuit structure includes multiple circuits. The IC also includes a secondary monitoring structure for monitoring multiple operations. The secondary monitoring structure includes a network communicatively coupled to multiple circuits of the primary circuit structure. The secondary monitoring circuit structure is for analyzing the monitored operations and reporting on the analysis to a circuit outside of the IC.

Abstract: A connection switching device for an aircraft network includes a switching network and a second identification device. The switching network connects input/output devices, such that applications may be interconnected or such that an application may be connected to a peripheral device. The second identification device detects an input/output device that is connected to the connection switching device.

Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Abstract: A method for data storage includes receiving in a memory device data for storage in a group of analog memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.

Abstract: Systems, methods, and apparatuses for error checking are disclosed. In one embodiment, an error checking system is used on a device that has a plurality of parallel data lanes as inputs. It may be desired to provide an error checking system with sufficient resolution to detect single-bit errors, determine how many bits are in error, and/or determine which bit(s) of a parallel data lane are in error. In one embodiment, the present disclosure provides for switchable error checking through the use of a multiplexor configured to select a particular data lane for error checking. This switchable error checking may provide benefits such as low cost, low power consumption, and/or low size.

Abstract: Selection of a minimum voltage and/or maximum clock frequency in an integrated circuit is described. Selection of the minimum voltage and/or maximum clock frequency is accomplished by generating a timing error prediction signal and a timing error detection signal in a timing error module that is placed in a critical path in the integrated circuit.

Abstract: A method for integrity checking for a cryptographic engine in a computing system includes monitoring a state of a side channel of the cryptographic engine during operation of the cryptographic engine by a side channel monitor; comparing the state of the side channel to a side channel model of the cryptographic engine to determine whether a mismatch exists between the state of the side channel and the side channel model; and based on a mismatch between the state of the side channel and the model of the side channel, indicating an error in the cryptographic engine.

Abstract: Various systems and methods for media defect detection.

Abstract: Embodiments relate to multi-contact sensor devices and operating methods thereof that can reduce or eliminate offset error. In embodiments, sensor devices can comprise three or more contacts, and multiple such sensor devices can be combined. The sensor devices can comprise Hall sensor devices, such as vertical Hall devices, or other sensor types in embodiments. Operating modes can be implemented for the multi-contact sensor devices which offer significant modifications of and improvements over conventional spinning current principles, including reduced residual offset.

Abstract: A processor includes a store queue that stores information representing store instructions. In response to retirement of a store instruction, the processor invalidates the corresponding entry in the store queue, thereby indicating that the entry is available to store a subsequent store instruction. The store address is not removed from the queue until the subsequent store instruction is stored. Accordingly, the store address is available for comparison to a dependent load address.

Abstract: A system, and in particular a system operating in real-time, may have its operation rely on a particular sequence of trigger signals, hardware or software, for proper operation. A trigger sequence checker provides a way to monitor in real-time predetermined sequences of triggers and is configured to generate an error signal upon detection of a faulty operation or sequence. Rules for sequences of triggers are stored in memory and are used by the trigger sequence checker to verify one or more sequences of triggers received as an input to the checker. A plurality of triggers may be handled by the checker. In one embodiment the checker is configurable to be set in a learning mode to capture triggers rules.

Abstract: Arbitrating node failures. A method includes determining at a first node that communication to a second node has been lost. The method further includes sending an arbitration request to a plurality of arbitrators. The method further includes receiving from the plurality of arbitrators a sufficient number of arbitration reply grant messages to have arbitration reply grant messages from a quorum of the arbitrators. As a result of receiving a sufficient number of arbitration reply grant messages to have arbitration reply grant messages from a quorum of the arbitrators, the method further includes declaring the second node down.

Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.

Abstract: Embodiments of the inventions are related to systems and methods for data processing, and more particularly to systems and methods for mitigating trapping sets in a data processing system.

Abstract: The present invention is related to systems and methods for adaptive parameter modification in a data processing system.

Abstract: Systems and methods are provided for detecting an anomaly in a computer that is part of a population of networked computers. Snapshots are received from a plurality of computers within the population of computers, where individual snapshots include a state of assets and runtime processes of a respective computer. An asset normalization model is generated from the snapshots and serves as a baseline model for detecting an anomaly in the state of assets and runtime processes of a respective computer. A snapshot from at least one of the computers is compared to the asset normalization model in order to determine whether an anomaly is present in a state of static assets and runtime processes of the at least one of the computers.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for selectable positive feedback data processing.

Abstract: An extremum seeking control method optimizes a control process for a plant such as an air handling unit. The method compensates for abrupt changes in the operation of the plant by resetting the extremum seeking control strategy in response to a detection of the abrupt change.

Abstract: A useful embodiment of the invention is directed to a method associated with a computer program comprising one or more basic blocks, wherein the program defines and uses multiple data structures, such as the list of all customers of a bank along with their account information. The method includes identifying one or more invariants, wherein each invariant is associated with one of the data structures. The method further includes determining at specified times whether an invariant has been violated. Responsive to detecting a violation of one of the invariants, the detected violation is flagged as an anomaly.

Abstract: A useful embodiment of the invention is directed to a method associated with a computer program comprising one or more basic blocks, wherein the program defines and uses multiple data structures, such as the list of all customers of a bank along with their account information. The method includes identifying one or more invariants, wherein each invariant is associated with one of the data structures. The method further includes determining at specified times whether an invariant has been violated. Responsive to detecting a violation of one of the invariants, the detected violation is flagged as an anomaly.

Abstract: An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.

Abstract: Disclosed herein are systems, methods, and non-transitory computer-readable storage media for using an intermediate database management layer to manage communications between an application layer and a database layer. The database management layer can receive an initial communication from the application layer and transmit a subsequent communication to a particular database based upon a rule. The rules can specify the particular database based upon the initial communication and an availability status of the database. The rules specify criteria by which the initial communication is identified and logic specifying the particular database to receive the subsequent communication based upon the identification of the initial communication.

Abstract: The present inventions are related to systems and methods for information divergence based data processing.

Abstract: Improved flaw scan circuits are provided for repeatable run out data. RRO (repeatable run out) data is processed by counting a number of RRO data bits detected in a servo sector; and setting an RRO flaw flag if at least a specified number of RRO data bits is not detected in the server sector. The RRO flaw flag can also optionally be set by detecting an RRO address mark in the servo sector; counting a number of samples in the servo sector after the RRO address mark that do not satisfy a quality threshold; and setting the RRO flaw flag when the counted number of samples that that do not satisfy the quality threshold exceeds a specified flaw threshold. If the RRO flaw flag is set, the RRO data can be discarded, and/or an error recovery mechanism can be implemented to obtain the RRO data.

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection.

Abstract: Methods and structure for enhanced SAS expander functionality to store and forward buffered information transmitted from an initiator device to a target device and to process errors in control circuits of the expander without intervention from the general purpose programmable processor of the expander. A PHY of an expander is associated with control circuits that comprise buffering of commands to be forwarded to an end device directly coupled to the PHY. The control circuits locally process errors detected from the end device. The control circuits comprise a SATA host circuit adapted to communicate with a SATA end device to detect and clear error conditions and a SATA target circuit to communicate with one or more STP initiator devices to report and clear error conditions reported by the end device. The structures and methods may also service SAS connections (in addition to STP connections).

Abstract: Various embodiments of the present invention provide systems and methods for media defect detection.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing with soft guaranteed global processing iterations.

Abstract: Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.

Abstract: Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold.

Abstract: Some aspects of the disclosure relate to automated quality control of a media asset. The quality control can comprise testing automatically various facets of content reproduction. In one embodiment, three facets can be tested: (1) access to a rendering unit configured to reproduce content of the media asset; (2) rendering of at least a portion of visual content of the media asset; and (3) rendering at least a portion of the aural content of the media asset. In one aspect, testing the rendering of the visual content can be differential in that features of the rendering can be monitored at a plurality of instants during content reproduction and can be compared for two or more instants of the plurality of instants. In another aspect, based on the comparison, the media asset can be deemed to pass the quality control and thus be accepted for consumption.

Abstract: Method, computer program product, and system for performing an operation to maintain data integrity in a parallel computing system, the operation comprising providing a lookup table specifying a plurality of predefined destinations for data packets, receiving a first data packet comprising a destination address specifying a first destination, wherein the first data packet has an error of a first type, identifying, from the lookup table, an entry specifying a second destination for data packets having errors of the first type, and sending the first data packet to the second destination to avoid corrupting the first destination.

Abstract: A method, control module and system of a vehicle including at least a first and a second control computer each containing a number of local Digital Control Modules and at least one Actuator Control Module wherein the Actuator Control Module of each control computer is operatively connected to all local Digital Control Modules of the same control computer, wherein the Actuator Control Module of each control computer is further operatively connected to all Digital Control Modules of the electrical system in a manner that enables each Actuator Control Module of the system to receive internal data of each Digital Control Module of the electrical system.

Abstract: Embodiments relate to systems and methods for detecting register corruption within CPUs operating on the same input data enabling non-invasive read access to and comparison of contents of at least one set of according ones of registers of different CPUs to detect corrupted registers in form of according registers with inconsistent contents.

Abstract: A technique for detecting an imminent read failure in a non-volatile memory array includes applying a bulk read stress to a plurality of cells of the non-volatile memory array and determining whether the plurality of cells exhibit an uncorrectable error correcting code (ECC) read during an array integrity check at a margin read verify voltage level subsequent to the bulk read stress. The technique also includes providing an indication of an imminent read failure for the plurality of cells when the plurality of cells exhibit the uncorrectable ECC read during the array integrity check. In this case, the margin read verify voltage level is different from a normal read verify voltage level.

Abstract: The present description refers to a technique for receiving a client instruction, performing an action in response to the client instruction, generating an instance of a progress information message by the business object calling a first method of an API and identifying the progress information message to be generated, determining if an error condition occurs during the performing the action, generating an instance of an error message, if the error condition occurs, by calling the first method of the API, sending the progress information message instance from a second software work process to the client application in response to a request for progress information received by the second software work process from the client application, and sending the error message instance, if generated, from the first software work process to the client application.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to read or write performance of a phase change memory.

Abstract: Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors.

Abstract: A data storage system configured to manage unreliable memory units is disclosed. In one embodiment, the data storage system maintains an unreliable memory unit list designating memory units in a non-volatile memory array as reliable or unreliable. The unreliable memory unit list facilitates management of unreliable memory at a granularity level finer than the granularity of a block of memory. The data storage system can add entries to the unreliable memory unit list as unreliable memory units are discovered. Further, the data storage system can continue to perform memory access operations directed to reliable memory units in blocks containing other memory units determined to be unreliable. As a result, the operational life of the data storage system is extended.

Abstract: Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.

Abstract: The present invention is related to systems and methods for maintaining additional processing information during extended delay processing.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for coasting one or more calibration loops based upon identification of a probability of data inaccuracies.

Abstract: Techniques are described for detecting faults in media content based on the behavior of users viewing the media content. Embodiments stream a first instance of media content to one or more users. The behavior of the one or more users is monitored while the users are viewing the streaming first instance of media content. Embodiments then determine whether the first instance of media content is faulty, based on the monitored behavior of the one or more users.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, data processing systems are disclosed that include a data decoding circuit having a data decoder circuit, an element modification circuit, an element modification log, and a mis-correction detection circuit.

Abstract: The present disclosure relates to some aspects relate to a method for detecting stack memory corruption. In some embodiments, the method comprises determining an expected memory range of a data element that is to be written to a stack memory by tracking changes to a stack pointer. The determined memory range is stored in a stack object database. Upon receiving a stack memory access related instruction (e.g., LOAD/STORE instruction or arithmetic instruction operating on memory addresses) to write data to the stack memory, an address of the memory location to be accessed is determined. If the address falls within the expected memory range, no stack corruption is present. However, if the address falls outside of the expected memory range, stack corruption is present. Therefore, the present method provides for real time detection of corruption (e.g., overrun and underrun errors) in stack memory.