Abstract: A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or a user command. When executed, the diagnostic procedure automatically checks for integrity of one or more portions of data in the computer, to identify any failure(s). In some embodiments, the failure(s) may be displayed to a human, after revalidation to exclude any failure that no longer exists.

Abstract: A method and system are provided for determining an imminent failure of a non-volatile memory array. The method includes: performing a first array integrity read of the memory array until an error is detected; determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage; performing a second array integrity read of the memory array until all bits of the memory array indicate a predetermined state, wherein a second word line voltage associated with all of the bits indicating the predetermined state is a second threshold voltage; and comparing a difference between the first and second threshold voltages to a predetermined value.

Abstract: A versioned workload partition (WPAR) can be migrated from a source machine to a destination machine. Each thread associated with a process executing within the versioned WPAR is frozen. For each thread associated with the process, an error number associated with the thread is received in response to freezing execution of the thread and at least a current state of the thread is determined as checkpoint information associated with the thread based, at least in part, on the error number associated with the thread. The checkpoint information associated with the one or more threads is provided to the destination machine. The checkpoint information is used at the destination machine to reconstruct the process within a destination versioned WPAR on the destination machine.

Abstract: A semiconductor apparatus includes an arithmetic circuit that executes a program based on an operating clock signal input through a clock transfer node, an internal oscillator that generates an internal clock signal to be used internally, a watch dog timer that counts the internal clock signal, detect that a count value reaches a predetermined value of an execution time of the program in the arithmetic circuit and output a notification signal, and a clock monitor circuit that detects presence or absence of the operating clock signal in response to the notification signal.

Abstract: Safe operation in a processor may be verified by making use of an execution trace module that is normally only used for testing and software development. During operation of the processor in the field, a sequence of instructions may be executed the processor. A portion of the execution is traced to form a sequence of trace data. The sequence of trace data is compressed to form a checksum. The checksum is compared to a reference checksum, and an execution error is indicated when the checksum does not match the reference checksum.

Abstract: Methods and communication systems are presented, in which impulse noise is monitored on a communication channel, and impulse noise protection parameters are adjusted according to the monitored impulse noise without interrupting communication service.

Abstract: A method and apparatus for detecting split brain in a distributed system is provided. After determining that a rogue instance is no longer an active member of the cluster, a recovery instance detects activity associated with a redo log that is updated by the rogue instance to store log records that describe changes made by the rogue instance to data associated with the cluster.

Abstract: Various methods for implementing delta data storage, for example, within a hybrid automatic repeat request (HARQ) buffer, are provided. One example method includes receiving a redundancy version including a plurality of redundancy version bits and soft combining the redundancy version bits with corresponding buffered bits to generate corresponding soft combined bits. The example method further includes comparing the soft combined bits with the corresponding buffered bits to identify changed bits and unchanged bits, storing the changed bits in a buffer to thereby replace the buffered bits that correspond to the changed bits. Similar example apparatuses are also provided.

Abstract: An integrated circuit is interfaced with at least one dynamic random access memory (DRAM) via a memory interface. A plurality of user test options are received. The testing of the memory interface is controlled in accordance with the plurality of user test options. Test data, generated as a result of the testing of the memory interface, is stored.

Abstract: Problem isolation in a virtual environment is described. In one example, a method is disclosed which includes maintaining a topology of network devices in a virtual environment in a performance management database hosted on a problem isolation server. The network devices can be monitored for metrics breaching a baseline. A snapshot of portions of the topology associated with the metrics breaching the baseline can be captured using a snapshot module. The snapshot captured can include a partial topology. Time stamps associated with the metrics can be maintained. The time stamps can include time stamps for when the metrics breach the baseline. The time stamps can be correlated with the snapshot to form a problem isolation timeline.

Abstract: Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to techniques for accurately determining a number of data symbols in a data packet. The techniques provided herein may allow a receiving terminal to correct number of symbol calculations based on such ambiguous length field values.

Abstract: A memory system including a primary memory storage partition, a secondary memory storage partition, and a memory controller that is connected to read and write to the primary memory storage partition and detect a permanent bit error at an address associated with the primary memory storage partition. In response to a detected permanent bit error, the memory controller stores data from the address associated with the permanent bit error to an address associated with the secondary memory storage partition.

Abstract: A method and system dynamically configures faults during software testing. During runtime of a service platform, a computer system hosting the service platform receives a request from a test program to register a list of controllers. Each of the registered controllers controls the generation of a different fault. The test program triggers the execution of a service to be tested on the service platform. During execution of the service, a predefined condition is encountered. A fault is generated if one of the registered controllers controls the fault generation associated with the predefined condition. Based on the generation of the fault, the behavior of the service can be verified.

Abstract: The present disclosure is directed to network communication between a sender and a receiver. Network communication is established between the sender and the receiver using a first acknowledgment mechanism for signifying receipt of data by the receiver. The first acknowledgment mechanism is selected from one of a receiver positive acknowledgment mechanism (RPA) and a receiver negative acknowledgment mechanism (RNA). Communication information is monitored, wherein the communication information indicates at least a current state of performance for network communication. Based on the communication information, a message is exchanged between the sender and the receiver to negotiate a switchover to a second acknowledgment mechanism for signifying receipt of data by the receiver. The second acknowledgment mechanism is selected from the other of the receiver positive acknowledgment mechanism (RPA) and the receiver negative acknowledgment mechanism (RNA).

Abstract: A method and system is provided for measuring, guaranteeing, and reducing replication data lag time between a primary system and one or more standby systems. Each standby system determines the lag time between the generation of a consistent version of data on the primary system and the time that the consistent version is applied on the standby system. Applications can request and be guaranteed to receive data from a standby system that is identical to the state on the primary system at the time of the query, or lag the primary state only by a maximum tolerable amount. A standby system may also publish a service that guarantees a maximum lag time and withdraw the service offer when the actual lag time exceeds the guaranteed lag time. Implications for implementing synchronous and asynchronous replication as well as performance optimizations are also discussed.

Abstract: A method of transmitting computational data comprising: a step of generating first computational data and generating first generated data using a first generation algorithm for error detection on return; a step of generating second computational data and generating second generated data using a second generation algorithm for error detection; a step of mutually comparing the first/second computational data; a step of transmitting transmission data including coincident computational data and first/second generated data; in the receiving device, a step of generating computational data and third/fourth generated data from preset first/second generation algorithms; and a step of comparing the first/third generated data and the first/third generated data, and detecting error in the received computational data.

Abstract: In a particular embodiment, a method of monitoring interrupts during a power down event at a processor includes activating an interrupt monitor to detect interrupts. The method also includes isolating an interrupt controller of the processor from the interrupt monitor, where the interrupt controller shares a power domain with the processor. The method also includes detecting interrupts at the interrupt monitor during a power down time period associated with the power down event.

Abstract: Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.

Abstract: One processor core of a plurality of processor cores that are included in a multi-core processor that processes a request from an external device detects a prescribed event, specifies a sub resource that is assigned to the one processor core based on the resource management information that indicates a sub resource of a plurality of sub resources that are included in a physical resource and a processor core that is assigned to the sub resource, and executes a reboot based on the specified sub resource.

Abstract: A method for a network device to access a packet switched network is applied to a system in which the network device accesses the packet switched network by connecting to PEs in an active-standby mode. The method includes: an active PE and a standby PE each sends a fault detection message to the network device through an interface connected to the network device; the active PE sets the state of the interface “up” and advertises a route to a remote PE if a fault detection response returned by the network device is received through the interface within a preset period; otherwise, the active PE sets the state of the interface to “down” , and withdraws the advertised route; and the standby PE sets the state of the interface to “up” and advertises another route to the remote PE after receiving a fault detection response through the interface connected to the network device.

Abstract: Embodiments are directed to establishing the integrity of a portion of data on at least one level of a plurality of network stack levels and automatically continuing an established federation relationship between at least two federation computer systems. In an embodiment, a first federation computer system receives a digital signature corresponding to a computer system signed by a digital signature which includes the computer system's identity and other federation relationship information configured to establish a trusted federation relationship between a first federation computer system and a second federation computer system. The first federation computer system attempts to validate the received digital signature at a first level of a network stack and determines that the validation at the first network stack layer was unsuccessful. The first federation computer system then validates the received digital signature at a second, different level of the network stack.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.

Abstract: A trace output unit for collecting, buffering and outputting trace data generated by trace circuitry monitoring processing activities of a data processing apparatus is described. The trace output unit comprises an input for receiving a stream of trace data; a plurality of data stores arranged in parallel with each other for storing the trace data; and storage control circuitry for controlling storage of items of the trace data in the data stores. The control circuitry is configured to route the trace items to selected ones of the data stores and to store control data identifying related trace items stored in different data stores. The trace output unit further comprises output control circuitry configured to identify related trace items stored in different data stores from the stored control data and to recombine the related trace items from different data stores to form an output trace data stream.

Abstract: Performance information which is a possible generation cause of a fault is extracted accurately. A fault cause extraction apparatus 10 includes a storage unit 12 and a correlation-destruction-propagation detecting unit 25. Here, the storage unit 12 stores a correlation model including one or more correlation functions, each of which is generated based on a time series of performance information including a plurality of types of performance values in a system and transforms a performance value for one of the types being an input to a performance value for another one of the types being an output.

Abstract: As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

Abstract: Systems and methods are disclosed for automated notification systems. A representative system, among others, can be summarized as follows. A host computer system, or base station, is designed to monitor travel data corresponding to a mobile thing and to initiate a notification communication to a personal communications device (PCD) indicating travel status of the mobile thing (MT) to a remote computer system. The remote computer system, within or associated with the PCD, is designed to detect a failure to receive the notification communication and to cause one or more tasks to be performed based upon the notification communication failure.

Abstract: A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

Abstract: In a method of data processing within a controller ensuring that voting operations are reliably performed error free and in a corresponding controller unit, the input data are characteristic for the particular application where voting occurs. Voting whether or not the incoming data is correct involves a voting comparison method, a voting average method, and checking for a difference being within a certain range. The time dependent signature indicates correctly transmitted input data. Voting, based on the reviewed signature characteristics is an encoded operation. The time dependent signature indicates the data is coming from a correct source, has been a modification, and correct timing slides. Voting whether or not the incoming data is correct is performed in an encoded manner. A correct data is transmitted to be further used to actuate an actuator. The erroneous data is transmitted to be further sent to a fail safe guard.

Abstract: Provided are a method, system and program for batching transactions to apply to a database. A transaction manager receives a plurality of transactions to apply to a database and adds the transactions to a work queue. One of a plurality of agents processes a batch of transactions from the work queue. Each agent executes a batch of transactions from the work queue against the database independent of the operations of other of the agents executing batches of transactions. The agent applies the transactions in the batch against the database and commits the transactions in the batch to the database in response to completing all of the transactions.

Abstract: An information processing apparatus receives a request transmitted from a client to a server and a response transmitted from the server to the client. The information processing apparatus includes a processor. The processor counts a first number of first requests having no corresponding response within a first time period, counts a second number of second requests having a corresponding response, and detects a failure in the server on the basis of the first number and the second number.

Abstract: Apparatus and methods are provided that prevent cross-site request forgery at one or more web servers. A proxy dynamically monitors web server responses to client requests for content having a selected characteristic, adds a hidden token to content identified as having the selected characteristic prior to serving the content to a requesting client, and stores a copy of the hidden token for later verification that client request content sent to a web server is authentic. The proxy monitors client request content sent to the one or more web servers for a selected characteristic, and allows client request content having the selected characteristic to be processed by a web server application only if the client request content includes a token previously provided by the proxy and only if the token has a value matching a stored token value for the respective client.

Abstract: According to one embodiment, a memory control device includes a first controller, a second controller, an access module, and a response sort module. The first controller controls processing of a data access command to a nonvolatile memory from a host. The second controller controls processing assigned to the second controller between the first controller and the second controller. The access module performs data access to the nonvolatile memory in response to a command from the first controller or the second controller. When an error occurs in the data access by the access module, the response sort module returns a response to the second controller instead of the first controller.

Abstract: A computer program product is provided for performing a method including: receiving transmission data over a selected time interval for each of a plurality of communication paths; calculating an average round-trip transmission time for each of the plurality of communication paths over the time interval; comparing an average round-trip transmission time for a communication path having the highest average round-trip transmission time to a threshold value and to a multiple of an average round-trip transmission time for a communication path having the lowest average round-trip transmission time; and determining, based on a result of comparing the highest round-trip transmission time to the threshold value and to a multiple of the lowest round-trip transmission time, whether the time period indicates a delay in communication between the I/O subsystem and the control unit requiring at least one of a monitoring action and a recovery action.

Abstract: A method for analyzing fault modes that may cause a fault is presented in which a multi-point analysis may be performed to identify multi fault modes that are interrelated in causing the fault. The method provides for easy and systematic switching from a top-down to bottom-up approaches of analysis to insure accurate and easy to perform multi-point analysis of the related fault modes.

Abstract: A communication monitoring apparatus that is capable of preventing determination of communication error due to communication shutdown accompanying the communication speed change so as not to inspire a user with unnecessary uneasiness. The communication monitoring apparatus monitors a connecting condition of communication between a terminal that can change a communication speed and a host apparatus through a network. A check unit periodically checks whether the connecting condition of communication between the terminal and the host apparatus through the network is normal or abnormal at first set time, and determines that a communication error occurs when the checked result shows abnormal connecting condition. A control unit detects a communication speed change in the terminal, and stops the check by the check unit before the communication speed change concerned.

Abstract: Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: The present invention discloses a method for error connection and error prevention of service in an Automatically Switched Optical Network (ASON), to resolve the technical problems that the conventional method for error connection and error prevention cannot realize rapid automatic configuration and the efficiency is low and other problems. Through automatically completing the configuration of the error connection and error prevention information of the start node and the end node by the control plane, the present invention overcomes the defect that manual setting is error prone; it is rapid and simple to implement the interaction of the error prevention information between the start node and the end node by protocol exchange.

Abstract: A testing method for a server supporting an intelligent platform management interface (IPMI) is applied to test a server before an operating system (OS) of the server operates. The test method includes the following steps. A baseboard management controller (BMC) of the server is activated. The server is activated, and a monitoring module is operated. Real-time status data of the server stored in the BMC of the server is obtained. The monitoring module executes a pre-test procedure according to the real-time status data of the server before the OS operates. A test result of the pre-test procedure is stored.

Abstract: A method and apparatus are provided for performing cross-host root cause diagnosis within a complex multi-host environment. In a multi-host environment, sometimes system failures on one host may cause problems at another host within the same environment. A probabilistic model is used to represent failures that can occur within each host in the environment. The cause and effect relationships among these failures together with measurement values are used to generate a probability that each potential failure occurred in each host. When a problem is observed on one host without detecting a corresponding root cause within the same host, a cross-host failure diagnosis is performed. The probabilistic models for other hosts in the environment are used to determine the most likely cause of the failure.

Abstract: In an encoded stream decoding device, a storage amount checking circuit confirms that a sufficient amount of stream has been stored in a buffer circuit. Thereafter, a control circuit starts repeatedly outputting a control signal to a decoding circuit to instruct the decoding circuit to perform a variable-length decoding process. If, by iterating the decoding process, the total amount of a consumed stream in the buffer circuit 11 is caused to be higher than or equal to a threshold set in a threshold setting circuit, a disabling circuit generates a decoding disable signal having a value of “1,” and outputs the decoding disable signal to the control circuit. When receiving the decoding disable signal, the control circuit outputs, to the decoding circuit, a control signal for instructing to stop the decoding process, so that the decoding circuit stops the decoding process.

Abstract: Tools for use in obtaining useful information from processed log messages generated by a variety of network platforms (e.g., Windows servers, Linux servers, UNIX servers, databases, workstations, etc.). The log messages may be processed by one or more processing platforms or “log managers” using any appropriate rule base to identify “events” (i.e., log messages of somewhat heightened importance), and one or more “event managers” may analyze the events to determine whether alarms should be generated therefrom. The tools may be accessed via any appropriate user interface of a console that is in communication with the various log managers, event managers, etc., to perform numerous tasks in relation to logs, events and alarms.

Abstract: One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which the certain storage device is connected, and when command transmission fails while transmitting a command from a kth switch (k is an integer of 0 or more) which is connected to a (k+1)th switch and is one level upstream of the (k+1)th switch or from any port of the controller portion, it is determined that a failure has occurred in a power source that supplies power to the (k+1)th switch.

Abstract: A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.

Abstract: A sniffer device determines whether an abnormal condition is present in a network communication. In response to determining that the abnormal condition is present, the sniffer device collects network-level packets into a data structure. The data structure containing the collected network-level packets can be analyzed for determining whether the abnormal condition caused an issue with a communicating entity.

Abstract: A fault detection system for detecting a fault in a process system includes a first circuit configured to modify an input of the process system with a modifying signal. The fault detection system further includes a second circuit configured to receive an output from the process system and configured to determine whether the fault exists based on at least one of a reduction of a signal component and an unexpected transformation of the signal component, wherein the signal component corresponds to a function of the modifying signal.

Abstract: A system for implementing scalable input/output (I/O) function level error detection, isolation, and reporting, the system comprising, an I/O hub communicatively coupled to a computer processor, system memory and at least one I/O adapter, the at least one I/O adapter include a function and the I/O hub including logic for implementing a method. The method comprising detecting an error in a communication initiated between the function and the system memory, the communication including an I/O request from an application. The method further comprising preventing future communication between the one function and the system memory in response to the detecting. The method additionally comprising notifying the application that the error in communication occurred in response to the detecting.

Abstract: A method for driving an electronic device stably is provided. The electronic device includes a power supply circuit to which power is fed by power sequentially supplied from a contactless power feeding device, and a plurality of loads to which power is sequentially supplied from the power supply circuit. Further, a method for driving an electronic device stably is provided. The electronic device includes a power supply circuit to which power is fed by power supplied from a contactless power feeding device, and one or more loads to which the power supply circuit repeatedly supplies power. The power supply potential Vdd is restored to more than or equal to 90% of the initial potential Vdd0 within an interval in which the power supply circuit is not connected to a load; then, the next load may be connected to the power supply circuit, and may be driven.

Abstract: According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

Abstract: Detection, notification and/or processing of events, such as errors associated with adapters, are facilitated. Hardware detects an event, places one or more adapters in an error state to prevent access to/from the adapters, and notifies the operating system of the event.

Abstract: Systems, methods, and other embodiments associated with shared error searching for web resource requests are described. A web resource request that includes one or more request strings is received and a error detection directive that identifies a first type of error to be located in a specified request string component is accessed. At least a portion of a first request string that corresponds to the specified request string component is searched, in a single pass, for the first type of error and other types of errors. Results with respect to the first error type are returned while occurrences of the first and other types of errors for are recorded for responding to subsequent error detection directives. Thus, a subsequent error detection directive for the other types of errors in the first request string component may be processed without re-searching the portion of the first request string already searched with respect to the first error detection directive.