Abstract: Improving the performance, life and amount of data storage in write limited non-volatile memory may be achieved by: a) utilizing a serial content-addressable memory (CAM) to perform logical address translation, b) a minimum CAM function to perform erase error count wear leveling, c) increasingly refining a two dimensional error-correction coding (ECC) method as needed to correct for degrading storage, and/or d) serially generating ECC and using an ECC serial decoder to correct the data.

Abstract: The present disclosure includes apparatuses and methods related to updating reliability data. A number of methods can include receiving, at a variable node, either a first reliability data value with a first hard data value or a second reliability data value with a second hard data value, sending the first hard data value or the second hard data value to each check node coupled to the variable node according to a parity check code, and updating the reliability data based on input from less than all of the check nodes.

Abstract: Embodiments may communicate via an electromagnetic radiator, or light source, that can be amplitude modulated such as light emitting diode lighting via receivers that can determine data from light received from the radiator. Some embodiments decode data of a packet transmitted from modulated lighting by means of a device with a low sampling frequency such as a relatively inexpensive camera. Many embodiments determine locations of start frame delimiters in packets. Several embodiments implement repeat decoding on packets of the same data to reduce packet error rates. Some embodiments are intended for indoor navigation via photogrammetry using self-identifying light anchors. In many embodiments, the data signal may be communicated via the light source at frequencies causing flicker that is not perceivable to the human eye.

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract: A method and a circuit for generating cyclic redundancy checks. The method calculates a plurality of cyclic redundancy checks for a transport block with a plurality of information bits. At least one cyclic redundancy check among the plurality of cyclic redundancy checks is calculated based on a subset of information bits, and at least one information bit among the plurality of information bits is not within said subset of the information bits. In addition, a transport block cyclic redundancy check may be calculated based on all the information bits.

Abstract: According to the present invention, a computing unit abnormality determining apparatus is disclosed which determines whether there is an abnormality in a computing unit, comprising a comparison operation abnormality determining part configured to perform a comparison operation using the computing unit to determine whether there is an abnormality in the comparison operation; and an arithmetic/logical operation abnormality determining part configured to perform an arithmetic/logical operation of a predetermined operational expression using the computing unit, the predetermined operational expression including at least one of an arithmetic operation and a logical operation, and compare an operational result obtained by the arithmetic/logical operation with a corresponding stored value of a correct value to determine whether there is an abnormality in the arithmetic/logical operation.

Abstract: The subject matter disclosed herein provides an outer coding framework for minimizing the error rate of packets. In one aspect, the method may include determining, based on a cyclic redundancy check, a first erasure table including zero or more erasures; determining a second erasure table; using the first erasure table to locate errors in a frame of packets, when the zero or more erasures of the first erasure table do not exceed a threshold of erasures; and using the second erasure table to locate errors in the frame of packets, when the one or more erasures of the first erasure table do exceed the threshold of erasures. The frame may include the one or more rows encoded using the outer code. The block that is read may be provided to enable an inner code to encode the block before transmission. Related systems, apparatus, methods, and/or articles are also described.

Abstract: A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.

Abstract: A method includes detecting that a first device in a memory array has degraded, the first device storing a portion of a data record, wherein the data record is encoded using a first error control technique. The method continues with recovering the data record using portions of the data record stored in devices other than the first device in the memory array and encoding the data record using a second error control technique. The method also includes storing the data record in the devices of the memory array other than the first device.

Abstract: An error correction code decoding device comprises a first memory having a memory space like a matrix, a first decoding unit writing a first information into the first memory along a first direction, a second decoding unit reading the first information from the first memory along a second direction and a plurality of turbo decoders included in the second decoding unit, and differentiating access timing to a same row or same column with each other.

Abstract: A data storage device includes an interface that is configured to interface with a host, a command bus, multiple memory devices that are operably coupled to the command bus and a controller that is operably coupled to the interface and to the command bus. The controller is configured to receive a copy command from the host using the interface, read data from a source memory device in response to the copy command, write the data to a destination memory device in response to the copy command and communicate results to the host using the interface.

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Abstract: Processing a sequence of data frames in an error correction code (ECC) decoder is disclosed. Processing includes receiving a first data frame in the sequence of data frames, storing the first data frame, initiating processing of the first data frame through the ECC decoder, receiving a second data frame from the input sequence of data frames, storing the second data frame, and initiating processing of the second data frame through the ECC decoder before the first data frame is finished being processed through the ECC decoder.

Abstract: A communicating unit used in an X-ray image pickup apparatus in this invention has an error detecting function to detect communication errors, and an FIFO for temporarily storing data received from a control and image processing apparatus, which is an external apparatus, by a receiving function of a communication control unit. Only when no error is detected within a predetermined period before and after receipt of data, by the receiving function of the communication control unit, from the control and image processing apparatus, a transmitting function of the communication control unit performs controls to transmit and write the data received and temporarily stored in the FIFO to an external portion. Thus, when a cable is plugged or unplugged or the control and image processing apparatus which is an external apparatus is rebooted, the error detecting function detects this as a communication error. In such cases also, an inadvertent writing of the data can be prevented.

Abstract: An encoding device includes an encoder and a puncturing unit. The encoder generates parity bits based on information bits. The puncturing unit punctures the parity bits based on a puncturing pattern complying with a first criterion determining a period of the puncturing pattern and a second criterion determining positions of remaining parity bits.

Abstract: A lighting system controller is provided that is configured to automatically synchronize a lighting controller with a centralized configuration. In a particular example, this automatic synchronization activity may include modifying the configuration of the lighting controller to match configuration information stored locally on the lighting system controller. Conversely, this automatic synchronization activity may include modifying the locally stored configuration information to match the current configuration of the lighting controller. In some examples, the lighting system controller is configured to use cyclic redundancy checks when determining whether to modify configuration information.

Abstract: Architecture, system and method for providing compression of repair data in an IC design having a plurality of memory instances. In one embodiment, the repair data storage method includes determining repair data for each of the memory instances and compressing the repair data into a compressed format that is stored in a shared nonvolatile storage common to the memory instances.

Abstract: A complementary error evaluator polynomial is generated by obtaining a syndrome polynomial and one or more erasure locations. The syndrome polynomial and the erasure locations are associated with Reed-Solomon encoded information. A complementary error evaluator polynomial and an error locator polynomial are simultaneously generated using the syndrome polynomial and the erasure locations where the complementary error evaluator polynomial is a complement of the error evaluator polynomial.

Abstract: A method of encoding data for transmission from a source to a destination over a communications channel is provided. A plurality of redundant symbols are generated from an ordered set of input symbols to be transmitted. A plurality of output symbols are generated from a combined set of symbols including the input symbols and the redundant symbols, wherein the number of possible output symbols is much larger than the number of symbols in the combined set of symbols, wherein at least one output symbol is generated from more than one symbol in the combined set of symbols and from less than all of the symbols in the combined set of symbols, and such that the ordered set of input symbols can be regenerated to a desired degree of accuracy from any predetermined number, N, of the output symbols.

Abstract: A cyclic redundancy check (CRC) or other function may be used as an error correction mechanism by analyzing CRC results against a table of CRC results for potential flipped bits. From the table, an incorrect bit may be identified and corrected. Two or more bits may be identified and corrected by testing the XOR of the calculated CRC results with two or more results within the table to identify two or more bits that are incorrect. In one embodiment, data stored on a data storage system may be stored with a calculated CRC for each block of data. When the data is read from the storage system, the CRC function may be used to verify data integrity and to identify one or more bits that are incorrect in the retrieved data.

Abstract: A tree decoding method for decoding a linear block code is provided. According to the tree decoding method, an estimated path metric of node v is f(y)=g(v)+h(v), where g(v) represents a sum of bit metrics of all bits on a path from the root node to the node v, and h(v) represents a lowest bound of estimated accumulated bit metrics from the node v to the goal node. The present invention creatively improves the approach for calculating h(v). According to the present invention, some parity bits are only related to a part of the information bits, according to which the edge metric h(v) of the parity bits can be preliminarily incorporated into the path metric of the part of the information bits. As such, some nodes having inferior path metric could be eliminated in advance, thus minimizing the searching range and simplifying the decoding complexity.

Abstract: A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.

Abstract: Methods and apparatus for enabling effective decoding of rate-compatible punctured codes are presented herein. A puncturing component can derive one or more partial puncturing patterns and corresponding decoding matrices/graphs that represent punctured code from a parity check matrix/graph of a mother code and a puncturing pattern specified for the mother code. Further, a rowcombining component can combine rows of the parity check matrix/graph based on the derived one or more partial puncture patterns. Further, the rowcombining component can create at least one decoding matrix/graph to represent the punctured code based on the combined rows. In addition, a selection component can select a decoding matrix/graph from the created at least one decoding matrix/graph that does not contain a girth-4 cycle.

Abstract: An improved mapping policy, signal mapper, transmitter, receiver, and communication system are introduced. The improved signal mapping policy alternates between standard and inverted bit mapping functions at selected phase states to reduce the error coefficient of MSK and other types of CPFSK signals. The proposed policy can more generally be applied to other types of signals with memory as well. Simulations show that the mapping policy can significantly improve performance particularly at lower to moderate SNR values.

Abstract: Described embodiments provide for rate matching with an encoded sequence of data bits. The encoded sequence of data bits is divided into two or more sub-blocks, with each sub-block having at least one column of bits, each including a set of valid bits. A set of dummy bits is generated and appended to each column of each sub-block. A starting point index for the set of valid bits within each sub-block is generated and the number of bits supported by the physical layer is determined. Only the valid bits of each sub-block are interleaved, based on each starting point index, until either i) there are no valid bits remaining, or ii) the number of interleaved bits reaches the number of bits supported by the physical layer. All dummy bits and any valid bits exceeding the number of bits supported by the physical layer are omitted.

Abstract: An application specific processor to implement a Viterbi decode algorithm for channel decoding functions of received symbols. The Viterbi decode algorithm is at least one of a Bit Serial decode algorithm, and block based decode algorithm. The application specific processor includes a Load-Store, Logical and De-puncturing (LLD) slot that performs a Load-Store function, a Logical function, a De-puncturing function, and a Trace-back Address generation function, a Branch Metric Compute (BMU) slot that performs a Radix-2 branch metric computations, a Radix-4 branch metric computations, and Squared Euclidean Branch Metric computations, and an Add-Compare-Select (ACS) slot that performs a Radix-2 Path metric computations, a Radix-4 Path metric computations, a best state computations, and a decision bit generation. The LLD slot, the BMU slot and the ACS slot perform in a software pipelined manner to enable high speed Viterbi decoding functions.

Abstract: The method is for decoding an LDPC encoded codeword, the LDPC code being represented by a bipartite graph between check nodes and variable nodes including first variable nodes and second variable nodes connected to the check nodes by a zigzag connectivity. The method includes updating messages exchanged iteratively between variable nodes and check nodes including a first variable processing phase during which all the messages from the first variable nodes to the check nodes are updated and a check nodes processing phase during which all the messages from the check nodes to the first variable nodes are updated. The check nodes processing phase further includes updating all the messages from the second variable nodes to the check nodes, and directly passing an updated message processed by a check node to the next check node through the zigzag connectivity.

Abstract: A method and apparatus encode a source data stream via convolutional encoding or selected encoding scheme. Plural encoded data streams are interleaved and transmitted on a transmission channel. Data groups generated via convolutional or selected encoding are interleaved via time-interleaving functions to disperse selected bits within puncture groups of the data groups, bits in between data groups, and bits in selected sets of data groups to facilitate reconstruction of the source data stream from at least a portion of the interleaved data stream received on at least one transmission channel. The time-interleaving functions are selected to facilitate reconstruction of the source data stream from one transmission channel following continuous blockage. Subsets of bits of puncture groups are selected to allow reconstruction of the source data stream from more than one of plural transmission channels using a minimum number of subsets.

Abstract: A digital broadcasting system and method, where the digital broadcasting system includes: a transmission stream generator multiplexing a normal stream and a turbo stream to generate a dual transmission stream; a transmitter inserting an supplementary reference signal (SRS) into the dual transmission stream, processing the turbo stream to reconstitute the dual transmission stream, and outputting the reconstituted dual transmission stream; and a receiver receiving the reconstituted dual transmission stream, separately turbo decoding the turbo stream, inserting the turbo decode turbo stream into the dual transmission stream, and decoding the dual transmission stream into which the turbo decoded turbo stream has been inserted, to restore normal stream data and turbo stream data. Thus, reception sensitivity of a digital broadcasting signal can be efficiently improved.

Abstract: A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.

Abstract: Teachings presented herein provide a method (100) and apparatus (10) for processing input information bits (16) for coding using a code (20), such that the length of the information word (14) formed from the input information bits (16) matches a fixed information word length defined by the code 20. In at least one embodiment, a coding circuit (10) receives input information bits (16) and adds error protection bits (26) as needed, to make the information word length match the fixed information word length. The method (100) and apparatus (10) contemplate generating the error protection bits (26) by sub-coding a subset (28) of the input information bits (26) (e.g., parity bit generation), thereby providing extra protection for that subset (28). These teachings allow the same code (20) to be used for coding feedback or other information, where the amount of information to be coded varies as a function of operating modes.

Abstract: Quasi-cyclic LDPC (Low Density Parity Check) code construction is presented that ensures no four cycles therein (e.g., in the bipartite graphs corresponding to the LDPC codes). Each LDPC code has a corresponding LDPC matrix that is composed of square sub-matrices, and based on the size of the sub-matrices of a particular LDPC matrix, then sub-matrix-based cyclic shifting is performed as not only a function of sub-matrix size, but also the row and column indices, to generate CSI (Cyclic Shifted Identity) sub-matrices. When the sub-matrix size is prime (e.g., each sub-matrix being size q×q, where q is a prime number), then it is guaranteed that no four cycles will exist in the resulting bipartite graph corresponding to the LDPC code of that LDPC matrix. When q is a non-prime number, an avoidance set can be used and/or one or more sub-matrices can be made to be an all zero-valued sub-matrix.

Abstract: The subject matter disclosed herein provides methods and systems for converting fixed-point soft bit values, provided by a demapper, into floating-point soft bits values. In one aspect, there is provided a method. The method may include receiving, from a demapper, soft bits formatted as a fixed-point value. Moreover, the soft bits may be converted from the fixed-point value to a floating-point value. The floating-point value is punctured to remove a bit. The converted soft bits are provided to a buffer to enable decoding of the buffered soft bits. Related systems, apparatus, methods, and/or articles are also described.

Abstract: According to one embodiment, a maximum likelihood decoder includes a branch metric calculator, a processor configured to perform addition, comparison, and selection of an output from the branch metric calculator and a path metric memory, and outputs a selection signal for identifying a selection result, a path memory configured to store a time variation of the selection signal, and a path detection module configured to detect a decoding signal based on the time variation of the stored selection signal. A decoding method includes selecting operation modes of at least one of the branch metric calculator, the processor, and the path memory between a first operation mode in which an operation is performed at a channel rate frequency and a second operation mode in which an operation is performed at a specific frequency lower than the channel rate frequency.

Abstract: According to an embodiment of the present invention provides the signal processing system. In the signal processing device that estimates information data from a reception signal by performing iterative processing between a demodulator that demodulates data of n(>m) bits obtained by modulating data of m bits into m bits and an ECC decoder and carrying out maximum a posteriori probability decoding, the device has a module that calculates an a posteriori value after demodulation by performing calculation of modulation data having a pattern estimated to have a high probability alone as modulation data to be decoded from all patterns of the modulation data to be decoded when effecting calculation of the a posteriori value after demodulation based on an a priori value fed back from the ECC decoder at the time of effecting modulation for a second or subsequent time.

Abstract: A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. The disclosed path metric difference computation unit computes differences between paths through a multiple-step trellis, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second of the plurality of paths is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third of the plurality of paths is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle.

Abstract: Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algorithm, wherein the merge points each have a path metric difference, which is a difference between an ML path metric at the merge point and a non-surviving path metric at the merge point. Merge points are selected based upon relative path metric differences associated with nodes on the ML path. Next, alternate paths in the Viterbi trellis are computed based on the ML path with alternate paths substituted at corresponding merge points. A passing decoded bit sequence is output in response to passing an error check, wherein the passing decoded bit sequence is associated with one of the one or more alternate paths.

Abstract: The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.

Abstract: An enhanced mechanism for providing data protection for variable length records utilizes high performance block storage metadata. In an embodiment, an emulated record that emulates a variable length record, such as a Count-Key-Data (CKD) record or an Extended-Count-Key-Data (ECKD) record, is generated by a Host Bus Adapter (HBA) of a mainframe system. The emulated record comprises a sequence of extended fixed-length blocks, each of which includes a data block and a footer. A confluence of the footers defines a high performance block storage metadata unit associated with the emulated record and includes a checksum that covers all data blocks and all footers of the entire emulated record. In one embodiment, the checksum is checked during transit of the emulated record between a HBA and a storage subsystem (e.g.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel characterized by intersymbol interference. Each of the one or more codewords incorporates one or encodes one or more parity bits. The codewords are processed by a Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Meta-Viterbi detector receives an output generated from a Viterbi detector having 2s states and processes the received output using a trellis diagram having 2t states.

Abstract: A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.

Abstract: A Viterbi decoder and a Viterbi decoding method are provided for simplifying hardware and increasing an operation speed by using a decision feedback unit selecting one of at least two levels based on at least one survivor symbol fed back from a path memory unit. The Viterbi decoder includes a path memory unit (PMU) storing a survivor path, a decision feedback unit (DFU) selecting one of at least two levels based on at least one survivor symbol fed back from the PMU, a branch metric calculation unit (BMCU) calculating a branch metric by using the level selected by the DFU and the received symbol, and an add-compare-selection unit (ACSU) deciding the survivor path by using the branch metric calculated by the BMCU and a previously stored state metric and transmitting the decided survivor path to the PMU.

Abstract: Methods and apparatus are provided for reduced complexity Soft-Output Viterbi detection. A Soft-Output Viterbi algorithm processes a signal by determining branch metrics using a branch metrics unit; determining survivor paths for sequence detection using a first add-compare select unit; and determining survivor paths for generating one or more bit reliability values using a second add-compare select unit, wherein the first and second add-compare select units process the branch metrics determined by the branch metrics unit. The first and second add-compare select units can optionally process branch metrics having a different number of bits.

Abstract: A method and apparatus for turbo code decoding are provided to reduce memory consumption during calculation of state metrics. In an embodiment of a turbo code decoder, a natural recursion unit comprises a plurality of add-compare-select (ACS) units performing natural recursion operations to generate a state metric. The original state metric is then converted to a differential metric before being stored into a memory device. The differential metric contains less data than the state metric so that memory consumption is reduced. To restore the original state metric from the differential metric, a plurality of revival units operating in parallel is provided. Thereby, the state metric is reacquired from the differential metric, and a Log Likelihood Recursion (LLR) operation is accordingly performed by an LLR unit.

Abstract: A method of calculating backward computations branch metrics for a butterfly in a trellis of a MAP-genre decoding algorithm, the method comprising providing initialised branch metrics for the transitions in the butterfly and incrementing the branch metrics with a group of data values corresponding to said transitions in accordance with control signals derived from the butterfly index and one or more polynomials describing tap positions of the encoding equipment to whose operation the trellis relates, wherein said group comprises systematic bit and parity bit values.

Abstract: A data communication method for puncturing of parity bits defining all parity data for a minimum code rate generated by an encoder is disclosed. The method initializes an accumulator associated with the parity bits to an initial value, and for each parity bit increments the accumulator by a increment value and determines if the accumulator has overflowed. If the accumulator overflows, at least one of the parity bits is selected for transmission.

Abstract: Cooperative concatenated coding techniques are provided for wireless communications between at least two users and a base station. A network system employing cooperative concatenated coding includes cooperating user devices each configured to encode and transmit at least a portion of a joint message. The joint message includes at least a portion of a first message from a first cooperating user device and at least a portion of a second message from a second cooperating user device. An embodiment includes encoding a first message from a first cooperating user, receiving a second message from a second cooperating user and decoding the second message. The methodology also includes re-encoding at least a portion of the decoded message with at least a portion of the first message to form a combined message, and then transmitting at least a portion of the combined message.

Abstract: A method and system constructs a minimal trellis for decoding a block group code. A generator matrix of the code is obtained and converted into a row-reduced echelon matrix form. Vertices are determined from the row-reduced echelon matrix form at a first time. Further vertices at later times are also determined to obtain a minimal trellis for the block group code C for storing or use in decoding received codes.

Abstract: The present invention relates to a decoder for tail-biting convolution codes and a method thereof. The decoder receives an encoding bit sequence in a convolutional encoding method from a channel, generates an expanded encoding bit sequence, Viterbi decodes the expanded encoding bit sequence, and generates decoded data. In addition, the decoder selects a central bit sequence of the decoded data, rearranges the central bit sequence, and generates final decoded data. Accordingly, the decoder has a simplified configuration for decoding the bit sequence encoded in the tail biting convolutional encoding method, and the decoder also decodes a bit sequence encoded in a zero-tail convolutional encoding method.

Abstract: Systems and techniques for transmitting an Irregular Systematic with Serially Concatenated Parity (Ir-S-SCP) are described. The techniques include generating an outer code comprising a plurality of bits using systematic bits as input, repeating the plurality of bits of the outer code a pre-determined number of times to generate at least a first set of repeated bits and a second set of repeated bits, serializing the generated sets of repeated bits, wherein each generated set is serialized in parallel with another generated set, interleaving the generated sets of repeated bits, generating an inner code, the inner code generated in part based on the interleaved sets, puncturing the inner code to output parity bits, wherein the puncturing is non-uniform and the puncturing is based at least in part on an incremental redundancy scheme, and transmitting the parity bits, wherein the transmitted parity bits and the systematic bits comprise the Ir-S-SCP code.