Abstract: A data storage device includes a non-volatile memory device including a memory block having a number of memory dies, and a controller coupled to the memory device. A memory access command is received and a memory access operation based on the received command is performed. A number of bytes transferred during the memory access operation is determined, and the determined number of bytes is analyzed to determine whether the number of transferred bytes is equal to a predetermined number. A transfer status fail bit is set if the number of transferred bytes is not equal to the predetermined number.

Abstract: Disclosed embodiments relate to trust domain islands with self-contained scope. In one example, a system includes multiple sockets, each including multiple cores, multiple multi-key total memory encryption (MK-TME) circuits, multiple memory controllers, and a trust domain island resource manager (TDIRM) to: initialize a trust domain island (TDI) island control structure (TDICS) associated with a TD island, initialize a trust domain island protected memory (TDIPM) associated with the TD island, identify a host key identifier (HKID) in a key ownership table (KOT), assign the HKID to a cryptographic key and store the HKID in the TDICS, associate one of the plurality of cores with the TD island, add a memory page from an address space of the first core to the TDIPM, and transfer execution control to the first core to execute the TDI, and wherein a number of HKIDs available in the system is increased as the memory mapped to the TD island is decreased.

Abstract: An apparatus includes a communication device and an evaluation unit, wherein the communication device can be linked to a communication bus and can receive secure telegrams by way of the communication bus, and wherein a secure telegram includes user data and CRC data in each instance. In at least one embodiment, in order to improve the communication within the secure bus system, the evaluation unit can determine an error rate from received secure telegrams by way of a CRC check and if a threshold value of the error rate stored in the evaluation unit is exceeded, can effect a secure state of the apparatus.

Abstract: A storage apparatus for controlling a storage unit includes a cache memory for temporarily storing data to be stored in the storage unit, and a processor for executing a process including receiving unit data which is divided from data to be migrated, calculating first checksum data from the received unit data, storing the unit data and the first checksum data to the cache memory, reading out the stored unit data and the first checksum data from the cache memory, calculating second checksum data from the read out unit data, storing the unit data to the storage unit, and determining whether data migration has been performed properly by comparing the first checksum data to the second checksum data.

Abstract: Message content associated with at least one message received by a message processing server is stored in association with the message processing server. The message content within an incoming message is compared with the stored message content. A determination is made as to whether the stored message content is duplicated by the message content associated with the incoming message. A duplicate message content management action is performed based upon the determination as to whether the stored message content is duplicated by the message content associated with the incoming message. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: A method may include receiving a content message from a content provider at a computing device, the content message including at least one content item to be included in alert messages. The method may further include verifying a content item included in the content message for duplication against a content history by utilizing the computing device, the verifying including: computing an item checksum for the content item; querying the content history for the item checksum; and determining whether the item checksum is a duplicate based on a result returned from the query. The method may further include if the content item is determined not to be a duplicate: matching the content item to an alert template associated with a subscriber, and generating an alert message including the content item based on the alert template.

Abstract: A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.

Abstract: A data writing method for a rewritable non-volatile memory module is provided. The present method includes compressing an original data to generate a first data and determining whether the length of the first data is smaller than a predetermined length. The present method also includes outputting the first data as a compressed data when the length of the first data is not smaller than the predetermined length. The present method further includes generating an ECC code corresponding to the compressed data, generating an ECC frame according to the compressed data and the ECC code, and writing the ECC frame into the rewritable non-volatile memory module. Accordingly, when data corresponding to the original data is read from the rewritable non-volatile memory module, error bits in the data can be corrected and the original data can be restored according to the ECC code.

Abstract: A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device.

Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

Abstract: A method of de-mapping non-binary Galois field symbols from physical layer code-words in a data communication system, in which at least one physical layer code-word includes portions mapped from more than one non-binary Galois field symbol is provided. The method includes calculating at least a provisional likelihood estimate for values of a first non-binary Galois field symbol having at least portions within a first physical layer code-word, the calculating including selecting a first number of values of a second non-binary Galois field symbol having at least portions within the first physical layer code-word, the first number forming a subset of the possible values of the second non-binary Galois field symbol.

Abstract: Provided are methods and systems of selectively decoding optical data read from an optical storage medium based on a checksum algorithm technique. In one embodiment, optical data is converted into a data stream and buffered, and the checksum algorithm is applied to the data stream. If the calculated checksum matches an encoded checksum of the data stream, the data stream may be output without requiring further decoding. If the calculated checksum does not match the encoded checksum, the buffered data stream may be decoded to produce a corrected data stream, and the checksum algorithm may be applied to the corrected data stream. In some embodiments, the optical data may be re-read if the corrected data stream does not pass the checksum test, and the data stream obtained from the re-reading may be combined with the buffered data stream for further decoding.

Abstract: A flash memory includes a memory sector, a command interface, a first signal buffer, a control signal generation circuit, a data input buffer, an error correction circuit, an address buffer, an address signal generation circuit, a plurality of data memory circuits, and write circuit. The command interface receives a write data input instruction from an external device to generate a write data input instruction signal, and receives a write instruction from the external device to generate a write instruction signal. The error correction circuit is activated by the write data input instruction signal to receive the write data in synchronization with the write enable signal, and is activated by the write instruction signal to generate a check data for an error correction in synchronization with the control signal.

Abstract: A method for updating firmware of an embedded system includes the following steps: a firmware update instruction for updating the firmware of the embedded system according to a firmware image is received. Wherein, the embedded system includes a memory and a storage unit. The firmware of the embedded system is stored in the storage unit. The firmware image is divided into several partition images. Several available blocks are obtained from the memory. The partition images are stored into the available blocks. Information of the partition images stored in the available blocks is recorded into an image information table. The partition images are obtained from the memory according to the image information table. The firmware of the embedded system is overwritten by the partition images obtained.

Abstract: A method and apparatus for the installation of software is described herein. In one embodiment, a process is provided to verify a first set of packages selected from all packages, for example, on an optical disk, and verify a second set of packages on the optical disk. The verifying of the first set of packages calculates a first checksum for each package in the first set of packages and compares this first checksum to a second checksum for each package read from the optical disk. A second set of packages is verified if the verification of the first packages is successful. The second set of packages is verified by copying each package in the second set of packages, from the optical disk. A third checksum is included with each package read, and this third checksum is compared with a fourth checksum calculated for each package.

Abstract: Data errors in non-volatile memory inevitably increase with usage and with higher density of bits stored per cell. The memory is configured to have a first portion operating with less error but of lower density storage, and a second portion operating with a higher density but less robust storage. Input data is written and staged in the first portion before being copied to the second portion. An error management provides checking the quality of the copied data for excessive error bits. The copying and checking are repeated on a different location in the second portion until either a predetermined quality is satisfied or the number or repeats exceeds a predetermined limit. The error management is not started when a memory is new with little or no errors, but started after the memory has aged to a predetermined amount as determined by the number of erase/program cycling its has experienced.

Abstract: In a first embodiment of the present invention, a method for operating a midpoint device utilizing an Input/Output (I/O) interconnect is provided, wherein the midpoint device contains a plurality of ports, the method comprising: receiving a request to initiate a session between a device on a first port of the midpoint device and a device on a second port of the midpoint device; retrieving information regarding whether the first port supports a feature, and information regarding whether the second port supports the feature; and when the first port supports the feature and the second port does not support the feature, permitting the session to be initiated, such that communications between the first device and the second device are performed partially using the feature, independently of support of the feature on other ports.

Abstract: One embodiment of the present invention sets forth a technique for protecting data with an error correction code (ECC). The data is accessed by a processing unit and stored in an external memory, such as dynamic random access memory (DRAM). Application data and related ECC data are advantageously stored in a common page within a common DRAM device. Application data and ECC data are transmitted between the processor and the external common DRAM device over a common set of input/output (I/O) pins. Eliminating I/O pins and DRAM devices conventionally associated with transmitting and storing ECC data advantageously reduces system complexity and cost.

Abstract: A method for adaptively applying an error-correcting code to a storage device is disclosed. A determination is made that a system is in an idle state of input/output requests. First data symbols are copied into a first location within a buffer. First data symbol errors corrected using a first error-correcting code. Second data symbols including corrected bits are written in a second location on the recording media with a second error-correcting code. An error number for the second data symbols in the second location is determined. If the error number is below a first threshold error number, the first data symbols are deleted. If the error number is above the first threshold error number, the second data symbols are deleted.

Abstract: Systems and methods of tracking error data are disclosed. A method includes receiving a first checksum associated with error locations of a first error correction code operation and receiving a second checksum associated with error locations of a second error correction code operation. The first checksum is compared to the second checksum and an action is initiated on a region of a memory array based on a result of the comparison.

Abstract: Subject matter disclosed herein relates to remapping memory devices.

Abstract: Methods, systems and computer readable media for controlling an instrument in communication with a host computer are provided. Operations of an instrument that must be completed on schedule are controlled via an embedded controller embedded in the instrument. A complete status packet is sent to a host computer from the embedded controller Periodically, the embedded controller repeats the sending of a complete status packet to the host computer, wherein status values in the complete status packet are updated with each iteration of sending a complete status packet.

Abstract: A system and method for ensuring or verifying the integrity of data transmitted between protection domains. When the data is transmitted, it may be received in a different logical configuration (e.g., as a different number of “chunks”). The receiving domain computes its data integrity metadata (e.g., checksum, CRC, parity) on its form of the data using its protection scheme (e.g., checksum algorithm), and also applies the sending domain's protection scheme to the data as it was received from the sending domain. Similarly, the sending domain applies the receiving domain's protection scheme to compute data integrity metadata on the transmitted data as it appears in the receiving domain. The metadata may be compared to determine whether the data was corrupted during the transfer. Either domain may forward its data integrity metadata to the other, which may store and/or forward it as needed.

Abstract: Message content associated with at least one message received by a message processing server is stored in association with the message processing server. The message content within an incoming message is compared with the stored message content. A determination is made as to whether the stored message content is duplicated by the message content associated with the incoming message. A duplicate message content management action is performed based upon the determination as to whether the stored message content is duplicated by the message content associated with the incoming message. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.

Abstract: Several methods and apparatus to single XOR operation weaver reconstruction of a failed drive of a raid are disclosed. A failed drive of the drive group implemented in a WEAVER code with an (n,t,t) layout is determined. A set of scatter/gather lists is produced from a number of the other drives of the drive group. A scatter/gather list is created by modifying a pointer data of the set of scatter/gather lists. An additional scatter/gather list is generated from the set of scatter/gather lists. A single XOR operation is performed on the data segment, the parity segment, the additional data segment and the additional parity segment to form a resulting scatter/gather list including a resulting data segment and a resulting parity segment. The resulting data segment and the resulting parity segment are written as sequenced in the resulting scatter/gather list to a replacement drive.

Abstract: A method for uploading and storing application code in a re-writable, non-volatile memory of an electronic device is carried out by means of a bootloader. The bootloader receives the application code transmitted by a master unit through a communication channel, writes at least one portion of the application code to a portion of the non-volatile memory, and validates the at least one portion of the application code by means of the bootloader.

Abstract: A communication method includes causing a transmitter to apply error correcting or detecting code systems to multiple frames or packets and to transmit the multiple frames or packets in succession, causing a receiver to receive the transmitted frames or packets and to decode each of the frames or packets received, and causing the receiver to send an acknowledgment signal to the transmitter on the basis of the results of decoding of the frames or packets. The transmitter applies two or more error correcting or detecting code systems to the frames or packets.

Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header includes a CRC to provide improved error detection.

Abstract: Aspects of the invention support a component configuration mechanism when rebooting a circuit module (201) of a programmable logic controller (101). A component (application) may be configured from a plurality of sources, including flash memory (204) and a web-based configuration source. The configuration mechanism avoids using invalid configuration data when replacing the communication module. The circuit module may support a plurality of components, where some of the components may be associated with a web-based configuration while other components may be associated with a CPU-based configuration. If the configuration data in the flash memory of the communication module is determined to be invalid, the communication module obtains configuration data from a web-based configuration source for a web-based configured component and from an associated CPU module (202) for a CPU-based configured component.

Abstract: A method of processing data, the method including decoding extracted data, correcting errors of the decoded data and generating data bits and data bit flags indicating error-corrected data bits from among the data bits, re-decoding the extracted data according to the data bits and the data bit flags, and correcting errors of the re-decoded data.

Abstract: A method for controlling access to data in a Flash is provided, including steps as follows: outputting at least one main data block to a buffer area of the Flash continuously, the buffer area of the Flash being adapted to buffer data to be inputted to a storage area of the Flash; generating and buffering checksum data for each main data block while outputting the at least one main data block; and outputting the buffered checksum data of the at least one main data block to the buffer area of the Flash. Another method for controlling access to data in the Flash, apparatuses corresponding to the methods and methods for controlling data access by a controller are also provided. The efficiency of data access in the Flash is raised.

Abstract: The present invention intends to provide a semiconductor recording device that is able to continuously record data and has high reliability even in a case where writing errors frequently occur. When data to be written is recorded as an error correction code (ECC) in a plurality of physical blocks constituting a nonvolatile memory and a writing error occurred, a time interval between the writing error that occurred immediately before and the present writing error is detected. Then, when the time interval is within a first reference time, an error position management unit registers a writing error occurrence block number and block numbers grouped with the writing error occurrence block in the ECC. Then, the writing error registered in the error position management unit is read at a predetermined timing, and the error is corrected on the basis of the ECC and the corrected data is rewritten.

Abstract: A flash memory system includes a memory unit including a main cell that stores main data and a parity cell that stores parity data, and an ECC receiving a codeword including the stored main data and the stored parity data, performing error correction on the codeword by executing an operation on a finite field with respect to the codeword, and an element of the finite field comprising a codeword corresponding to an erased page of the memory unit.

Abstract: A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data.

Abstract: According to one embodiment, providing a bitstream to one or more programmable devices of a service unit card includes receiving the bitstream at a snooper of the service unit card. The snooper determines whether the bitstream is current. If the bitstream is current, the bitstream is loaded onto the programmable devices. If the bitstream is not current, the received bitstream is discarded, and a substitute bitstream is identified. The substitute bitstream is loaded onto the programmable devices.

Abstract: A method and device for adjusting communications power are used for detecting a communications condition between a connection port and a connection target, and a communications-supporting power of the connection port that includes at least one of a transmitting power and a receiving power is adjusted according to a detected communications condition. Therefore, accuracy of data transmission and reception is ensured, and power used for data transmission and reception is reduced.

Abstract: A method and apparatus for dynamic network link acceleration provides a managed communication link for accelerated and reliable network communication between a client and other network devices on demand. In one or more embodiments, the system comprises an enhanced client capable of providing front-end services. The enhanced client may establish the communication link with a back-end mechanism. The communication link may provide error correction, security, quality of service, and other services including acceleration of communications. In one embodiment, the enhanced client provides a communication link utilizing the TMP protocol by cooperative action with a back-end mechanism. A client may be various computing or network devices and may be enhanced with front-end services automatically by automatic download and installation of an internal front-end or manually by user installation of an internal front-end.

Abstract: A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.

Abstract: A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.

Abstract: A firmware updating method for use in a mobile device is provided. The method comprises the following steps. First, during a previous downloading procedure or a previous updating procedure, a flag indicating a current status of the previous downloading procedure or the previous updating procedure, and a signature corresponding to the flag are generated and stored in a non-volatile storage device. Next, the flag and the signature are acquired from the non-volatile storage device when booting subsequent to the previous downloading or updating procedure. Next, integrity of the flag is verified by inspecting the signature. Lastly, the updating procedure is performed to update an original firmware with a new firmware when the integrity of the flag is verified and the flag indicates that the previous updating procedure is undergoing or the previous download procedure is completed.

Abstract: Methods and systems for capturing error information regarding a Serial Advanced Technology Attachment (SATA). An initiator device is enhanced in accordance with features and aspects hereof to detect an error condition in operation of the system and to transmit error information to the SATA target device during a soft reset condition applied to the SATA target device. The SATA target device discards all such frames received during the soft reset condition until the initiator device clears the soft reset condition. The error information may be captured for further analysis and debug of the error condition by suitable error analyzer equipment such as a SATA bus analyzer. The initiator device may be a SATA initiator or a Serial Attached SCSI (SAS) initiator using the SATA Tunneling Protocol (STP). Features and aspects hereof may also include a SAS/SATA bridge device coupling a SAS initiator to the SATA target device.

Abstract: The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.

Abstract: Disclosed herein is an encoding apparatus which combines an RLL code word and an error correction code word, with an interleaving technique when encoding, including: an error correction encoding section; an interleaving section; and an RLL encoding section, wherein, if an address i (i is an integer satisfying relations 0?i<k×m) is assigned to each symbol of k×m error correction code words and xij is denoting the number of symbols included in n symbols of a jth (j is an integer satisfying relations 0?j<m) code word of m error correction code words to serve as symbols corresponding to the address i of an information word of an RLL code, for any j, the interleaving section interleaves a series inside an information word of the RLL code word so that the following relations are satisfied: ? i ? x ij = n ? ? and ? ? x ij > 0.

Abstract: A method is provided of data storage by encoding a bit stream on a surface. The method involves printing coded data on the surface which encodes the bit stream, and printing alignment data on the surface which is indicative of a position of the coded data on the surface. The alignment data has a first registration structure indicative of a plurality of reference points indicative of a position of the coded data in an alignment direction, and a second registration structure indicative of a plurality of reference points indicative of a position of the coded data in a direction perpendicular to the alignment direction.

Abstract: A method for backing up data of a storage system, where at least two mirroring channels are provided between a first mainboard and a second mainboard of a storage system, and the method includes: transmitting data through at least one mirroring channel if all the mirroring channels are effective; and transmitting the data through remaining mirroring channel(s) if at least one of the mirroring channels for transmitting the data fails. The present disclosure enables traffic to be transmitted evenly on normal mirroring channels, and ensures maximized utilization of the bandwidth of mirroring channels. Corresponding to the foregoing method, an apparatus for backing up data of a storage system is provided in another embodiment of the present disclosure.

Abstract: A memory management method and a controller for a non-volatile memory storage device are provided. The memor management method and the controller are adapted for establishing a logical-to-physical mapping table of each block in a memory buffer of the controller by merely reading the data stored in a system management area within a start page of each block, so as to promote the management efficiency of the non-volatile memory storage device. In addition, the method and the controller of the present invention integrate all of or a part of the system management areas within the start page for efficiently managing and using the memory capacity of all the system management areas within the start page.

Abstract: A semiconductor memory device is capable of outputting a preset logic level through an EDC pin according to an operation mode during an initial operation, and providing a stable operation according to the specification of the semiconductor memory device just after the input of a data clock (WCK). The semiconductor memory device includes an output circuit configured to output a synchronous data in response to a data clock when the data clock is enabled, and output an asynchronous data when the data clock is disabled, and a data clock detection circuit configured to control outputting the asynchronous data by checking whether the data clock is in a stable state or not.

Abstract: A computer program product, apparatus, and method for inserting multiple CRCs in an output data stream from a channel subsystem to a control unit are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a message to transmit from the channel subsystem to the control unit. The method also includes determining a first CRC insertion position, and receiving a first CRC calculated over a first block of data in the message. The method additionally includes inserting the first calculated CRC at the first CRC insertion position, and determining a second CRC insertion position. The method further includes receiving a second CRC calculated over a second block of data in the message, and inserting the second calculated CRC at the second CRC insertion position.

Abstract: A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program.

Abstract: A method includes organizing a first media source block in the media container file; calculating forward error correction (FEC) redundancy data based on the first media source block; organizing the FEC redundancy data in at least one FEC reservoir in the media container file; providing, in the media container file, meta data providing an association between the first media source block and the at least one FEC reservoir; storing the first media source block as a first elementary item in the media container file; and providing, in the media container file, information that the first elementary item comprises the first media source block