Abstract: Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.

Abstract: Systems and methods to respond to error detection are provided. A particular method may include issuing a first command to a first redrive device and a second command to a second redrive device. The method may also include reissuing the second command to the second redrive device in response to detecting a transmission error between a memory controller and the second redrive device. The method may further include storing at a first buffer first data that is received from the first redrive device in response to the first command. The method may include storing at a second buffer second data that is received from the second redrive device in response to the reissued second command. The method also may include merging the second data with the first data.

Abstract: A memory controller and a method for improved computer system performance invalidates (i.e., cancels or does not allow for execution of) speculative or unnecessary scrub write commands as part of the periodic execution of the overall scrub command upon the occurrence of certain events, such as if the error checking and correction (ECC) operation indicates that the data were received without error or if the ECC operation indicates that the data received have an uncorrectable error.

Abstract: Non-inline transaction error correction is disclosed. Where a transaction being processed in a pipeline is determined to include a correctable error, it is output, or drained, from the pipeline into an error queue. The pipeline is switched from a normal mode of operation to a correction mode of operation. In the correction mode, a correction command is inserted into and processed within the pipeline to correct the error within the transaction. The pipeline is switched from the correction mode of operation to a restart mode of operation. In the restart mode, the transaction is reprocessed within the pipeline. The pipeline is then switched from the restart mode of operation back to the normal mode of operation.