Abstract: A method and a system for automated switchover timer's tuning on network systems or Next Generation Emergency Systems configured so that the sending, by a master node, of a heartbeat and/or ARP ping to one or more backup nodes and/or a surveillance unit according to preconfigured switchover timer values can occur to check if the master node is still active. One or more backup nodes and/or a surveillance unit, can use an additional first Session Initiation Protocol (SIP) OPTION message to the master node after receiving the heartbeat and/or the ARP ping or if the heartbeat and/or ARP ping fails to be received according to the switchover timer values. An administrator or an administrative unit of the network can perform a switchover or failover to a backup node in case the first SIP OPTION message is not answered with a suitable response by the master node.

Abstract: Systems, methods, and other embodiments associated with at-speed testing of static random access memory (SRAM) are described. In one embodiment, a method includes loading, into a multi-stage pipeline of memory devices, a control pattern for testing a static random access memory (SRAM). The SRAM is tested by generating a test input that is based, at least in part, on the control pattern from the multi-stage pipeline of flip-flops. The test input is provided to the SRAM over a series of clock cycles that are at a core clock speed of the SRAM.

Abstract: Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A main signal path includes a Mueller-Muller based timing error detector (MM TED). The main signal path generates a main error signal for clock recovery. A secondary signal path that includes a secondary MM TED. Each signal path samples soft symbols from a received signal. The sampling of the secondary MM TED is deliberately offset in time. A scale factor applied to the main error signal and to a secondary error signal is adaptively adjusted based on a comparison between the main error signal and the secondary error signal.

Abstract: A device for controlling frequency synchronization includes a processor (101) for controlling a phase-controlled clock signal to achieve phase-locking between the phase-controlled clock signal and a reference clock signal, and for controlling a frequency-controlled clock signal so as to achieve frequency-locking between the frequency-controlled clock signal and the reference clock signal. The processor is also configured to monitor a deviation between the frequency- and phase-controlled clock signals, detect a change of circumstances such as temperature changes causing frequency drifting of the frequency-controlled clock signal, and replace or correct the frequency-controlled clock signal with or on the basis of the phase-controlled clock signal when both the monitored deviation and the detected change of circumstances show correlation confirming frequency drift of the frequency-controlled clock signal.

Abstract: Systems and methods are disclosed herein for a replicated duplex computer system. The system includes a triplet of network elements, which each maintain a clock signal, and a monitor at each network element for monitoring incoming clock signals. Each network element interfaces with a fault containment region (FCR). The system provides the ability to transition to a duplex system if one of the fault containment regions fails. The three network elements are able to send their clock signals to the other network elements and receive their own clock signal and clock signals from the other elements. The monitors are configured to detect discrepancies in the clock signals of the network elements. If a monitor determines that an FCR has failed, each network element is reconfigured so that the FTPP system operates in a duplex mode without the faulty FCR by replacing the clock signal from the faulty element with its own clock signal.

Abstract: A method for generating a preamble signal for a wireless communication system including the step of combining a plurality of different short PN sequences into a long PN sequence, wherein one of the plurality of short PN sequences includes information that is configured for coarse timing synchronization, and the long PN sequence includes information that is configured for fine timing synchronization.

Abstract: A semiconductor memory device includes a plurality of banks, each including a plurality of first memory cells and a plurality of second memory cells; a first input/output unit configured to transfer first data between the first memory cells and a plurality of first data pads; a second input/output unit configured to transfer second data between the second memory cells and a plurality of second data pads; a path selection unit configured to transfer the first data, which are input through the first data pads, to both the first and second memory cells during a test mode; and a test mode control unit configured to compare the first data of the first and second memory cells, and to control at least one of the first data pads to denote a fail status based on a comparison result, during the test mode.

Abstract: A method and system for client recovery strategy to maximize service availability for redundant configurations is provided. The technique includes adaptively adjusting timing parameter(s), detecting failures based on adaptively-adjusted timing parameter(s), and switching over to a redundant server. The timing parameter(s) include a maximum number of retries, response timers, and keepalive messages. Switching over to alternate servers engaged in warm sessions with the client may also be implemented to improve performance. The method and system allow for improved recovery time and suitable shaping of traffic to redundant servers.

Abstract: A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receiving wireless data transmissions from one or more remote peripheral devices. The wireless USB hub further includes a hub controller for passing appropriate peripheral device information to a USB upstream port and then to a computer.

Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.

Abstract: Upon receiving a particular data unit by a receiving layer of a wireless device, it is detected that a previous data unit earlier in sequence to the particular data unit has not yet been received by the receiving layer. A timer is started in response to the detecting, where the timer has a time-out period that is variable dependent upon a parameter associated with receipt of the particular data unit. Upon expiration of the timer based on the timeout period, the receiving layer generates an error indication.

Abstract: A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of the scan chains (101.k, 102.k), a shared scan-programmable control circuit (110, 300), a tree circuit (400) coupled with the functional integrated circuit (P1, P2), the shared scan-programmable control circuit (110, 300) coupled to control the tree circuit (400), and a selective coupling circuit (180) operable to provide selective coupling with the shared scan-programmable control circuit (110, 300) for scan programming through any of the multiple scan decompressors (120.1, 120.2). Other circuits, devices, systems, and processes of operation and manufacture are disclosed.

Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.

Abstract: An information processing apparatus includes a degeneration control unit and a re-synchronization processing instructing unit. The degeneration control unit degenerates, of a first controller group including a first controller and a second controller group including a second controller, the second control device group when the first and second controller performing a synchronization operation with each other detect occurrence of errors. The re-synchronization processing instructing unit instructs a controller included in the first controller group to execute re-synchronization processing. When another controller different from the first controller receives the instruction for the execution of the re-synchronization processing, the another controller performs interrupt mask setting.

Abstract: An application attempts to use a first protocol stack to send a first message to a server. After attempting to send the first message to the server, the application attempts to use a second protocol stack to send a second message to the server. After attempting to send the second message to the server, the application performs a timeout activity before a timeout period for the second message expires when the first message timed out. Alternatively, when the timeout period for the second message expires and the first message did not time out, the application performs the timeout activity. When the client device received a response to the second message from the server before the timeout period for the second message expires, the application performs a different activity.

Abstract: In accordance with embodiments, there are provided mechanisms and methods for resolving a data conflict. These mechanisms and methods for resolving a data conflict can enable an improved user experience, increased efficiency, time savings, etc.

Abstract: Embodiments of the present invention provide a system that leverages the Operational Support System(s) (OSS) and Business Support system(s) (BSS) of a (e.g., public) computing Cloud with a service to automate virtual instance restarts. For example, under embodiments of the present invention, a failed virtual instance is detected within the Cloud computing environment, and a request for a new virtual instance is received in response thereto. Upon receiving the request, an entitlement of a user associated with the failed virtual instance will be tested. Specifically, a set of authentication calls and checks are deployed in accordance herewith to ensure the integrity of the requests, as well as the authorization of the requester for the resource use. Assuming testing is passed, a countdown timer associated with the failed virtual instance will be decreased. When the countdown timer reaches a predetermined threshold (e.g.

Abstract: In a test and debug system in which a plurality of selectable modules under test have different operational rates, a selection unit associated with each module is used to control the application of the RCLK signal from the module to the combiner unit, the combiner unit providing a composite RCLK signal. Each selection unit has output signals of RCLK_NE and RCLK_PE signals which are applied to an combiner unit to form the composite RCLK signal. In response to the SELECT signal, the RCLK_NE and RCLK_PE are synchronized with the module RCLK signal. When the SELECT signal is removed, the RCLK_NE and RCLK_PE signals are continuously applied to the combiner unit.

Abstract: An object of the present invention is to provide a semiconductor device capable of recognizing circuit malfunction in an actual operation and of specifying a point of the circuit malfunction, and the semiconductor device, which does not induce the malfunction in the circuit of a subsequent stage when restoring the malfunction. The present invention is the semiconductor device provided with a plurality of logic circuits and a plurality of judging circuits for judging malfunction based on data from the logic circuits, wherein each of the judging circuits is provided with a first register, delay unit, a second register, a comparator and scanning unit, which makes the second register a shift register to allow to transmit an error signal held in the second register to the subsequent stage, while allowing the comparator to hold a comparison result.

Abstract: A clock signal test apparatus for testing a computer system includes a frequency generator to generate a clock pulse signal, a real-time clock (RTC) chip to receive the clock pulse signal from the frequency generator, and a micro control unit (MCU). The MCU is to receive a test command signal from the computer system to set a first current time of the RTC chip equal to a current system time of the computer system, and to receive a time comparing command from the computer system after a test interval to retrieve a second current time of the RTC chip and transmit the second current time of the RTC chip to the computer system.

Abstract: An integrated microprocessor system for safety-critical control systems, comprising at least two microprocessor system modules each comprising at least one processor core, a read/write memory and a memory protection unit, and a read-only memory which is jointly assigned to the processor cores of the microprocessor system modules. Each of the microprocessor system modules executes a main program and a monitoring program which may comprise a plurality of subprograms. If the memory protection unit detects unauthorized operations by one of the programs for accessing a separate address area (A, B) of another program, then the respective memory protection unit assigns a separate address area (A, B) of the read/write memory to the main program and to the monitoring program.

Abstract: A clock supply method for supplying a clock to a plurality of processing units includes supplying a clock from a first clock supply unit to processing units forming a first group as a primary clock and to processing units forming a second group as a standby clock; supplying a clock from a second clock supply unit including a clock source different from that of the first clock supply unit to the processing units forming the second group as a primary clock and to the processing units forming the first group as a standby clock; and when a processing unit in the first or second group detects an abnormality of the primary clock, switching the standby clock into use in place of the primary clock being supplied to the processing units that has detected the abnormality belongs; wherein the first and second clock supply units supply clocks with the same frequency.

Abstract: A method for generating a test pattern set for detecting small delay defects of an IC is disclosed. In one embodiment, the method includes: (1) generating a traditional delay fault pattern, (2) fault grading the traditional delay fault pattern for small delay defect coverage, (3) reporting faults detected by the fault grading and delay information associated with the detected faults, (4) determining which of the detected faults are timing-aware target faults employing the delay information and (5) generating timing-aware delay fault patterns for the timing-aware target faults.

Abstract: A primary time server of a Coordinated Timing Network remains as current time server, even if time code information of the primary time server is unavailable. The primary time server receives the necessary or desired timing information from a secondary time server and uses that information to maintain time synchronization within the Coordinated Timing Network.

Abstract: A program processing device has a non-volatile storage, a volatile storage and a controller. The controller has a detector that detects a bit flip in the program, the variable data, and the constant data in the volatile storage, a constant recovery unit that, when the detector detects an error in the constant data, writes the constant data in the non-volatile storage into the volatile storage, and then continues the execution of the program from a point at which the program was being executed before the detector detected the error, and a restart that, when the detector detects an error in one of the variable data and the program, writes the program, the initial value of the variable data, and the constant data in the non-volatile storage into the volatile storage, and then executes the program written into the volatile storage from a beginning of the program.

Abstract: The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached.

Abstract: A communication control apparatus transmits data to an other communication control apparatus and receives a notification as to whether the data has normally been received or not from the other communication control apparatus. The communication control apparatus includes setting changing means for changing setting of a transmission circuit when reception error which is a notification that the data has not normally been received is received from the other communication control apparatus.

Abstract: A system for detecting a work status of a computer system is provided. The system includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD), a South Bridge chipset and a device driver. The device driver is configured for driving the Super I/O chipset to generate and send a start signal to the CPLD, and is further configured for driving the Super I/O chipset to periodically generate and send a test signal to the CPLD. The CPLD is configured for receiving the start signal and triggering a clock to start timing from an initial time, monitoring whether a predetermined amount of test signals have been received in a predetermined time, and is further configured for sending a reboot signal to the South Bridge chipset when the predetermined amount of test signals have not been received in the predetermined time. The South Bridge chipset is configured for rebooting the computer system when receiving the reboot signal. A related method is also provided.

Abstract: A digital interface (22) includes a self-test structure (56). The structure (56) includes a transmit section (52) and a receive section (36) having a correlator (68). A method (114) of testing the interface (22) entails coupling the receive section (36) with the transmit section (52) and communicating a test data structure (86) from the transmit section (52) to the receive section (36) at a high data rate. The test data structure (86) includes a pre-defined sync pattern (88), a header (90), and a payload (92). The receive section (36) detects the sync pattern (88) and performs time frame synchronization (148) at the correlator (68). When synchronization (148) is successful, the receive section (36) decodes (154, 162) the header (90) and the payload (92). If time frame synchronization (148) and decoding (154, 162) are successful, a validation indicator (100) is output for external observation at a low data rate.

Abstract: Addition of specific test logic may improve the level of test vector compression achieved from existing variable scan test logic. Methods for determining the compressed vectors' states, given the desired uncompressed vectors' values may be used, and techniques for selectively enabling test or other features on a chip by inserting the proper code or codes into the chip may further be used. Techniques may be used to incorporate and apply various types of reset operations to multiple strings of variable scan test logic, as may methods to minimize the test vector compression computation time.