Abstract: In a time synchronization method, after clock board times between service boards are synchronized, a service board obtains a CPU time and the clock board time of the service board according to a preset periodicity, and makes a record. When performing CPU time synchronization between the service boards, the service board obtains a current CPU time of the service board, calculates a synchronization time of the CPU based on the current CPU time, a last recorded CPU time and clock board time, and adjusts the CPU time of the service board to the synchronization time. After the clock board times between the service boards that need to implement CPU high-precision time synchronization are synchronized by using a high-precision time synchronization protocol, the CPU time of each service board is adjusted to a corresponding synchronization time.

Abstract: An integrated circuit for use in high-reliability electronic systems contains one or more digital majority voters with corresponding disagreement detectors connected to the same input signals producing a majority value output and an error signal that is active when not all input signals agree. Internal error signals from multiple majority voter/disagreement detectors as well as external error inputs may be combined using disjunctive error logic to produce an “error detected” output indication. Cold-sparing and hot-plugging are supported by providing cold-sparable electrostatic discharge protection circuits and power-on reset circuitry controlling cold-sparable output stages. Internal modular redundancy provides immunity to single-event transients as well as enhanced reliability.

Abstract: Disclosed are systems and methods for providing in-service testing using a redundant segment. A device (e.g., memory, filter, GPU) is implemented as multiple device segments. For example, a filter including 1024 taps may be implemented as sixteen smaller filter segments that include 64 taps each. A redundant segment that is of similar size to the device segments is used to provide in-service testing of the individual device segments. For example, the redundant segment is provided the same input as a device segment and the output of the redundant segment and the device segment are compared to determine whether the device segment is operating correctly. Multiplexers are used to cycle use of the redundant segment to provide in-service testing of each of the device segments. For example, the multiplexers can be configured into different modes to provide for testing of the various device segments.

Abstract: This invention relates to a method for detecting faults in the operating states of a surgical robotic system, wherein the surgical robotic system including a master computer, a master embedded computer and a plurality of slave embedded computers is provided; the master computer controls the master embedded computer and the slave embedded computers via the LAN router; the master embedded computer communicates with the slave embedded computers via the LAN router and a first communication bus. In the present invention, the master computer, the master embedded computer and the slave embedded computers can detect faults interactively. Safety and reliability of the operation of the surgical robotic system can be improved without increasing any additional detection components, and communication burden of the system can be effectively reduced. The present invention can be widely applied to a minimally invasive surgical robotic system.

Abstract: A method for suppressing current leakage in a memory includes a column redundancy evaluation which is executed when a memory is powered on so as to find out a failed memory unit of the memory. A current path between the failed memory unit and a pre-charging power source is disconnected according to the column redundancy evaluation result. Thus, bit lines in the failed memory cells are not pre-charged to avoid current leakage occurred between bit lines and word lines in the failed memory cells.

Abstract: A latch circuit having three latch stages generates a majority output value from the stages, senses when the latch stage outputs are not all equal, and feeds the majority output value back to inputs of the latch stages to reload the latch stages. The latch circuit uses a not-equal gate whose output is an error signal that can be monitored to determine when a single-event upset has occurred. A master stage is controlled by a first multiplexer which receives one system clock signal, while a slave stage is controlled by a second multiplexer which receives another system clock signal, and the latch stage outputs are connected to respective inputs of the not-equal gate, whose output is connected to second inputs of the multiplexers. The latch circuit is part of a latch control system, and reloading of the latch stages takes less than one cycle of the system clock (less than 500 picoseconds).

Abstract: An anomaly detector detects anomaly of a first device. A second device reset part, in case that anomaly has been detected by the anomaly detector, resets a second device. A first device reset part, in case that anomaly has been detected by the anomaly detector, resets a first device. Further, a collating part collates data generated by the first device with data generated by the second device, and judges anomaly when these data are in disagreement with each other. A reset part, in case that the anomaly has been judged by the collating part, resets the second device.