Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: A system and method are disclosed for generating triggers within a hardware emulator. The system allows for dynamic reconfiguration of the trigger generation scheme during emulation. In one aspect, input probe signals are received on an address port to a memory from an integrated circuit within the emulator. The memory outputs from a data port, data, which is addressed, at least in part, by the input probe signals. The data output from the data port may be sent through further combinatorial logic or directly connected to a logic analyzer and represents trigger information. In another aspect, the trigger generation scheme may be reconfigured dynamically during emulation. For example, where the memory is a dual-port RAM, an emulation host can write to the memory to perform the reconfiguration.

Abstract: A method and system of supporting and testing equipment distant from the support system are provided. The method includes the steps of forming a communications link between the equipment and the support system, using the support system to measure performance of the equipment and to provide a set of performance data, providing library data relating to the equipment, comparing the performance data with the library data and analysing the compared data whereby to provide a performance diagnosis of the equipment, all in a substantially continuous real time operation.

Abstract: A system and method are used to provide uncorrelated code hopping in a communications system. A shift register receives data. The shift register is clocked to shift the data. A scaler performs a scaling operation on the data with a numerical value of active codes. A truncator truncates the scaled data to its seven most significant bits to produce a pseudo random hop number. A code matrix shifter circularly shifts the active codes in a code matrix based on the pseudo random hop number to produce a circularly shifted code. A transmitter transmits the circularly shifted code.

Abstract: In one embodiment, the invention is a method and apparatus covering a multilayer process space during at-speed testing. One embodiment of a method for selecting a set of paths with which to test a process space includes determining a number N of paths to be included in the set of paths such that at least number M of paths in N for which testing of the process space will fail, computing a metric that substantially ensures that the set of paths satisfies the requirements of N and M, and outputting the metric for use in selecting the set of paths.

Abstract: This disclosure describes methods, systems and software that can be used to calculate the estimated mean time to data loss for a particular configuration of a disk group. For example, a system can be used to evaluate a plurality of configurations, and/or to select (and/or allow a user to select) an optimal configuration of the disk group, based, in some cases, on the relative estimated mean times to data loss of the various configurations. This can allow, if desired, the configuration of the disk group to minimize the likelihood of data loss in the disk group.

Abstract: Exemplary methods and computer recovery readiness evaluation process relate to a virtual recovery testing process for Disaster Recovery Plans (DRPs) that can be executed by technical generalists. As such, by implementing the DRP virtual testing process a technical generalist can be charged with the tasks of evaluating and validating documented DRP assumptions, plan execution steps, interoperability dependencies/requirements in addition to the availability of applications, application specific vaulted vital records, and hardware systems that are referenced within the recovery logic of a DRP. Further, the use of established DRP problem management processes to addresses anomalies & deficiencies can also be accomplished.

Abstract: At least one exemplary embodiment is directed to implementing personalized sound management applications. A module comprising hardware and software is provided to manufacturers to build a device. A process is architected for remote enabling of a device with personalized sound management applications. Consumers select applications for managing their sound environment through purchased and subscription hardware and applications via a web environment. All products developed by manufacturers are tested and certified running the personalized sound management applications. Manufacturers and consumers may both be covered under for liability insurance. Users may remotely purchase may update, purchase hardware, add and download subscription based applications, and replace consumable through the web environment.

Abstract: An apparatus and method are described for sending serialized command in an environment where ESD or other phenomenon might cause malfunctions. Commands are encoded where there are at least two bit changes between any two commands. In this example, each command code that is different from legal commands by only one bit is an illegal command, Illustratively, if six bits provide 64 codes for commands, and only eight codes are used for legal commands, there will be 56 illegal command codes. Illustratively, any command code, that is only one bit different from a legal command, will be an illegal command. In practice a illegal command may be detected, and the system may recover. An illegal command due to and ESD event may be defined, and when detected a recovery process may be entered. When data (not command) are being sent, error detecting and correcting bits may be employed.

Abstract: In a method of initializing a computer memory that receives data from a plurality of redrive buffers, a predetermined data pattern of a selected set of data patterns is stored in selected redrive buffers of the plurality of redrive buffers. Each of the selected set of data patterns includes a first initialization data pattern and an error correcting code pattern that is a product of a logical function that operates on the first initialization data pattern and an address in the computer memory. The selected set of data patterns includes each possible value of error correcting code pattern. A redrive buffer of the plurality of redrive buffers that has stored therein an error correcting code pattern that corresponds to the selected address is selected when sending an first initialization data pattern to a selected address. The selected redrive buffer is instructed to write to the selected address the first initialization data pattern and the error correcting code pattern that corresponds to the selected address.

Abstract: A multithreaded computer application provides more robust mutually exclusive accesses as instantiations (threads) of a single program, such that deadlock situations are avoided. The application method uses the system primitives to implement system services that provide a ‘gate’ functionality (S1, S4, S6, S21, S24, S30) to the functional code for which exclusive access is to be granted. Critical sections still exist, but they are only used for the management of state variables and decisional branching of this ‘gate’ mechanism. Also, time limit provisions (S 15) are implemented to avoid blocking of the not granted threads. The method includes executing the ‘exclusive functional code section’ outside the critical sections, which avoids a cascading of blocking effects due to a never ending or non-terminating critical section as in the prior art design model.

Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present invention describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

Abstract: A device is disclosed for testing the function of a display port. The device includes a display port transmitting part, a field programmable gate array, and a memory. The display port transmitting part transmits connecting signals to a display port timing controller mounted on a display panel. The field programmable gate array applies a test signal to the display port timing controller, and controls the connecting signals applied from the display port transmitting part to the display port timing controller. The memory has software that determines acceptance or rejection of the display port function based on data output from the display port timing controller in response to the connecting signals or the test signal.

Abstract: An integrated circuit that includes a controller and multiple internal circuitries, whereas the integrated circuit is characterized by further including a security mode determination unit that includes multiple one time programmable components for defining a security mode out of multiple possible security modes, whereas a selected circuitry mode affects access to an internal circuitry. A method for testing an integrated circuit, the method includes: receiving a request to access an internal circuitry; and responding to the request in view of a defined security mode; whereas the method is characterized by a stage of defining a security mode of a debug circuit out of multiple security modes, whereas the definition is responsive to at least a state of multiple one time programmable components.

Abstract: The present invention provides a method for improving Hybrid Automatic Repeat Request (HARQ) uplink transmission in a user equipment (UE) of a wireless communication system. The method includes the HARQ entity of the UE instructing an HARQ process to perform transmission or retransmission of a transport block according to an uplink (UL) grant allocated to the UE, and flushing all HARQ buffers for uplink transmission in the HARQ entity when a Time Alignment Timer of the UE expires.

Abstract: A method for assessing the risk and cost for data loss and disaster recovery (DR) plans includes providing an application having a graphical user interface (GUI) comprising first and second windows arranged adjacent to each other. The first window comprises a catalog of components used to generate data disaster recovery (DR) configurations and the second window displays the generated DR configurations. A first DR configuration is generated in the second window and components are added to the first DR configuration by dragging and dropping components from the catalog into appropriate locations of the second window. Metrics for the first DR configuration are calculated and reported in the second window. A second configuration is also similarly generated in the second window and the metrics results are graphically compared to each other.

Abstract: A wireless device for implementing Incremental Redundancy (IR) operations includes an IR memory dedicated to storing data related to the IR operations. The IR memory includes a Type I IR memory adapted to store IR status information of a Radio Link Control (RLC) data block and a Type II IR memory adapted to store the RLC data block.

Abstract: Systems and methods are provided to implement fault tolerant data processing services based on active replication and, in particular, systems and methods for implementing actively replicated, fault tolerant database systems in which database servers and data storage servers are run as isolated processes co-located within the same replicated fault tolerant context to provide increased database performance.

Abstract: The method includes predetermining an output enable time period by measuring the maximum settling time when a signal is read during a transition from 0 to 1 or vice versa, and multiplying the maximum settling time by a safety factor 2.5, to set an output enable time period; reading and latching an input value; and transmitting the latched value onward after the predetermined output enable time period. An embodiment of the apparatus 10 includes two inverters 12, 14 and two pass gates 16, 18 and connected to a line 20 at its input. The pass gates 16, 18 are connected in a multiplexer configuration. A third pass gate 30 for connecting line 32, carrying the (inverted) output B of the metalatch, to further circuit portions, according to a 2-bit output enable signal applied to control lines 34, 36 respectively. In alternate embodiments, other logic circuit portions already provided can perform the function of pass gate 30.

Abstract: Embodiments of the invention provide methods and systems for improving the reliability of data stored on disk media. Logical redundancy is introduced into the data, and the data within a logical storage unit is divided into sectors that are spatially separated by interleaving them with sectors of other logical storage units. The logical redundancy and spatial separation reduce or minimize the effects of localized damage to the storage disk, such as the damage caused by a scratch or fingerprint. Thus, the data is stored on the disk in a layout that improves the likelihood that the data can be recovered despite the presence of an error that prevents one sector from being read correctly.

Abstract: A main step is retrieved from an operations process subject to verification. Mapping information is referenced to further retrieve a preventive measure against an error expected upon execution of the main step. Based on the order in which the preventive measure is executed within the operations process, it is determined whether the preventive measure has been incorporated into the operations process at a correct position and a result of the determination is output.

Abstract: A fault tolerant/fault resilient computer system includes a first coserver and a second coserver. The first coserver includes a first application environment (AE) processor and a first I/O subsystem processor on a first common motherboard. The second coserver includes a second AE processor and a second I/O subsystem processor on a second common motherboard.

Abstract: A semiconductor integrated circuit, including a data input unit for receiving an input data signal to be supplied to an external data input terminal, a storage unit for storing the input data signal received by the data input unit, a timing generating unit for generating a timing signal in response to an output request signal, a data output unit for outputting, in synchronization with the timing signal, the input data signal stored in the storage unit as an output data signal, a test output control unit for outputting, in synchronization with the timing signal, and a data selector for outputting the output data signal supplied from the data output unit to the external data output terminal in a normal operation mode and outputting the input data signal supplied from the test output control unit to the external data output terminal in a test mode.

Abstract: Contemplated validation systems provide access to a master validator, one or more remote validators, and an authorized party such that validation using a validation script can be performed in a flexible manner that allows modifications to the script in real time. Typically, modifications are requested by a remote validator in the field where the remote validator can not answer a validation request generated by the validation script in a proper or predetermined manner. A master validator will receive the request and modify the validation script accordingly to allow the validation to proceed. Most typically, modification of the script is authorized by an authorized party.

Abstract: A ULP offload engine system, method and associated data structure are provided for performing protocol offloads without requiring a TCP offload engine (TOE). In an embodiment, the ULP offload engine provides iSCSI offload services.

Abstract: An electronic circuit, including: a logic circuit having a plurality of logic cells; storage cells able to form a shift register, able to be connected to the logic cells; a connection control module having an input for the reception of an identification key, the module connecting the storage cells so as to form a test shift register when the receive input receives a valid identification key, and the module connecting the storage cells so as to form randomly a diversion circuit when the input does not receive a valid identification key. The invention allows the electronic circuit to be protected against fraudulent access in read or write mode. The invention also relates to a smart card including this electronic circuit.

Abstract: Formulating an integrated disaster recovery (DR) plan based upon a plurality of DR requirements for an application by receiving a first set of inputs identifying one or more entity types for which the plan is to be formulated, such as an enterprise, one or more sites of the enterprise, the application, or a particular data type for the application. At least one data container representing a subset of data for an application is identified. A second set of inputs is received identifying at least one disaster type for which the plan is to be formulated. A third set of inputs is received identifying a DR requirement for the application as a category of DR Quality of Service (QoS) class to be applied to the disaster type. A composition model is generated specifying one or more respective DR QoS parameters as a function of a corresponding set of one or more QoS parameters representative of a replication technology solution. The replication technology solution encompasses a plurality of storage stack levels.

Abstract: A system that select tests to exercise a given computer system is described. During operation, the system tests the given computer system using a set of tests, where a given test includes a given load and a given cycling time selected from a range of cycling times. Moreover, for the given test, the system monitors a stress metric in the given computer system. Additionally, the system selects at least one of the tests from the set of tests to exercise the given computer system based on the monitored stress metric.

Abstract: A semiconductor integrated circuit has a terminal to input a debug signal which specifies a debug mode, a reset circuit to generate a reset signal when a power is turned ON, and a debug mode control circuit to output a control signal which causes a shift to the debug mode based on the debug signal and the reset signal. The debug mode control circuit includes a latch circuit to generate a first signal by latching the debug signal, and a register circuit to generate a second signal when written with a permit code, and the control signal is generated based on the first signal and the second signal.

Abstract: Methods and apparatuses for encoding data in a wireless communication system including receiving an information sequence, and encoding the received information sequence to generate three subblocks of sequences. A first subblock of the three subblocks is the information sequence, a second subblock of the three subblocks is an encoded sequence, and a third subblock of the three subblocks is an interleaved and encoded sequence. The method further includes permuting the three subblocks of encoded sequences separately by subblock permutation, and continuously mapping the three subblocks into a circular buffer, the circular buffer including a first part, a second part, and a third part.

Abstract: A method of detecting and isolating a fault includes collecting information regarding utilization of a resource of a device. The method further includes predicting the fault based on the information and modifying operation of the device in response to the fault.

Abstract: A load test method for a computer and apparatus are provided. The method includes acquiring control information indicating a type of a hardware resources required for executing a load test program and quantitative conditions determined for each type of the hardware resources, acquiring an assignment rule table specifying a set of rules for each of the various hardware resources to assign the hardware resources of the computer to a load test program, selecting a rule for each of the hardware resources from the acquired assignment rule table in such a manner that a load is imposed on a predetermined part of the computer, developing the load test programs by assigning the hardware resources of the computer to the load test programs based on the acquired control information and the selected rule for each of the various hardware resources, and executing in parallel the developed load test programs.

Abstract: A method for improving the performance for a streaming service by link-adaptation and power-control in a wireless packet network such as an Enhanced General Packet Radio Services (EGPRS) cellular network is described. In particular, the effects of a combined link adaptation and power control scheme (referred to as an error-based scheme) for achieving a target error rate, which is non-zero but low enough so that limited retransmission and error concealment techniques are effective, is presented.

Abstract: The present invention detects patterns that conform to the user conditions in cases where a disaster recovery constitution is constructed by connecting a plurality of sites. The design system is used in cases where the disaster recovery constitution is provided in a storage system. The site information acquisition section acquires information relating to the constitution in the sites and information relating to the connections between the sites, and stores the information in the site information table. The candidate pattern generation section generates candidate patterns for each of the parameters on the basis of the site information table and a basic pattern table. The candidate pattern evaluation section evaluates the respective candidate patterns by using the user condition table and presents patterns which conform to the user conditions to the user. The document output section generates a construction procedure and operating procedure on the basis of patterns selected by the user.

Abstract: Systems and methods of storing error correction data are provided. A method may include storing data at a first memory having a first non-volatile memory type. The method may also include determining error correction data related to the stored data. The method may further include storing the error correction data at a second memory having a second non-volatile memory type. The first non-volatile memory may have a slower random access capability than the second non-volatile memory.

Abstract: A system for testing a communication device includes a testing module, a measurement module, and a control module. The testing module transmits one or more first test signals based on a first test sequence. The measurement module acquires test data by receiving one or more second test signals that are based on the one or more first test signals. The control module initiates the first test sequence in response to receiving a start test signal from an analysis system. The control module transfers the test data to the analysis system in response to a transfer data request. The control module initiates a second test sequence while the analysis system is analyzing the test data. The testing module generates and transmits one or more third test signals based on the second sequence when the second test sequence has been initiated.

Abstract: A cache memory device that includes a cache which stores data and tag information specifying an address of stored data, includes a detection unit that detects an error by reading out the tag information when a writing/readout request of desired data occurs to the cache, a search unit that searches the tag information for an address of the desired data when no error is detected in the tag information as a result of error detection by the detection unit, a memory unit that stores an address of data that is to be replaced by the desired data, the address being contained in the tag information, when the address of the desired data is not contained in the tag information as a result of search by the search unit, and a control unit that requests an external unit to replace data with a use of the address stored by the memory unit.

Abstract: Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

Abstract: A set of fault records representing faults previously detected in an enterprise computer system is received and analyzed. The analysis comprises a variety of analytical operations and results in a report provided to a user, the report particularly including a set of fault sources identified as highly important to address, with respect both to the system as a whole and to particular categories of faults.

Abstract: A method of analyzing problem data from a computer application is disclosed. The method evaluates a memory dump, identifying call stacks within the memory dump that are related to application failures, creates a hash of the identified call stack and adds the hash to a database. The database may then be evaluated to look for trends in the error data such as whether the same call stack is causing problems.

Abstract: A system accesses a log of events on more than one computing system and scans these logs in an effort to determine the likely cause of various items of interest, events, or problems. These items of interest often include improper or frustrating behavior of a computer system, but may also include delightful or beneficial behaviors for which a user, group of users, company, service, or help desk seeks a cause. Once the likely source of the item of interest is found, a test may be performed to confirm the source of the problem and warning or corrective action taken.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: A method for testing a memory device is disclosed. The method includes: respectively writing at least one test data into a plurality of storage blocks in the memory device such that a plurality of first time written test data are stored in the storage blocks; in a read with write back test mode, reading the first time written test data from the storage blocks in the memory device and writing the plurality of first time written test data into the storage blocks to generate a plurality of second time written test data; and in a compress test mode, reading the plurality of second time written test data from the storage blocks by a compress test operation and determining whether the memory device operates erroneously according to the plurality of second time written test data and the test data.

Abstract: A debug circuit for a multi-mode circuit driven by a clock signal, with an input for a clock signal, and a debug signal generator arranged to generate for each of a subset of the modes of the multi-mode circuit a corresponding debug signal based on a clock signal provided at the input. The frequency of debug signals is dependent on the frequency of a clock signal provided at the input, and each debug signal selects its respective mode for a length of time longer than that of each other mode of the multi-mode circuit, or each debug signal selects its respective mode for a length of time shorter than that of each other mode of the multi-mode circuit.

Abstract: A nonvolatile memory includes a memory cell array having a plurality of memory cells, a read-out circuit outputting data stored in the memory cell array asynchronously in response to an input address signal, a selection circuit outputting an selection signal for selecting a location of the memory cell to be failed, an error making circuit receiving a test mode signal, making the data outputted from the read-out circuit fail and outputting the failed data in response to the selection signal when the test mode signal is activated, and outputting the data outputted from the read-out circuit when the test mode signal is not activated, a data latch circuit latching either the failed data or the data outputted from the read-out circuit and outputting the latched data, and an error correcting circuit detecting the error in the latched data, correcting the error, and outputting the corrected signal.

Abstract: A memory system, memory, and memory system command protocol are disclosed. Within the memory system, a memory controller communicates a command to the memory, the command being selected from a set of commands including a write command and a plurality of non-write commands. A Hamming distance value calculated between a digital value indicating the write command and a digital value indicating any one of the plurality of non-write commands is greater than 1.

Abstract: Methods, systems, and program products are provided for failback to a primary communications adapter. Embodiments of the present invention include receiving, in a driver for a primary communications adapter and a backup communications adapter, a link up event for the primary communications adapter; inferring that the primary communications adapter is capable of receiving packets; setting the backup communications adapter to idle; and activating the primary communications adapter. In typical embodiments, the primary communications adapter includes a plurality of linked communications adapters comprising an EtherChannel pseudo-adapter.

Abstract: An approach is provided that rejuvenates a software application to reduce the effects of software aging. An active replica corresponding to a software application is identified. If rejuvenation of the software application is appropriate, a new replica is created and state information is transferred from the active replica to the new replica. In addition, client requests are redirected to the new replica. After the state data has been transferred and requests have been redirected, the active replica is terminated. Once the active replica has been terminated, the new replica becomes the active replica. When rejuvenation is again proper, another new replica is created and the state data is transferred from the new active replica to the new replica and requests are redirected to the new replica. This process repeats whenever rejuvenation of the application is needed.

Abstract: A recording medium for storing start position information for each zone and a method of managing data using the information. In a disc having a plurality of zones which form a group, and a spare area which is allocated at the start portion or the end portion of the group for replacing defects, when start logical sector numbers of each zone are changed by slipping replacement during initialization or reinitialization, the information is stored in the defect management area to thereby increase the compatibility of the medium. In particular, by the method of managing data using information stored in a defect management area, generation of errors is prevented in reading or writing due to the change of a physical position of a real-recorded file which are caused by wrong calculation of the start logical sector numbers for each zone.

Abstract: A method for transmitting a signal in a wireless network includes sending a first signal from a first source to a first intermediate station. A second signal is sent from a second source to a second intermediate station. The first signal is additionally received by the second intermediate station. The second signal is encoded according to dirty paper coding (DPC) such that the first signal does not interfere with the transmission of the second signal. The first signal is sent from the first intermediate station to a first destination and simultaneously, the DPC encoded second signal is sent from the second intermediate station to a second destination.