Abstract: Methods and systems are disclosed for optimizing compilation efforts for design debug based on formal analyses. The method includes accessing a circuit design, automatically determining a segment as being a design region of interest, identifying a behavior within the segment for performing at least one verification test, compiling the segment without compiling a remainder of the circuit design, and providing performance indicators corresponding to the behavior within the segment based on the segment as compiled.

Abstract: Techniques for predicting the outcome of a storage management operation on a hyper-converged infrastructure (HCI) deployment are provided. In one set of embodiments, a computer system can retrieve a current storage resource state of the HCI deployment. The computer system can then execute a simulation of the storage management operation in view of the current storage resource state, where the executing includes performing one or more simulated data movements between one or more host systems in the HCI deployment. Upon completing the simulation, the computer system can generate a report including, among other things, a predicted result status of the storage management operation based on the simulation.

Abstract: Various embodiments provide for determining redundant logic in a circuit design based on one or more enable conditions of clock gates, which can be part of electronic design automation (EDA). In particular, some embodiments use one or more enable conditions (of the clock gates) with a satisfiability solver to determine redundant logic coupled to clock circuit elements gated by the clock gates.

Abstract: Embodiments relate to a system, program product, and method for integrating compiler-based testing in post-silicon validation. The method includes generating a test program through a device-under-test (DUT). The method also includes generating a plurality of memory intervals and injecting the plurality of memory intervals into the test program. The method further includes injecting a plurality of compiled test snippets into the test program and executing one or more post-silicon validation tests for the DUT with the test program.

Abstract: Machine learning techniques are employed to model test runs of an automated test platform in ways that allow for reliable identification of various types of test behavior such as, for example, whether certain classes of failures can be characterized as test flake.

Abstract: Embodiments are for using design context projection and wire editing in augmented media. Responsive to receiving an indication of an error in a design for an integrated circuit (IC), a localized area is extracted encompassing the error in the design. Augmented reality media of the localized area of the design is generated with a guide pattern, the localized area including objects. The augmented reality media of the localized area is caused to be presented in a three-dimensional (3D) projection on an augmented reality device for a user. Responsive to receiving at least one modification to the augmented media in the 3D projection, the design for the IC is updated with the modifications.

Abstract: A fault simulation system, a server (100), a user device (200) comprising a user interface and a wire controller (300), intended for teaching and validating practical knowledge in the long-distance training of vehicle (500) maintenance personnel, allowing the emulation or simulation of faults by manipulating the signals of the electronic system of the vehicle (500). Some embodiments of the invention are developed with the purpose of simulating the most diverse defects in vehicles, acting, for example, in the injection calculator module, air conditioning system, CAN bus system, dynamic stability control, ABS system, accelerator, speed governor, speed limiter, airbag system, fuel pump, gear selector lever, wiper nozzle, among others, enabling a highly realistic emulation of a fault scenario by manipulating the signals of the electronic communication system of the vehicle (500).

Abstract: An efficient and cost-effective method for usage of emulation machine is disclosed, in which a new concept and use model called debug station is described. The debug station methodology lets people run emulation using a machine from one vendor, and debug designs using a machine from another vendor, so long as these machines meet certain criteria. The methodology and its associated hardware hence are called a ‘platform neutral debug station.’ The debug station methodology breaks loose usage of emulation machines, where people can choose the best machine for running a design, and the best machine for debugging, and they do not need to be the same. Unlike the past, where people needed to run emulation and debug a design using same emulator from beginning to the end, the mix-and-match method described herein allows users to use emulators in the most efficient way, and often most cost effective too.

Abstract: An integrated circuit device is disclosed. The device includes a circuit configured to perform a function, a fault management component, at least one user register, an analog test bus component, a built-in self-test component, a safety monitor component, and gating logic. Additionally, the circuit is separated from the fault management component, the at least one user register, the analog test bus component, the built-in self-test component, the safety monitor, and the gating logic.

Abstract: In a display control device (10), an acquisition unit (21) acquires a value of a signal outputted from an apparatus (60) during execution of a control program (52) which controls the apparatus (60). A control unit (22) controls a display device (30) to display a code of the control program (52) on a screen (54), and to display the value of the signal acquired by the acquisition unit (21), on a portion in the code of the control program (52) which corresponds to the signal, in a format that enables distinction of a state of the apparatus (60) of the time the value of the signal is outputted.

Abstract: An automated method of detecting patterns corresponding to a plurality of real world business measures corresponding to a plurality of business processes, assessing the next instance of such measures and related business attributes, and describing the next best action to optimize business outcomes based upon a plurality of control parameters. The system operates by continuously abstracting input data from a process agnostic data system (PADS) that links real-world things, activities and processes, into a process agnostic measure store (PAMS) configured to accept measures data without limitation as to a specific process or a plurality of processes. The machine self-learning system can then automatically project a business outcome, suggest most relevant attributes that can impact the said outcome, and suggest actions to change such outcome(s).

Abstract: A computer implemented method of modifying a compiled design of an electronic circuit is disclosed. The method includes accessing a stored compilation representing the design, and causing the computer to generate a modified version of the stored compilation in response to an indication of a change to a portion of the design.

Abstract: Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.

Abstract: A system, method and computer program product for installing a computer program within a computerized system of a car, the method comprising: installing a computer program on an emulator comprising a multiplicity of sub systems, each emulating a car sub system; executing a scenario from a scenario library, thereby activating at least one of the sub systems until a stopping criteria has been met; monitoring inputs and outputs transmitted to or received from any of the sub systems; and subject to said executing being completed successfully, installing the computer program on one or more car sub systems.

Abstract: A software testing framework provides functionality for utilizing pre-existing tests to load and performance test a network service. Methods can be tagged with annotations indicating that they are tests, such as integration tests. The methods implementing the integration tests can also be tagged with other types of annotations that can be used to select individual tests for use in testing, such as annotations indicating whether a test is a positive or negative test, annotations specifying dependencies upon other tests, or annotations indicating that a test is a member of a test suite. The annotations can be utilized in conjunction with test selection criteria to select individual integration tests for use in load and performance testing of the network service. The selected integration tests can be deployed to and executed upon load-generating instances to execute the integration tests and generate requests to the network service at high throughput.

Abstract: Simulation or calculation to estimate activity per unit in a chip design, combined with estimation of the specific location or region in which the unit logic will be finally placed, provides for calculation of an estimation of the activity distribution within the floorplan. Activity distribution estimation can be performed with fine granularity (at a gate level), at coarse granularity (at a macro level), or at an intermediate granularity (at a network-on-chip unit level). The estimation is displayed, visually, to a user of a design tool. Furthermore, the estimation is used to make manual or automatic optimizations of the floorplan and the location and configuration of units within the floorplan.

Abstract: Methods of the present disclosure can include methods for prioritized path tracing in a statistical timing analysis of integrated circuits. Methods of the present disclosure can include: determining a required arrival time for a merge point in a statistical timing graph, the merge point having a plurality of associated input edges; calculating a plurality of edge slack distributions for each of the plurality of input edges and the required arrival time at the merge point; projecting a representative edge slack from each of the plurality of edge slack distributions; identifying a most critical input edge based on the plurality of representative edge slacks; generating a prioritized listing of input edges from lowest-value representative edge slack to highest-value representative edge slack; and tracing a next-most critical input edge of the prioritized listing, subsequent to tracing a path from the most critical edge to a source point.

Abstract: Mechanisms are provided for processing natural language content having a computer code segment. Natural language content is processed using a natural language processing (NLP) engine and a segment of content within the natural language content is identified that is not recognized by the NLP engine. The segment is analyzed to determine whether the segment contains computer code and, if so, a code segment annotation for the computer code is generated that provides a natural language description of functionality of the computer code in the segment. The code segment annotation is stored in association with the natural language content and natural language processing is performed using the NLP engine on the code segment annotation to further process the natural language content.

Abstract: Disclosed are a system and a method for performing a timing analysis of an integrated circuit (IC). An internal timing constraint of a logic device in a first signal pathway of a hierarchical entity in an IC design is determined based on a reference value and, if necessary, on library information. A first boundary timing constraint associated with the first signal pathway is derived based on the internal timing constraint and a second boundary timing constraint associated with the first signal pathway is derived based on the first boundary timing constraint and a target slack value for the internal timing constraint. A static timing analysis is performed using the second boundary timing constraint. Based on the analysis, a timing abstraction for the hierarchical entity is generated. A timing model for the IC design is generated using the timing abstraction and other timing abstractions for other hierarchical entities in the design.

Abstract: Exemplary embodiments disclose a method for generating an assertion based on a user program code. The method may include receiving a user program comprising at least one assertion directive, a compiled result of the user program, and architecture information of a processor, and generating, based on the compiled result of the user program and the architecture information of the processor, an assertion which states an operation that the processor needs to perform in accordance with a code of the user program indicated by each of the at least one assertion directive.

Abstract: Method and system are disclosed for repetitive circuit simulation. In one embodiment, a computer implemented method for performing multiple simulations of a circuit includes providing descriptions of connectivity, instants, signal activities, and statistical parameters of the circuit, parsing the circuit in accordance with the descriptions of connectivity, instants, signal activities, and statistical parameters of the circuit to form one or more circuit partitions, performing a first pass simulation of the one or more circuit partitions in accordance with a set of stimuli to generate a history of the first pass simulation, and performing subsequent simulation of the one or more circuit partitions using the history of the first pass simulation.

Abstract: Potential errors that might result from operating logic and/or memory circuits at an insufficient operating voltage are identified by electrically altering nodes of replica or operational circuits so that the electrically altered nodes are susceptible to errors. The electrically altered nodes in an embodiment are controlled using parametric drivers. A minimized operating voltage can be selected by operating at a marginal operating voltage and detecting a voltage threshold at which errors in the electrically altered nodes are detected, for example.

Abstract: A data receiver module receives, at a storage device simulator, a data transmission from a storage controller being tested. The data transmission includes data and metadata. The metadata is associated with the data. A signature receiver module receives a signature from the storage controller as part of the data transmission. The signature is used to distinguish the metadata from the data. A data/metadata determination module examines the data transmission and determines data from metadata using the signature. A metadata storage module stores the metadata of the data transmission on the storage device simulator in response to the data transmission including metadata. The data storage simulator includes a data storage device. A data discard module discards the data of the data transmission in response to the data transmission including data.

Abstract: A method and system for subnet defect diagnostics through fault compositing is disclosed. A testing apparatus generates callout data for an integrated circuit device under test. A computer received the callout data, which includes a list of faults. Each fault of the list of faults has associated with it one or more failures and/or conflicts. In order to explain the failures, two or more faults are selected and composited, yielding a composite fault having a composite conflict count. The composite fault is assigned a score based on the composite conflict count, which score determines a candidate composite that best explains the faults of the list of faults. This procedure may be repeated to explain all the failures.

Abstract: An asymmetric approach for compressing digital data, or digitized analog data, uses dictionary-based compression for a transmitter and receiver communicating over a lossy unidirectional communication channel. The transmitter is responsible for generating active dictionaries, selecting appropriate dictionaries for compressing data, retiring old dictionaries, and sending new dictionaries to the receiver. The receiver passively stores the dictionaries from the transmitter and uses the right stored dictionary to decompress data received from the transmitter, as indicated by instructions in the compressed data set.

Abstract: Techniques for performing multiprocessing/multithreaded concurrent fault simulation of large-scale integrated circuit (IC) designs are described herein. Specifically, an IC design's source files, coded in HDL (Hardware Description Language) and/or ESL (Electronic System-Level) languages, are compiled into a database; stuck-at, transition and/or inter-process communication faults are generated and equivalent faults are collapsed. Furthermore, all faults are partitioned into disjointed fault sets, and a plurality of worker processes (or threads) are created to process those fault sets concurrently. The worker processes can run either locally on a multiprocessor platform, or remotely on different computers that are connected via an intranet and/or the Internet. Moreover, each worker process creates a plurality of child threads to carry out the multithreaded concurrent fault simulation of the IC design.

Abstract: Mechanisms are provided for creating shift register definition from high-level model using high-level model simulation. The mechanisms initialize all potential scan chain latches, identify the latches in a given scan chain, and separate the scan chain latches into chunks. For each chunk, the mechanisms identify the latches within the chunk that change at each shift. The mechanisms isolate the scan path latch when divergence occurs.

Abstract: A method and system for subnet defect diagnostics through fault compositing is disclosed. Each fault contained in callout data comprises explain failure data and conflict counts. A first fault on a fan-out sink of a fan-out net that explains a first failure is selected from the callout data. A second fault on a different sink of the same fan-out net that explains a second failure that the first fault does not explain is selected. The first fault and the second fault are composited to yield a composite fault. The composite fault unions the failures explained by the first fault with the failures explained by the second fault. A composite conflict count is generated by combining the conflict count of the first fault and the conflict count of the second fault, and a score is assigned to the composite fault. A best candidate composite fault is determined based on the score.

Abstract: A computer-implemented method, computer program product, and computing system for defining one or more failure conditions. Two of more executions are selected from a plurality of available executions based upon a simulation modeling file, thus defining two or more selected executions. A first of the two or more selected executions is executed while monitoring for the occurrence of the one or more failure conditions.

Abstract: A multimedia testing system is described herein that uses a virtual hardware driver to test software application behavior using virtual hardware in place of physical hardware devices. The virtual hardware driver receives customized input patterns that emulate behavior and formatting of data from a wide variety of hardware devices. For webcams, the system can send a steady stream of frames like those that would be provided as output from a physical webcam. A test environment can observe software interaction with the received customized input patterns to determine how the software will interact with various physical hardware devices. Thus, the multimedia testing system allows automated testing of a software application that interacts with multimedia hardware without physically buying and installing hardware devices.

Abstract: A method and apparatus are provided for an embedded wireless interface that is embedded in, for example, one of an input and output controller device for controlling input and output communications with off-board devices, within a memory controller device and a processor motherboard. The embedded wireless interface may be utilized as a wireless test access point to provide signal stimulations for test purposes or to monitor communications over a specified wired communication link.

Abstract: Methods, systems and computer program products for CPU signaturing to aide in performance analysis. Exemplary embodiments include a performance analysis method including identifying a workload having one or more testcases, assigning a CPU signature to each of the one or more testcases, calling a CPU signature application programming interface that toggles the CPU to generate the CPU signature, passing four parameters to the CPU signature application programming interface, prior to running each of the one or more testcases of the workload, generating the CPU signature, dynamically determining a run order of the one or more testcases at a run time of the workload and reviewing performance data during the running of each of the one or more testcases, each of the one or more testcases being identifiable by its respective CPU signature.

Abstract: The simulation method includes a step of measuring a predetermined characteristic from a real device by using test equipment that supplies a test signal to a device-under-test (DUT); a step of saving Response Data generated from measurements obtained by measuring in a file; and a step of verifying activities of a test plan program in a simulation system that simulates the test equipment by using the Response Data saved in the file.

Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.

Abstract: A method for server side logic unit testing in an application server environment is provided. The method includes reading a plurality of input parameters from an XML input repository, where the input parameters define an initial state of a test environment, and configuring the test environment to the initial state using the input parameters. The method further includes executing a unit test case using a command test manager to interface between the unit test case and the test environment, where the command test manager translates a command from the unit test case into a test command. The method also includes passing the test command to controller command logic, and accessing test data stored in a database through an access bean using a bean simulator. The method additionally includes receiving test results, including catching an exception on an error condition, and outputting the test results to an XML output repository.

Abstract: A method, system, and computer program product for automated root cause identification of a failure of a logic controller have been provided. The method includes receiving logic controller failure information, receiving a logic model of logic code for the logic controller, and mapping the logic controller failure information to the logic model to identify a logic failure model state. The method further includes determining a potential trigger of the failure of the logic controller as a root cause via tracing through at least one path in the logic model to reach the logic failure model state. The method also includes identifying the root cause in the logic code via mapping the root cause from the logic model to the logic code, and outputting the logic code with the identified root cause of the failure of the logic controller.

Abstract: Received read commands and address signals are respectively decoded into internal column strobe signals and internal address signals for reading data out of a data storage portion of a memory. A waiting interval during which a readout data becomes ready is simulated or a transmission path on which the readout data is transmitted is simulated. When the simulation result indicates the readout data is ready, an error check operation is performed on the readout data. The operation interval of the error check is simulated. When the simulation for the error check operation indicates that the error check is completed, an error check result is sent out of the memory.

Abstract: A diagnostic process applicable to VLSI designs to address the accuracy of diagnostic resolution. Environmentally based fail data drives adaptive test methods which hone the test pattern set and fail data collection for successful diagnostic resolution. Environmentally based fail data is used in diagnostic simulation to achieve a more accurate environmentally based fault callout. When needed, additional information is included in the process to further refine and define the simulation or callout result. Similarly, as needed adaptive test pattern generation methods are employed to result in enhanced diagnostic resolution.

Abstract: Disclosed are systems and methods for prognostic health management (PHM) of electronic systems. Such systems and methods present challenges traditionally viewed as either insurmountable or otherwise not worth the cost of pursuit. The systems and methods are directed to the health monitoring and failure prediction of electronic systems, including the diagnostic methods employed to assess current health state and prognostic methods for the prediction of electronic system failures and remaining useful life. The disclosed methodologies include three techniques: (1) use of existing electronic systems data (circuit as a sensor); (2) use of available external measurements as condition indicators and degradation assessor; and (3) performance assessment metrics derived from available external measurements.

Abstract: A system, method of automated testing and control of networked devices is provided. One or more test cases are defined in a test plan for execution against a plurality of networked devices. The test cases are created using a command defined grammar comprising verbs which characterize how commands or actions should be performed. Abstraction markers allow for device-specific characteristics to be mapped to a target device, without modification of the test cases and the test plan itself. The verbs and abstraction markers, once mapped to a target device form device-specific commands comprising actions and device-specific characteristics which are executed against the target networked device. The resulting responses are parsed against expected responses and a result or verdict is assigned. By providing command grammar and abstraction capability a common test plan and test cases can be applied across a range of diverse networked devices without require user intervention or modification.

Abstract: Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

Abstract: Technologies disclosed herein can be used to diagnose defects on die having both scan chain and system logic defects, including in situations where the presence of one or more faults in the system logic potentially obscures the detectability of one or more faults in the scan chains (or channels) and vice versa. At least some embodiments employ an iterative approach where at least some scan chain faults are identified, these chain faults are used to identify system logic faults, and then additional chain faults are identified using the system logic faults and vice versa. Failing bits can be partitioned into at least two groups: failing bits determined as being caused by system logic failures, and failing bits determined as being possibly caused by chain defects, system logic defects, or the compound effects of both types of defects.