Abstract: Analyzing a distributed computer system, wherein said distributed computer system comprises at least one hardware unit to process data, an interconnection network and at least one processing unit to initialize said at least one hardware unit by using said interconnection network. According to the inventive method different trace files generated by components of said distributed computer system are post-analyzed and trace lines inside said different trace files belonging to the same action executed from at least one component inside said distributed computer system are identified by using unique key expressions, wherein an output file with context and/or time distribution information for different actions is generated by extracting trace lines representing cross process or cross controller calls and/or function calls for each related action based on an input file.

Abstract: According to an aspect of the embodiment, a switch for information acquisition, which is included in an information processing apparatus, inputs an acquisition instruction of information for a hung-up cause investigation. A trace information acquiring unit, which is included in the information processing apparatus, acquires trace information of a first target process, which is set in a trace information setting file. A core file generating unit, which is included in the information processing apparatus, generates a core file of a second target process, which is set in a core setting file.

Abstract: The present invention performance enhancement and reliability maintenance system and method pushes a processor to its maximized performance capabilities when performing processing intensive tasks (e.g., 3D graphics, etc). For example, a clock speed and voltage are increased until an unacceptable error rate begins to appear in the processing results and then the clock speed and voltage are backed off to the last setting at which excessive errors did not occur, enabling a processor at its full performance potential. The present invention also includes the ability to throttle back settings which facilitates the maintenance of desired reliability standards. The present invention is readily expandable to provide adjustment for a variety of characteristics in response to task performance requirements. For example, a variable speed fan that is software controlled can be adjusted to alter the temperature of the processor in addition to clock frequency and voltage.

Abstract: In the system, an apparatus for collecting trace information provided on a circuit executing a program includes a counter unit which increments a count value for each execution cycle of the program, and a collection unit outputs trace information at a fetching timing of the trace information outputted by the circuit and a count value of the counter unit at the fetching timing. Another apparatus for processing trace information includes a trace information acquisition unit which acquires the trace information added with a count value from a trace information collection apparatus, a sort processing unit which sorts the acquired trace information based on the count value, and a trace information storage unit which store the sorted trace information.

Abstract: A method for providing a virtual sensor network based system. The method may include obtaining project data descriptive of a virtual sensor network to be used in a control system of a machine; establishing a virtual sensor network including a plurality of virtual sensors based on the project data. Each virtual sensor may have a model type, at least one input parameter, and at least one output parameter. The method may also include recording model information, measurement data, and performance information of the virtual sensor network including the plurality of virtual sensors; creating one or more calibration certificates of the virtual sensor network including a plurality of virtual sensors based on the model information, the measurement data, and the performance information; and generating a documentation package associated with the virtual sensor network.

Abstract: A method for a computer including a processor that is capable of counting invalidation of translation lookaside buffers and generating an interrupt at the occurrence of the invalidation, the invalidation being performed by an operating system upon switching between application programs, includes acquiring identification information of application programs from the operating system and storing the identification information as a first list; detecting an interrupt generated from the processor at the occurrence of switching from a first application program to a second application program; and when the interrupt is detected, acquiring the identification information of the first and second application programs from the operating system or the mechanism and comparing the acquired identification information with the first list to determine whether either of the first and second application programs is a program that has been created or disappeared.

Abstract: A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data elements. The trace logic has trace generation logic operable to generate trace elements for inclusion in the stream, and is further arranged to generate trace timing indicators for inclusion in the stream. Each trace timing indicator indicates the elapse of one or more processing timing intervals, the processing timing interval being a predetermined plurality of clock cycles.

Abstract: A system for identifying an exiting process and removing traces and shadow page table pages corresponding to the process' page table pages. An accessed minimum virtual address is maintained corresponding to an address space. In one embodiment, whenever a page table entry corresponding to the accessed minimum virtual address changes from present to not present, the process is determined to be exiting and removal of corresponding trace and shadow page table pages is begun. In a second embodiment, consecutive present to not-present PTE transitions are tracked for guest page tables on a per address space basis. When at least two guest page tables each has at least four consecutive present to not-present PTE transitions, a next present to not-present PTE transition event in the address space leads to the corresponding guest page table trace being dropped and the shadow page table page being removed.

Abstract: An electronic circuit includes a first processor (100) operable to perform processing operations, a first trace buffer (230) coupled to the first processor (100), a first triggering circuit (210) coupled to the first processor (100), the first triggering circuit (210) operable to detect a specified sequence of particular processing operations in the first processor (100); a second processor (101), a second trace buffer (231) coupled to the second processor (101), a second triggering circuit (211) coupled to the second processor (101), the second triggering circuit (211) operable to detect at least one other processing operation in the second processor (101); and a cross trace circuit (330) having a trace output and having inputs coupled to the first triggering circuit (210) and to the second triggering circuit (211), the cross trace circuit (330) configurably operable to respond to a sequence including both a detection of the sequence of particular processing operations of the first processor (100) by the fir

Abstract: A method is disclosed for forecasting the behavior of an information technology system for executing a plurality of applications. In an embodiment, the method comprises the steps of monitoring (110) the execution of selected applications over a predefined time period, compiling (120) a trace of events indicating unintended behavior of the system during said period, determining (130) a correlation between an initial event and a subsequent event in said trace and forecasting (140) a recurrence of the subsequent event based on said correlation in response to a recurrence of the initial event. This facilitates a user to avoid or at least reduce the risk of future occurrence of events that may have a detrimental impact on the performance of the IT system.

Abstract: A monitoring device accesses a database storing, for each of a plurality of failure cases that occurred in a monitored device, a group of past monitoring data items each representing respective measured values of monitoring items of the monitored device measured until a time of occurrence of a failure case. The device receives, from the monitored device, a current monitoring data item representing current measured values of the plurality of monitoring items. The device calculates, for each of past monitoring data items stored in the database, a similarity degree between a past monitoring data item and a current monitoring data item on the basis of the respective measured values of the plurality of monitoring items. The device determines, among the plurality of failure cases, a failure case predicted to occur in the monitored device, on the basis of the calculation result. The device outputs the determination result.

Abstract: There is provided a trace/failure observation system which is capable of comprehensive collection of information that is needed for checking a desired operation in a system or the like where the amount of information to be observed is large, and which allows easy analysis of the desired operation. The system includes, in a system LSI to be subjected to trace/failure observation: an event detecting means for observing behavior of a portion to be observed; a first data reducing means for performing observation data reduction processing so that observation data from the event detecting means has an amount of information processable to a second data reducing means; and the second data reducing means for performing one or more steps of observation data reduction processing.

Abstract: A system includes a platform domain implementing address-indexed operations and an application domain implementing application context-oriented operations. The platform domain includes a platform interconnect to process address-indexed platform transactions and a trace monitor to generate a debug trace stream from platform transactions based on their platform context information. The application domain includes a processing component and a queue manager to queue descriptors for data frames to be processed by the application domain, each descriptor having application context information including application-specific debug information for the corresponding data frame.

Abstract: A method of generating timestamped trace messages includes generating a trace message in response to an event at an instruction pipeline of a data processing device. If timestamping is enabled, timestamps are only included in the trace message only if a programmable condition is detected. For example, a timestamp can be included in the trace message if the amount of space used to store messages at a trace message buffer exceeds a watermark value. The condition that results in a timestamped trace message is programmable, and can be selected via a debug interface. Because timestamps are only included in trace messages when the programmable condition is satisfied, some trace messages will not include a timestamp, thereby reducing the amount of buffer space needed to store the trace messages.

Abstract: Various embodiments of the present invention provide systems and methods for determining storage medium health. For example, a storage device is disclosed that includes a storage medium and a data processing circuit. The data processing circuit receives a data set derived from the storage medium. The data processing circuit includes a data detector circuit, a data decoder circuit, and a health detection circuit. The data detector circuit receives the data set and provides a detected output. The data decoder circuit receives a derivative of the detected output and provides a decoded output. The health detection circuit receives an indication of a number of times that the data set is processed through the combination of the data detector circuit and the data decoder circuit.

Abstract: Systems and methods that automatically identify causes of errors during one or more CAD processes, such as while binding external reference drawings to a host drawing and/or batch comparing sets of multiple drawings. In certain examples, a first session of a CAD program can be used to track potential crash occurrences during a second CAD program's processing of a set of drawings and dynamically replace corrupt drawings and/or broken references with blank (proxy) drawings so that the desired process can complete. Whenever the first CAD session detects a potential error event, such as when the second CAD session is interrupted for a particular length of time, the first CAD session can log the error, close the second session, and/or continue the desired process with a new CAD session.

Abstract: Systems and methods for automatic determination of out of memory handling situations are provided. A system and method can include receiving data that includes one or more memory allocations or one or more pool heaps and running a test on the data to capture one or more tracebacks. If the one or more tracebacks are unique, then the one or more unique tracebacks are added to a list. The test is run a second time on the first traceback on the list to determine a result that indicates correct execution or incorrect execution with respect to memory handling. The result is stored in a computer-readable storage medium.

Abstract: In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.

Abstract: A monitoring apparatus includes: a reception section that receives information including first use mode information from an first information processing apparatus; a storage section that stores the first use mode information received by the reception section; and a transmission section, when the reception section receives fault information together with the first use mode information from the first information processing apparatus, that transmits information concerning countermeasures against a fault to the first information processing apparatus based on the first use mode information and pieces of second use mode information, stored in the storage section, of second information processing apparatuses which normally operate.

Abstract: A semiconductor integrated circuit comprising a processor having an output signal of instruction log information and being operable in a program in memory is disclosed. The semiconductor integrated circuit comprises trace determination circuit for comparing an instruction code that corresponds to the instruction log information from a processor with an instruction code that is read from the memory to detect faults.

Abstract: A system for monitoring error notification function comprising: an information processing apparatus including: a first processor including error notification function for generating error information indicative of an error occurred at least one component in the information processing apparatus; a first communication unit for sending the error information; and a management server including; a second communication unit for receiving the error information from the information processing apparatus; a second processor for monitoring the error notification function in accordance with a process including: instructing the information processing apparatus to generate a pseudo error command for urging the information processing apparatus to generate pseudo error information; wherein the second processor in the management server determines whether the error notification function in the system is operating properly or not by checking receipt of pseudo error information from the information processing apparatus.

Abstract: A method for providing a virtual sensor network based system. The method may include obtaining project data descriptive of a virtual sensor network to be used in a control system of a machine; establishing a virtual sensor network including a plurality of virtual sensors based on the project data. Each virtual sensor may have a model type, at least one input parameter, and at least one output parameter. The method may also include recording model information, measurement data, and performance information of the virtual sensor network including the plurality of virtual sensors; creating one or more calibration certificates of the virtual sensor network including a plurality of virtual sensors based on the model information, the measurement data, and the performance information; and generating a documentation package associated with the virtual sensor network.

Abstract: Disclosed is a method for adding performance counters to a .NET application after compilation of the .NET application to Common Intermediate Language code without a requirement for code changes to the original .NET application code or application recompilation from the development side. With regard to a further aspect of a particularly preferred embodiment, the invention may provide a method for adding the performance counters by declarative instrumentation of a .NET application at runtime or compile time, without the need for an application developer to hardcode instrumentation logic into the application. An instrumentation configuration file provides declarative definition for performance counters that are to be added to a particular application, and particularly includes a complete list of performance counters that need to be added and settings for each performance counter.

Abstract: A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.

Abstract: Disclosed is a clinical diagnostic analyzer employing a redundant error detection capability to further examine the internal message traffic for possible errors or questionable results by comparing the actual parameters against a fingerprint generated for each assay using an assay database and a configuration file. This testing does not rely on inputs from the software module being tested, and hence is an independent test. Further, a testing mechanism is provided to test the Redundant Error Detection (“RED”) capability itself.

Abstract: A data processing apparatus is provided having a plurality of processing circuits each having access to a memory. Tracing circuitry is provided for generating a stream of trace data for generating a stream of trace data corresponding to at least one of the plurality of processing circuits. Selection circuitry is provided to enable selective switching of the tracing circuitry from generating a first trace data stream corresponding to a first one of the plurality of processing circuits generating a second different trace data stream corresponding to a different one of the plurality of processing circuits. The selective switching is performed in dependence upon processing state information associating with one or more of the plurality of processing circuits. A corresponding method and computer program product are also provided.

Abstract: A method of storing data from a plurality of processors comprising the steps of (a) transferring data along a first bus (b) connectable between a first processor and a synchronising means and operable with a first protocol; (c) synchronising the synchronising means with a second processor; and (d) transferring the data along a second bus to a memory of the second processor wherein the second bus is connectable between the synchronising means and the memory of a second processor and operable with a second protocol.

Abstract: The present invention discloses systems and methods to maintain a multi-component system. The methods include defining a performance factor to be maintained in a given system, and collecting by agents associated with a given container in the system data associated with the performance factor. The collected data is then used to generate a statistical model that describes the normal operating condition of a given system corresponding to the desired performance factor to be monitored. The method also includes collecting real time data corresponding to the desired performance factor, and finding deviations between the real time data and parameters in the statistical model in a given time range. If a deviation is found, an alert is sent to the user to notify the user of such a deviation.

Abstract: An automation device having a diagnosis program for detecting operating and/or error statuses in hardware and/or software components of the automation device is disclosed. The diagnosis program is included in a Basic Input Output System of the automation device.

Abstract: An operations management apparatus which acquires performance information for each of a plurality of performance items from a plurality of controlled units and manages operation of the controlled units includes a correlation model generation unit which derives a correlation function between a first series of performance information that indicates time series variation about a first element and a second series of performance information that indicates time series variation about a second element, generates a correlation model between the first element and the second element based on the correlation function, and obtains the correlation model for each element pair of the performance information, and a correlation change analysis unit which analyzes a change in the correlation model based on the performance information acquired newly which has not been used for generation of the correlation model.

Abstract: A process for monitoring a machine, within the framework of a FMEA process for at least one component of the machine for at least one predetermined fault which can be diagnosed by means of a diagnosis diagram and a diagnosis system with sensors for detecting physical parameters of the machine, a diagnosis priority number being determined which is the product of the following index quantities: severity of the effect of occurrence of the fault with respect to the serviceability of the machine; expected machine-specific consequential costs when a fault occurs, and the possibility of correction of the fault. The diagnosis priority number is used in the evaluation of the diagnosis diagram, the diagnosis system, the current machine state, the necessary maintenance measures and/or the failure risk of the machine.

Abstract: A data processing apparatus and method for generating trace elements is provided. The data processing apparatus comprises a device for performing a sequence of operations including memory operations on data values having associated data addresses. For at least some of the memory operations the data address is determined relative to an architectural state value of an item of architectural state of the device. Trace logic is provided for receiving indications of the sequence of operations being performed by the device, and for generating from the indications a stream of trace elements. When for a memory operation the data address is determined to have been determined relative to an architectural state value of the item of the architectural state, the trace logic is operable dependent on that item of architectural state to omit at least one of a data address indication and a data value indication from the stream of trace elements generated in respect of that memory operation.

Abstract: A data processing apparatus having one or more trace data sources is provided in which the trace data sources operate to generate respective streams of trace data. At least one of said trace data sources comprises a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker generator is coupled to the trace data generator and operates to generate a synchronization marker and insert the synchronization marker into the trace data stream. The synchronization marker identifies a synchronization position in the trace data stream. A controller is coupled to the synchronization marker generator, and operates to initiate the synchronization marker generator to generate and insert a synchronization marker into the trace data stream. The controller controls initiation in dependence on behaviour of the data processing apparatus downstream of the trace data generator with respect to trace data flow.

Abstract: A data processing apparatus is disclosed, said data processing apparatus comprising a plurality of devices, trace logic associated with at least one of said plurality of devices, and tagging logic associated with at least one of said plurality of devices, said tagging logic being operable to: select at least one item, said at least one item comprising an activity to be monitored; provide said at least one selected item with tag data identifying said at least one item as an item to be monitored; and said trace logic being operable to: detect tagged items processed by said at least one device; and output trace information relating to at least some of said detected tagged items.

Abstract: A method and system for automatically developing a fault classification system from time series data. The sensors need not have been intended for diagnostic purposes (e.g., control sensors). These methods and systems are functionally independent of knowledge related to a particular equipment system, thereby allowing seamless application to multiple systems, regardless of the suite of sensors in each system. Because this algorithm is totally automated, substantial savings in time and development cost can be achieved. The algorithm results in a classification system and a set of features that might be used to develop alternative classification systems without human intervention.

Abstract: Trace circuitry, and a method of operating such trace circuitry, are provided for generating a trace stream indicative of activities of monitored circuitry of a data processing apparatus. The monitored circuitry produces data elements indicative of those activities, and the trace circuitry comprises trace element generation circuitry which is responsive to at least some of the data elements produced by the monitored circuitry to generate trace elements representative of those data-elements, with the trace elements generated being dependent on a selected trace mode of operation of the trace circuitry. Compression circuitry is then arranged to apply an encoding operation to a sequence of trace elements in order to produce a packet whose bit pattern represents the sequence of trace elements, and to cause that packet to be output in the trace stream, the encoding operation applied being dependent on a current compression scheme associated with the compression circuitry.

Abstract: A method, system, apparatus, and computer program product is presented for tracing operations. A set of related methodologies can be used within instruction tracing software, such as a tracing program, to reduce its tendency to generate interrupts that cause unwanted effects in the system that is being captured. A first methodology allows access to protected memory blocks so that instructions may be read from those memory blocks. A second methodology provides for the trace output buffer to be accessed using physical addressing. A third methodology traces only instruction addresses, which are resolved later during a post-processing phase of operation. A fourth methodology comprises multiple different methods for obtaining copies of instructions that have already executed rather than obtaining them before they are executed.

Abstract: A method is disclosed for adjusting trace data granularity. An initialization module sets a base granularity for trace data recorded for a component. A registration module registers a condition counter comprising a condition set. The threshold module sets a count threshold for the condition counter. An increment module counts each instance of the condition set. An adjustment module adjusts the granularity of trace data stored for the component to a modified granularity if the condition count exceeds the count threshold. In one embodiment, a timer module times an adjusted trace data granularity time interval. The adjustment module may set the granularity of the trace data to the base granularity when the adjusted trace data granularity time interval exceeds a specified time interval.

Abstract: This invention is to provide a technology for taking out trace information externally without lacking under the condition of limited output bandwidth. A semiconductor integrated circuit provided includes: a processing unit which can perform arithmetic processing according to a predetermined program and can output trace information with respect to the arithmetic processing; and a trace compression unit which can compress the trace information outputted from the processing unit. The trace compression unit includes a storage device, a comparator unit which can compare trace information stored in the storage device and the trace information newly outputted from the processing unit, and a trace information compression controller which can compress trace information to be externally outputted, based on the comparison result of the comparator unit.

Abstract: Disclosed is a remote monitoring diagnostic system in which a center and monitoring diagnostic units of a number of objects to be monitored are connected by a network. The center includes an algorithm forming unit for forming algorithms for monitoring, diagnosing, and operating each object to be monitored, a program group formation unit for forming monitoring, diagnostic, and operational programs from these algorithms, a transmitter for transmitting the programs in response to a request from the monitoring diagnostic unit, and a unit for forming information concerning prevention/maintenance form a diagnostic result and monitoring data from the monitoring diagnostic unit of each object to be monitored. The monitoring diagnostic unit of each object to be monitored includes a mobile program execution processor for executing the corresponding object to be monitored, and a transmitter for transmitting monitoring data to the center.

Abstract: Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not.

Abstract: Occurrence of a failure in a computer system is appropriately detected, and information required for removing the failure is automatically collected.

Abstract: A system accesses a log of events on more than one computing system and scans these logs in an effort to determine the likely cause of various items of interest, events, or problems. These items of interest often include improper or frustrating behavior of a computer system, but may also include delightful or beneficial behaviors for which a user, group of users, company, service, or help desk seeks a cause. Once the likely source of the item of interest is found, a test may be performed to confirm the source of the problem and warning or corrective action taken.

Abstract: A system and method for performance monitoring in processors is provided. The system and method evaluates the performance of the processor by counting selected events during one or more defined periods. The performance monitor provides improved performance characterization by providing highly-configurable start-stop control over the event counting.

Abstract: The present invention relates to computers executing in time-share mode, under the control of their operating systems, a number of separate and independent application programs. The present invention relates in particular to the networks of onboard computer networks of IMA type executing application programs written independently of the hardware specifications of the computers and not permanently resident in the computers. The method of the present invention associates with the digital core of each computer of the network a monitoring state machine operating independently and in having the monitoring state machine monitor the correct observance by the associated computer of the time sequencing of the tasks and memory partition allocations. Furthermore, the monitoring state machines can be configured to execute monitoring service applications of time-out or watchdog type to which the application programs executed by the computers of the network can subscribe.

Abstract: A data relay device relays a read request from a source device to a destination device and relays data corresponding to the read request from the destination device to the source device. The data relay device monitors elapsed time from a time point at which a read request is relayed to the destination device. When the elapsed time reaches warning time or error time, the data relay device sends a warning message or an error message to the source device.

Abstract: A hardware-information acquisition part, in the case of modification or addition to hardware configurations of semiconductor manufacturing devices to be managed, obtains that update information. To check the range of influence of a failure, as a first step, a software-condition conforming device extracting part extracts devices which have installed software related to the failure. Then, a hardware-condition conforming device extracting part determines, according to the information obtained by the hardware information acquisition part, whether the extracted devices satisfy hardware conditions under which the failure occurs, and if so, extracts those devices as the ones affected by the failure. Accordingly, even in the case of modification or addition to hardware, it is possible to ensure traceability of failures or requirements and thereby to identify the range of influence of failures with efficiency and reliability.