Abstract: A DC/DC converter includes N inductors and N power modules which correspond to N phases. The N inductors each include a plurality of inductor chips that are electrically connected in parallel to each other. The plurality of inductor chips are mounted separately on a main mounting surface and a sub-mounting surface of a printed circuit board. The sub-mounting surface is opposite to the main mounting surface.

Abstract: A board design assistance device includes a design data acquirer to acquire design data for a printed circuit board, a first determiner to determine, based on the design data for the printed circuit board, whether a lengthwise direction of board fiber in the printed circuit board is perpendicular to a longitudinal direction of an electronic component mounted on the printed circuit board, a second determiner to determine, based on the design data for the printed circuit board, whether a wire is routed crosswise from a pad receiving the electronic component mounted on the printed circuit board, and a notifier to provide a notification including error information specifying an electronic component determined to have a longitudinal direction not perpendicular to the lengthwise direction of the board fiber and determined to be connected to a pad from which a wire is not routed crosswise.

Abstract: Apparatuses may include a device substrate including a microelectronic device and bond pads proximate to an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball positioned and configured to carry a high-bandwidth data signal or a high-frequency clock signal may be located laterally or longitudinally adjacent to no more than one other ball of the ball grid array configured to carry a high-bandwidth data signal or a high-frequency clock signal. Each ball positioned and configured to carry a high-bandwidth data signal may be located only diagonally adjacent to any other balls configured to carry a high-bandwidth data signal or a high-frequency clock signal.

Abstract: The present disclosure relates to a system and method for electronic design. Embodiments may include receiving, using at least one processor, a plurality of distinct electronic designs at an electronic design database and storing the plurality of distinct electronic designs at the electronic design database. Embodiments may further include receiving a request to reuse one of the plurality of distinct electronic designs from a client electronic device associated with a user, wherein the request includes design connectivity information, block connectivity information, and page connectivity information. Embodiments may also include analyzing the design connectivity information, block connectivity information, and page connectivity information to identify one or more closest matches with the plurality of distinct electronic designs and providing the one or more closest matches to the client electronic device to allow for subsequent displaying at a graphical user interface.

Abstract: A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes generating a second circuit representation model based on updating the plurality of impedance values between the one or more port-pairs based on a second value for one or more parameters of the plurality of parameters of the circuit component, and updating the second circuit representation model by tuning the updated plurality of impedance values of the between the one or more port-pairs based on a predetermined use context of the circuit component in a circuit.

Abstract: A data processing apparatus includes means configured to obtain shaping data including a plurality of shaping models, means configured to obtain a predetermined condition, shaping model extraction means configured to extract a shaping model group including a plurality of shaping models which satisfy the predetermined condition from among the plurality of shaping models, and processing means configured to add shaping data of an additive model which associates a plurality of shaping models included in the shaping model group to each other to shaping data of the plurality of shaping models included in the shaping model group.

Abstract: Systems and methods related to scheduling of tasks for execution in parallel based on geometric reach are described. An example method includes processing information pertaining to connectivity among superconducting components and nodes included in a shared floor plan to generate a plurality of areas of reach, where each of the plurality of areas of reach corresponds to a portion of the shared floor plan. The method further includes generating a plurality of inflated areas of reach by inflating each of the plurality of areas of reach based on a target inductance of wires for routing signals among the superconducting components and the nodes included in the shared floor plan. The method further includes scheduling parallel execution of tasks for routing wires among a subset of the superconducting components and the nodes within any of the plurality of inflated areas of reach satisfying a geometric constraint.

Abstract: A high frequency flexible flat cable includes a first metal isolation layer, a first low-k dielectric adhesive layer attached to one side of the first metal isolation layer, a second low-k dielectric adhesive layer attached another side of the first metal isolation layer and at least two conductor layers respectively attached to the first low-k dielectric adhesive layer and the second low-k dielectric adhesive layer. In addition, the high frequency flexible flat cable further includes a third low-k dielectric adhesive layer, a fourth low-k dielectric adhesive layer, a second metal isolation layer and a third metal isolation layer. The second metal isolation layer and the third metal isolation layer are respectively adhered to outsides of the conductor layers by using the third low-k dielectric adhesive layer and the fourth low-k dielectric adhesive layer to adjust the impedance of the high frequency flexible flat cable according to requirements.

Abstract: Automated routing of signal nets for interposer designs. Signal nets are defined by their endpoints (bumps). The nets and their corresponding bumps are assigned to bump groups, based on the relative locations of the bumps and also based on length-matching constraints for the nets. Some of the bump groups may be “clones,” where the routing for one bump group may also be applied to its clone. In order for two bump groups to be clones, the bumps in the two bump groups must have a same relative position (i.e., same bump pattern), and the nets in the two bump groups must be subject to the same length-matching constraint. The routing through the interposer for one of the clones is determined, and that routing is then replicated for the other clones.

Abstract: Some examples described herein relate to a design system and a method for printed circuit board (PCB) design. In an example, a design system includes a processor and a memory coupled to the processor. The memory stores instruction code. The processor is configured to execute the instruction code to provide a workspace in a user interface in which a PCB design comprising multiple layers is capable of being created; provide a list of layout templates in the user interface; and provide an insert function, via the user interface, configured to insert a selected layout template of the list of layout templates into the workspace to be included in the PCB design. Each layout template of the list of layout templates is a tile layout that includes a layout component and metal lines that extend to one or more edges of the tile layout.

Abstract: A controlled-impedance printed circuit board (PCB) design program allows interactive movement of features from one of the vertically-stacked layers of the design to another layer in a graphical interface. The movement either moves a region of a layer of the PCB design, or moves an entire layer in a layer-swapping operation. The program computes modified widths of circuit traces of the first layer of the controlled-impedance printed circuit board design according to an impedance control value of the controlled-impedance printed circuit board design and according to a new position of the circuit traces caused by a movement of the features of the first layer to the second layer. The program also checks for violation of reference plane requirements for critical signals and warns the designer if such a violation is present.

Abstract: A system, method, and executable program code are used to design a capital project having a plurality of components. An application programming interface receives, from one or more 3D design systems, design change data for a checked component in the plurality of components. One or more rules each provide a design constraint between the checked component and at least one other functionally-related reference component, the functional relationship being defined by an end user for the design of the specific capital project. A computing processor applies each of the rules to produce a determination whether the checked component satisfies the design constraint of the applied rule. Finally, data indicative of each such determination are stored in a database, for eventual transmission to one or more of the 3D design systems.

Abstract: An integrated circuit includes at least one first conductive feature and at least one second conductive feature. The second conductive feature has at least one extension portion, and the extension portion of the second conductive feature is protruded from the projection of the first conductive feature on the second conductive feature. The integrated circuit further includes at least one third conductive feature, and at least one first conductive via electrically connecting the third conductive feature and the extension portion of the second conductive feature.

Abstract: A planar dual die package includes a package substrate and first and second semiconductor dice disposed side by side on a first surface of the package substrate. Outer connectors are disposed on a second surface of the package substrate, and the second surface of the package substrate includes a command/address ball region and a data ball region. Each of the first and second semiconductor dice includes die pads disposed in a command/address pad region corresponding to the command/address ball region and in a data pad region corresponding to the data ball region. Each of the first and second semiconductor dice are disposed on the package substrate so that a first direction from the command/address ball region toward the data ball region coincides with a second direction from the command/address pad region toward the data pad region.

Abstract: There is provided a voltage drop simulation device including: a memory; and a processor coupled to the memory and the processor configured to: divide a conductive body in which a current to be supplied from a power source to elements arranged on a PCB flows into a plurality of meshes including at least one mesh whose size is different from other meshes, calculate voltage values of a plurality of measurement points set in the plurality of meshes, respectively, and calculate a voltage drop of each of the plurality of meshes by dividing, for each of the plurality of meshes treated as a target mesh, a difference between voltage values of a first measurement point included in the target mesh and a second measurement point included in an adjacent mesh that is adjacent to the target mesh by a distance between the first and second measurement points.

Abstract: Mechanisms for generating circuit paths are disclosed. A computing device obtains a nodal list that identifies a grid of nodes that is referenced to an area and that uniformly covers at least a portion of the area at a predetermined density. The computing device modifies the nodal list to identify a circuit path from a start node through a succession of neighbor nodes to an end node based on a waypoint list. For each of a plurality of iterations the computing device performs a bubble operation that includes identifying a first pair of nodes that are successive nodes in the circuit path and that are adjacent to a second pair of nodes out of the circuit path, and altering the circuit path to make the second pair of nodes part of the circuit path, such that the first pair of nodes are no longer successive nodes in the circuit path.

Abstract: To provide dynamic data flow programming for digital signal processing, data flow graphs are constructed from graph libraries. The libraries provide redirection to relevant setup functions so that nodes of a graph table can be instantiated and associated memory can be allocated in dynamic working memory. The nodes of the graph table are modular and should conditions change, the data flow graph can be dynamically altered to change the parameters applied to these nodes thereby altering their functionality and adjusting the behavior of the data flow programming in accordance with the prevailing conditions.

Abstract: The present invention relates to a circuit board for COF (Chip on Film) package, which is capable of preventing an influence of coupling noise on a core block of an integrated circuit. The circuit board may include: a base film defined a core block region overlapping a predetermined location of a core block within an integrated circuit and having the same area as or larger area than the core block; first routing patterns formed on the base film; and a first block pattern covering the core block region. The first routing patterns may be formed outside the first block pattern at the same layer as the first block pattern.

Abstract: A printed circuit board (PCB) layout method executed in a computing device obtains pins of a first electronic component that are connected to a second electronic component or third electronic components included in a T topology circuit. A model of the first electronic component is created according to the obtained pins and is modified to form extended nets of the first electronic component. Pin pairs and match groups are set. Wiring paths of the T topology circuit are determined according to the match groups. The wiring paths are output to an output device.

Abstract: A method includes receiving a design of an interposer having nets, probe pads, and micro-bumps. The nets connect the micro-bumps. The probe pads are initially unconnected to the nets. The method further includes initializing a first set to logically include the nets; processing the first set such that every net interconnecting more than two micro-bumps is divided into a plurality of nets and every two micro-bumps are interconnected by one net; calculating an untested length for each net in the first set; selecting a net N from the first set wherein the net N has the maximum untested length in the first set, the net N representing at least a portion of a net P of the nets; selecting a pair of probe pads that are unconnected to the nets; and connecting the pair of probe pads to the net P by two dummy nets.

Abstract: A method of locating faulty logic on a semiconductor chip is disclosed. The method may include determining failure rates for the semiconductor chip, which contain one or more logic elements. The method also may include determining a masking pattern using failure rates. The masking pattern may mask less than all of the logic elements using a determination method. The method may also include applying a test vector to a selected logic element, wherein the result from a test vector is compared to a reference.

Abstract: A system and method for coordinating multiple-user edits of shared digital data. A coordinating device may receive commands to edit shared digital data from multiple independently operated user computers. The coordinating device may determine that two or more of the commands from respective user computers are mutually exclusive, redundant or otherwise conflict. The coordinating device may incorporate one of the multiple commands into a global command queue and may annul the other(s). The coordinating device may transmit the global commands to all user computers to be executed locally for implemented the same shared digital data thereon.

Abstract: A circuit-design method for a PCB is provided. A first user input is obtained via a user interface of a layout tool, wherein the first user input indicates that an object of a circuit diagram of the PCB is selected in the user interface. A plurality of constraint settings corresponding to an attribute are obtained from a database according to the attribute of the object. The plurality of constraint settings are displayed in a window of the user interface. A second user input is obtained via the user interface, wherein the second user input indicates that one of the plurality of constraint settings is selected in the window. At least one constraint parameter corresponding to the selected constraint setting is assigned to the object, and a tag corresponding to the attribute of the object is attached to the object of the circuit diagram.

Abstract: An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

Abstract: A method (and related apparatus) includes receiving user input and generating at least one of schematic content for a circuit based on the received user input and a printed circuit board (PCB) layout based on the circuit. The method further includes generating a bill of material (BOM) for the circuit, and receiving a user selection of at least one of a computer-aided design (CAD) tool format and a PCB layout tool format. The method also includes receiving a user selection to include footprints for the components used in the schematic content or PCB layout and exporting at least one of the schematic content, and PCB layout as well as the PCB footprints to one or more files in accordance with the selected CAD and/or PCB layout tool format.

Abstract: An object of the present invention is to provide wiring board design system and wiring board design method to determine a component and a wiring pattern in real-time when designing a wiring on a circuit board. The wiring board design system provides a cloud service for a terminal which is used by users via a network. When to arrange components on the circuit board, while pushing out automatically wirings which are overlapped with the components on the arranging position, the wiring board design system secures a space on that can arrange the component. The wiring processing is performed automatically and the fine adjustment such as rotation, movement of arranged components is performed automatically if necessary. The processing for equalization is performed so as to be the equal wiring density on the circuit board.

Abstract: A method for determining an area of a region for receiving a heat sink on a surface of a chip-supporting substrate is disclosed. The method can include determining, in response to a specified voltage drop associated with substrate wiring, a first set of wiring cross-sectional areas and corresponding lengths that satisfy the specified voltage drop. The method can also include determining, by selecting, in response to a specified thermal resistance associated with substrate wiring and insulating layers, from the first set, a second set of wiring cross-sectional areas and corresponding lengths that satisfy the specified thermal resistance. The method can also include selecting, from a set of placement areas corresponding to the second set of wiring cross-sectional areas and corresponding lengths, a heat sink placement area that is greater than a lower size for a placement area and less than an upper size for a placement area.

Abstract: Techniques for enabling the dynamic reuse of printed circuit board designs are provided. A master printed circuit board design comprising a plurality of modular flexible designs is received. Additionally, a target design that includes ones of the plurality of flexible designs is identified. Subsequently, as the master design, or ones of the plurality of flexible designs within the master design, are modified, the target design is correspondingly modified. With some implementations, the master design is housed within a library. The library may be used to implement versioning capability for the flexible designs. With further implementations, the master design may itself be a target design.

Abstract: Various exemplary embodiments relate to a printed circuit board (PCB) comprising a ball grid array (BGA) of BGA pads on one side of the PCB, arranged in a grid pattern; through-hole vias, including a via pad, arranged in said grid pattern electrically connected to said BGA pads; a solder mask covering the via pad with an opening; a solder pad within said opening electrically connected to said via pad; and a two-lead component attached to said solder pad.

Abstract: A method includes: with a setting frequency set as an operating frequency of an LSI, selecting a capacitor having a lowest resonant impedance and a resonant frequency close to the setting frequency with reference to a capacitor characteristic database and installing one or more capacitors, each being the selected capacitor, as high frequency decoupling capacitors, the number thereof corresponding to a value obtained by dividing the upper limit of the power feeding line impedance by a resonant impedance of the capacitor.

Abstract: Techniques for optimizing application specific integrated circuit (ASIC) and other IC pin assignment corresponding to a high density interconnect (HDI) printed circuit board (PCB) layout are provided. Applying the techniques described herein, pin assignments may be systematically and strategically planned, for example, in an effort to reduce the PCB layer count and associated cost, increase signal integrity and speed, reduce the surface area used by an ASIC and its support circuitry, reduce plane perforations, and reduce via crosstalk when compared to conventional designs with an ASIC mounted on a multilayered PCB.

Abstract: An electronic apparatus may include a circuit board, a processor disposed on an upper surface of the circuit board, and a memory disposed on a lower surface of the circuit board, such that the lower surface of the circuit board where the processor is arranged overlaps an area corresponding to where the memory is disposed.

Abstract: Electrical equipment 1 includes a chassis 2 that has a bottom portion 3 and side portions 4 and 5, a printed circuit board 10 that is stored in the chassis 2 such that one principal surface 10a faces an inner surface 3a of the portion 3, a sealing resin 20 that is filled in internal space S formed by the chassis 2 and the circuit board 10, embeds the circuit board 10, and a flow suppression portion 8 that decreases a drift velocity of the resin 20 pressed into the space S through the resin injection hole 11, and that is provided in at least part of region A from a position immediately below the hole 11 in the inner surface 3a to an inner surface 4a of a side portion 4 closest to the hole 11 out of the side portions 4 and 5.

Abstract: A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.

Abstract: A control unit, e.g., for a motor vehicle, includes a circuit board, a high-impedance circuit component situated on the circuit board and having an impedance of 1 k? or higher in relation to ground of the control unit, and at least one conductive protection element electrically connected to ground and situated adjacent to the high-impedance circuit component. The protection element has a height within a protective distance from the high-impedance circuit component that is at least equal to the protective distance. A method for designing a circuit board of a control unit, and a computer program product for executing the method, include the steps of specifying a position of the high-impedance circuit component, and specifying a position of the protection element such that the protection element has a height within a protective distance from the high-impedance circuit component that is at least equal to the protective distance.

Abstract: A testing system for testing a layout of a power pin of a chipset on a circuit board includes a layout information obtaining module, a power pin sorting module, a transmission line sorting module, a transmission line length calculating module, and a report generating module. The layout information obtaining module obtains layout information of the printed circuit board. The power pin sorting module sorts the power pin from a number of pins of the chipset. The transmission line sorting module sorts transmission lines that are connected to the power pin and are located on outer layers of the printed circuit board. The transmission line length calculating module calculates a total length of the transmission lines sorted by the transmission line sorting module and compares the total length with a threshold length. The report generating module generates a testing report indicating whether or not the power pin is qualified.

Abstract: A method of designing a reflectarray including a substrate having a surface perpendicular to a predetermined axis, wherein elements are disposed on the substrate. The method obtains a reflection phase of the elements as a function of a design parameter such as element spacing, when a radio wave enters the arranged elements, and stores a relationship between the reflection phase and the design parameter in a memory. Here, the design parameter is equally set for the elements. The method repeatedly determines, for each of the elements, the design parameter of a specific element in accordance with the relationship. The function of the design parameter has a range of almost 360 degrees with respect to a range of the design parameter. The reflection phase is the continuous function of the element spacing such that two resonant points occur at which the reflection phase becomes zero.

Abstract: A method is used for designing a multilayered circuit substrate that generates a physical design layout. The physical design layout represents of at least one electrical circuit passing through a plurality of layers. Based on performance requirements of the electrical circuit, a maximum allowable stub length of a via in the electrical circuit is computed. The computer processor determines if a stub length of an existing via in the physical design layout of the electrical circuit is less than the maximum allowable stub length. If the computer determines that the stub length of the existing via is less than the maximum allowable stub length, the computer removes an external non-functional pad of the existing via from the physical design layout.

Abstract: A printed substrate design system includes: an EMI condition determination unit that compares an EMI characteristic derived by an EMI characteristic derivation unit with an EMI allowable condition, and determines whether the EMI characteristic of a printed substrate satisfies the EMI allowable condition; a substrate configuration change unit that changes an internal configuration of the printed substrate to obtain a changed configuration of the printed substrate in a case where the EMI condition determination unit has determined that the EMI allowable condition is not satisfied, and sets design information of the changed configuration of the printed substrate to design information for deriving the EMI characteristic in the EMI characteristic derivation unit; and an output unit that outputs a printed substrate configuration in a case where the EMI condition determination unit has determined the EMI allowable condition is satisfied.

Abstract: A computer-based method for setting electrical specification of signal transmission lines of a printed circuit board (PCB) layout is provided. Data recorded in an electrical specification file is imported. The electrical specification file records a number of chips, pins of each chip, and electrical specification corresponding to each chip. The PCB layout is searched to find the chips and the pins recorded in the electrical specification file. The electrical specification of signal transmission lines connected to the found pins is set according to the electrical specification corresponding to each chip.

Abstract: A wiring-design aiding method for causing a computer to execute generating paths for buses so that the buses do not cross each other with respect to a wiring area including at least one wiring layer, the paths being represented by corresponding graphics The computer further executes verifying, for each bus, whether wires for nets belonging to the bus are successfully extracted from a component to which the bus is connected; and recording, in the wiring area, graphics representing the nets belonging to a bus for which it is determined in the verification that all the nets belonging to the bus are successfully extracted. The bus-path generation is re-executed with respect to the bus for which it is determined in the verification that at least one of the nets is not successfully extracted.

Abstract: Embodiments of the invention place surface-mount devices such as decoupling capacitors, resistors or other devices directly on the underside of a ball grid array (BGA) electronic integrated circuit (EIC) package, in place of de-populated BGA pads.

Abstract: To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and usage, and design structures are disclosed herein. The method includes applying a first voltage polarity to an actuator of a Micro-Electro-Mechanical System (MEMS) structure to place the MEMS structure in a predetermined state for a first operating condition. The method further includes applying a second voltage polarity which is opposite from the first voltage polarity to the actuator of the MEMS structure during a subsequent operating condition.

Abstract: An information processing apparatus is configured to compute the shape of a conductive pattern to be formed on a board by a drawing apparatus that performs drawing on the board using conductive liquid droplets. The information processing apparatus includes an image data generation unit configured to generate image data in which dots each having a diameter determined according to a drawing condition of a conductive pattern by the drawing apparatus are arranged at respective positions which are indicated by data of a conductive pattern and at which conductive liquid droplets are to be landed.

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract: A printed circuit board for carrying high frequency signals. Conducting structures of the printed circuit board are shaped within breakout regions to limit impedance discontinuities in the signal paths between vias and conductive traces within the printed circuit board. Values of parameters of traces or anti-pads, for example, may be adjusted to provide a desired impedance. The specific values selected as part of designing a printed circuit board may match the impedance of the breakout region to that of the via. The parameters for which values are selected may include the trace width, thickness, spacing, length over an anti-pad or angle of exit from the breakout region.

Abstract: An access arbitration module includes a plurality of active component communication ports for communicating with a plurality of active components, and includes a passive component communication port for communicating with a passive component. The access arbitration module also includes switching logic defined to control transmission of access communication protocol signals between each of the plurality of active component communication ports and the passive component communication port, such that an authorized one of the plurality of active component communication ports is connected in communication with the passive component communication port at a given time, and such that non-authorized ones of the plurality of active component communication ports are prevented from communication with the passive component communication port at the given time.

Abstract: First and second pin groups are each formed from a plurality of pins associated with specific nets. Pins in the first pin group are to be wired to pins in the second pin group according to their associated nets. A candidate selection unit selects a set of pair candidates each specifying a first pair of pins in the first pin group and a second pair of pins in the second pin group. The first and second pairs of pins are associated with the same pair of nets, and their respective distances are within a specified range. A pair determination unit determines which pins in the first and second pin groups are to be wired in pairs, based on the pair candidates selected by the candidate selection unit.

Abstract: A board design aid device includes a calculating and correcting units. The calculating unit groups a plurality of layers in a multi-layer board into a plurality of pairs of layers based on design information of the multi-layer board, the plurality of layers being stacked and derives a difference of total amounts in respect to a board design element, each of the total amounts being related to each layer of a pair of layers of the plurality of pairs of layers, the board design element being related to a warp of the multi-layer board. The correcting units, based on the difference of the total amounts, corrects an amount of the board design element for at least one of layers among at least one of the plurality of the pairs of layers so that the difference of the total amounts of the board design element is maintained within a certain range.