Abstract: A method for determining a deformation of a resist in a patterning process. The method involves obtaining a resist deformation model of a resist having a pattern, the resist deformation model configured to simulate a fluid flow of the resist due to capillary forces acting on a contour of at least one feature of the pattern; and determining, via the resist deformation model, a deformation of a resist pattern to be developed based on an input pattern to the resist deformation model.

Abstract: Disclosed is an operating method of an electronic device which includes receiving a design layout for manufacturing the semiconductor device, generating a first layout by performing machine learning-based process proximity correction (PPC), generating a second layout by performing optical proximity correction (OPC), and outputting the second layout for a semiconductor process. The generating of the first layout includes generating a first after cleaning inspection (ACI) layout by executing a machine learning-based process proximity correction module on the design layout, generating a second after cleaning inspection layout by adjusting the design layout based on a difference of the first after cleaning inspection layout and the design layout and executing the process proximity correction module on the adjusted layout, and outputting the adjusted layout as the first layout, when a difference between the second after cleaning inspection layout and the design layout is smaller than or equal to a threshold value.

Abstract: A computing system may include a circuit design access engine configured to access a circuit design. The computing system may also include a duplicate section processing engine configured to partition the circuit design into multiple circuit sections and determine, from among the multiple circuit sections, an identical section set based on duplicate criteria. Circuit sections of the identical section set may satisfy the duplicate criteria with respect to one another. The duplicate section processing engine may further be configured to perform an OPC processing operation on a selected circuit section of the identical section set and apply an OPC result of the performed OPC processing operation for other circuit sections of the identical section set instead of or without performing the OPC processing operation on the other circuit sections of the identical section set.

Abstract: A system for modeling a semiconductor fabrication process includes at least one first processor and at least one second processor. The at least one first processor is configured to provide at least one machine learning (ML) model, which is trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample. The physical pattern sample is formed from the design pattern sample by using the semiconductor fabrication process. The at least one second processor is configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor.

Abstract: Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.

Abstract: A method including: obtaining an image of at least part of a substrate, wherein the image includes at least one feature of a device being manufactured in a layer on the substrate; obtaining a layout of features associated with a previous layer adjacent to the layer on the substrate; calculating one or more image-related metrics in dependence on: 1) a contour determined from the image including the at least one feature and 2) the layout; and determining one or more control parameters of a lithographic apparatus and/or one or more further processes in a manufacturing process of the device in dependence on the one or more image-related metrics, wherein at least one of the control parameters is determined to modify the geometry of the contour in order to improve the one or more image-related metrics.

Abstract: A method of enhancing a layout pattern includes determining a vector transmission cross coefficient (vector-TCC) operator of an optical system of a lithographic system based on an illumination source of the optical system and an exit pupil of the optical system of the lithographic system. The method also includes performing an optical proximity correction (OPC) operation of a layout pattern of a photo mask to generate an OPC corrected layout pattern. The OPC operation uses the vector-TCC operator to determine a projected pattern of the layout pattern of the photo mask on a wafer. The method includes producing the OPC corrected layout pattern on a mask blank to create a photo mask.

Abstract: A method for optimizing a patterning device pattern, the method including obtaining an initial design pattern having a plurality of polygons, causing at least some of the polygons to be effectively connected with each other, placing evaluation features outside the boundaries of the polygons, and creating a patterning device pattern spanning across the connected polygons based on the evaluation features.

Abstract: A method of generating a mask used in fabrication of a semiconductor device includes, in part, selecting a source candidate, generating a process simulation model that includes a defect rate in response to the selected source candidate, performing a first optical proximity correction (OPC) on the data associated with the mask in response to the process simulation model, assessing one or more lithographic evaluation metrics in response to the OPC mask data, computing a cost in response to the assessed one or more lithographic evaluation metrics, and determining whether the computed cost satisfies a threshold condition. In response to the determination that the computed cost does not satisfy the threshold condition, a different source candidate may be selected.

Abstract: Exposure apparatus includes illumination optical system and projection optical system for forming projected image with light from the illumination optical system. The illumination optical system forms, on pupil plane of the illumination optical system, light emission region including first and second regions. The projected image is composited from images including first image formed by first light from the first region and second image formed by second light from the second region. The first light and/or the second light is broadband light. Increase/decrease change in line width in the second image caused by defocus has different sign with respect to increase/decrease change in line width in the first image caused by defocus, and increase/decrease change in line width in image obtained by compositing the first image and the second image, which is caused by defocus, is decreased.

Abstract: According to one embodiment, a method for displaying an index value in generation of a mask pattern verification model includes: calculating a first index value using a plurality of images; estimating a model on the basis of the first index value and pattern information; calculating a second index value using the model; and displaying at least one of the first index value and the second index value.

Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

Abstract: Methods for fracturing or mask data preparation are disclosed in which a set of single-beam charged particle beam shots is input; a calculated image is calculated using a neural network, from the set of single-beam charged particle beam shots; and a set of multi-beam shots is generated based on the calculated image, to convert the set of single-beam charged particle beam shots to the set of multi-beam shots which will produce a surface image on the surface. Methods for training a neural network include inputting a set of single-beam charged particle beam shots; calculating a set of calculated images using the set of single-beam charged particle beam shots; and training the neural network with the set of calculated images.

Abstract: Methods for matching features in patterns for electronic designs include inputting a set of pattern data for semiconductor or flat panel displays, where the set of pattern data comprises a plurality of features. Each feature in the plurality of features is classified, where the classifying is based on a geometrical context defined by shapes in a region. The classifying uses machine learning techniques.

Abstract: Methods for generation of shape data for a set of electronic designs include inputting a set of shape data, where the set of shape data represents a set of shapes for a device fabrication process. A convolutional neural network is used on the set of shape data to determine a set of generated shape data, where the convolutional neural network comprises a generator trained with a pre-determined set of discriminators. The set of generated shape data comprises a scanning electron microscope (SEM) image.

Abstract: A semiconductor device comprising at least one modified cell block that includes a modified abutment region in which is provided a first continuous active region arranged along a first axis parallel to a vertical abutment edge for positioning adjacent other cell blocks to form a vertical abutment, including non-standard, standard, and modified cell blocks. The structure provided within the modified abutment region improves a structural and device density match between the modified cell block and the adjacent cell block, thereby reducing the need for white space between vertically adjacent cell blocks and reducing the total device area and increasing cell density.

Abstract: A method includes positioning adjacent first through fourth active regions in a cell of an IC layout diagram, the first active region being a first type of an n-type or a p-type and corresponding to a first total number of fins, the second active region being a second type of the n-type or the p-type and corresponding to a second total number of fins, the third active region being the second type and corresponding to a third total number of fins, and the fourth active region being the first type and corresponding to a fourth total number of fins. Each of the first and second total numbers of fins is greater than each of the third and fourth total numbers of fins, and at least one of the positioning the first, second, third, or fourth active regions is performed by a processor.

Abstract: A computer-readable medium includes a program code that, when executed by a processing circuitry, causes the processing circuitry to divide a layout of a semiconductor chip into a plurality of patches, generate a plurality of segments from a layout of each of the plurality of patches, wherein a first patch of the plurality of patches includes first segments and a second patch of the plurality of patches includes second segments, calculate hash values respectively corresponding to the first segments and the second segments by using a hash function, calculate bias values of segments having a first hash value from among the first segments, calculate a representative value based on the bias values, and apply the representative value to the segments having the first hash value from among the first segments.

Abstract: A method to improve a lithographic process for imaging a portion of a patterning device pattern onto a substrate using a lithographic projection having an illumination system and projection optics, the method including: (1) obtaining a simulation model that models projection of radiation by the projection optics, wherein the simulation model models an effect of an obscuration in the projection optics, and configuring, based on the model, the portion of the patterning device pattern, and/or (2) obtaining a simulation model that models projection of radiation by the projection optics, wherein the simulation model models an anamorphic demagnification of radiation by the projection optics, and configuring, based on the model, the portion of the patterning device pattern taking into account an anamorphic manufacturing rule or anamorphic manufacturing rule ratio.

Abstract: Aspects of the disclosed technology relate to techniques of hotspot detection. Pinching-type hotspot candidates and bridging-type hotspot candidates are first identified in the layout design based on predetermined criteria. Simulation is then performed to derive aerial image intensity values for a plurality of sites on each of the pinching-type and bridging-type hotspot candidates. Pinching-type hotspots are determined from the pinching-type hotspot candidates based on one or more machine learning models for pinching-type hotspots, and bridging-type hotspots are determined from the bridging-type hotspot candidates based on one or more machine learning models for bridging-type hotspots. The input vector for the machine learning models is the aerial image intensity values for the plurality of sites.

Abstract: A method of manufacturing a semiconductor device includes randomly placing a plurality of standard cells from a library in which the standard cells are pre-stored, designing an interconnection pattern in which the standard cells are connected randomly to each other, connecting the standard cells according to the interconnection pattern to generate a virtual layout, performing an optical proximity correction operation on the virtual layout using an optical proximity correction (OPC) model, and forming and verifying a mask corresponding to the virtual layout on which the optical proximity correction operation is performed.

Abstract: A method for optimization to increase lithographic apparatus throughput for a patterning process is described. The method includes providing a baseline dose for an EUV illumination and an initial pupil configuration, associated with a lithographic apparatus. The baseline dose and the initial pupil configuration are configured for use with a dose anchor mask pattern and a corresponding dose anchor target pattern for setting an illumination dose for corresponding device patterns of interest. The method includes biasing the dose anchor mask pattern relative to the dose anchor target pattern; determining an acceptable lower dose for the biased dose anchor mask pattern and the initial pupil configuration; unbiasing the dose anchor mask pattern relative to the dose anchor target pattern; and determining a changed pupil configuration and a mask bias for the device patterns of interest based on the acceptable lower dose and the unbiased dose anchor mask pattern.

Abstract: The present disclosure relates to lithographic apparatuses and processes, and more particularly to tools for optimizing illumination sources and masks for use in lithographic apparatuses and processes. According to certain aspects, the present disclosure significantly speeds up the convergence of the optimization by allowing direct computation of gradient of the cost function. According to other aspects, the present disclosure allows for simultaneous optimization of both source and mask, thereby significantly speeding the overall convergence. According to still further aspects, the present disclosure allows for free-form optimization, without the constraints required by conventional optimization techniques.

Abstract: Methods and apparatus for pattern matching and classification are disclosed. In one example of the disclosed technology, a method of performing pattern matching according to a puzzle-matching the methodology includes analyzing an original source layout pattern and determining a signature for the original source layout pattern. A target layout is scanned to search for one or more portions of the target layout that have a signature that matches or is similar to the signature of the original source pattern. Similar patterns are searched based on a signature comparison of the source pattern and the target layout. In some examples of the disclosed technology, it is possible to match partial context to the original source pattern. In some examples, matches can be made in the target layout for different orientations of layout.

Abstract: Embodiments disclosed are directed to systems and methods for modifying an electronic circuit design. According to embodiments, the method includes generating a circuit element of an electronic circuit layout on a graphical user interface, and generating an array group including a plurality of circuit elements. Each cell of the array group includes the same circuit element, and the array group is generated such that a change in at least one attribute of the array group is applied to each circuit element of the plurality of circuit elements.

Abstract: Systems, methods, and devices are described herein for integrated circuit (IC) layout validation. A plurality of IC patterns are collected which include a first set of patterns capable of being manufactured and a second set of patterns incapable of being manufactured. A machine learning model is trained using the plurality of IC patterns. The machine learning model generates a prediction model for validating IC layouts. The prediction model receives data including a set of test patterns comprising scanning electron microscope (SEM) images of IC patterns. Design violations associated with an IC layout are determined based on the SEM images and the plurality of IC patterns. A summary of the design violations is provided for further characterization of the IC layout.

Abstract: A search engine receives data describing reference geometry and generates a hash based on the reference geometry. A reference bloom filter is generated for the reference geometry based on the hash. The search engine performs a search to determine whether instances of the reference geometry are present in an integrated circuit (IC) layout. The search includes comparing the reference bloom filter with each one of a plurality of bloom filters corresponding to a plurality of subdomains of the IC layout. Based on results of the comparison, one or more subdomains of interest are identified and searched to determine whether the particular reference geometry is present in the subdomain.

Abstract: Methods of semiconductor device fabrication are provided. In an embodiment, a method of semiconductor device fabrication includes receiving a first mask design comprising a first mask function, determining a transmission cross coefficient (TCC) of an exposure tool, decomposing the TCC into a plurality orders of eigenvalues and a plurality orders of eigenfunctions, calculating a kernel based on the plurality orders of eigenvalues and the plurality orders of eigenfunctions; and determining a first sub-resolution assist feature (SRAF) seed map by convoluting the first mask function and the kernel.

Abstract: A semiconductor device including: first, second and third active regions a first gate structure over the first active region and a first part of the second active region; a second gate structure over the third active region and a second part of the second active region; a first cell region including the first gate structure, the first active region and the first part of the second active region; a second cell region including the second gate structure, the third active region and the second part of the second active region; a first border region representing an overlap of the first and second cell regions which is substantially aligned with an approximate midline of the second active region; the second gate structure overlapping the first border region; and there being a first gap which is between the first gate structure and the first border region.

Abstract: A method for reducing chemo-epitaxy directed-self assembly (DSA) defects of a layout of a guiding pattern, the method comprising expanding a shape of the guiding pattern by a predetermined distance in both lateral directions to form a fin keep mask, where the fin keep mask comprises a stand-alone mask.

Abstract: A method of manufacturing a semiconductor device is provided as follows. A mask layout for forming a target pattern of a multi-height cell including a rectangular notch is generated. A preliminary rectangular mask pattern corresponding to the rectangular notch is detected from the mask layout. The multi-height cell is formed of standard cells arranged and connected to each other in a direction and the rectangular notch is disposed between two adjacent standard cells. A hexagonal mask pattern is, in response to the detecting of the preliminary rectangular mask pattern, placed on at least one short side of the preliminary rectangular mask pattern to generate a combined mask pattern. An outer boundary of the combined mask pattern remains in the mask layout and corresponds to the rectangular notch of the target pattern. A target mask and the semiconductor device are formed based on the combined mask pattern.

Abstract: Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.

Abstract: In some embodiments, a design verification system is provided that is configured to perform actions for ensuring fabricability of a segmented design. The design verification system searches a proposed segmented design for a paintbrush pattern to determine a positive paintbrush loss, and searches for an inverse paintbrush pattern to determine a negative paintbrush loss. The design verification system combines the positive paintbrush loss and the negative paintbrush loss to obtain a total paintbrush loss that indicates whether or not the proposed segmented design is fabricable. If the total paintbrush loss indicates that the proposed segmented design is not fabricable, the design verification system updates the proposed segmented design based on a gradient of the total paintbrush loss.

Abstract: According to one embodiment, a mask pattern correction system includes the following configuration. A stress analysis circuitry divides a layout of a circuit pattern formed using a design mask formed in accordance with mask design data into correction regions, and acquires a displacement amount from the regions. A correction value calculation circuitry calculates a displacement correction value from the displacement amount. A correction map generation circuitry generates a correction map based on a correction value difference of the displacement correction values. A mask position correction circuitry allocates the regions to a layout of the circuit pattern, performs displacement correction of a mask pattern on the design mask by the displacement correction values, and creates a correction mask based on the displacement correction.

Abstract: A photolithography model used in an optical proximity correction process modifies an image output intensity of a point disposed along a two dimensional plane and having coordinates (x,y) in accordance with a gradient of a convolution of a mask value at the point and a sampling pattern function selected at the point. The sampling pattern function includes, in part, a first subset of sampling patterns and a second subset of sampling patterns. The first subset of sampling patterns includes first and second nodes. The second subset of sampling patterns include first and second antinodes. The gradient of the convolution of the mask value and the first and second nodes of the first subset are scaled by a first coefficient. The gradient of the convolution of the mask value and the first and second antinodes of the second subset are scaled by a second coefficient.

Abstract: Devices, methods, non-transitory computer readable media, and other embodiments are described for automatic gate-level functional safety (FS) analysis and associated circuit design operations. One embodiment involves accessing register transfer level (RTL) design data, and accessing a set of FS data associated with an initial circuit design describing one or more failure modes associated with a plurality of circuit elements, an associated FS design criterion for each failure mode of the one or more failure modes, and one or more associations between the plurality of circuit elements and the one or more failure modes. The embodiment then involves generating a gate-level netlist using the RTL design data, mapping the one or more associations between the plurality of circuit elements from the RTL design data and the one or more failure modes to the gate-level netlist, and generating an updated set of FS data using the mapping of the one or more associations to the gate-level netlist.

Abstract: A method for correction of an optical proximity effect, comprising: parsing and dividing the periphery of a design pattern to obtain segments to process; for a segment having a corner comprising a segment side (101) and an adjacent side (102) forming a corner relation with the segment side, setting a target point according to the following principle: when the length of the adjacent side (102) is greater than a preset length, the target point is set at the location of the outer end point (104) of the segment side; when the length of the adjacent side (102) is less than or equal to the preset length, the target point is set between the vertex (103) of the corner and the outer end point (104) of the segment side, and the less the length of the adjacent side (102), the further the target point from the location of the outer end point (104); and adjusting, according to a simulation difference of the target point, the design pattern until it conforms to a design target.

Abstract: An integrated circuit system-on-chip (SOC) includes a semiconductor substrate, a plurality of components made up of transistors formed in the substrate, and a plurality of interconnection lines providing electrical connectivity among the components. Use of a channel-less design eliminates interconnection channels on the top surface of the chip. Instead, interconnection lines are abutted to one another in a top layer of metallization, thus preserving 5-10% of chip real estate. Clock buffers that are typically positioned along interconnection channels between components are instead located within regions of the substrate that contain the components. Design rules for channel-less integrated circuits permit feed-through interconnections and exclude multi-fanout interconnections.

Abstract: Disclosed is an approach for implementing placement for an electronic design, where when a dragged object is moved into a desired area, existing objects in that location are automatically moved as necessary in correspondence to the movement of the dragged object. Existing objects are only moved if they are causing a spacing violation or overlap with the dragged object being moved, either directly or indirectly.

Abstract: A method of tailoring BEOL RC parametrics to improve chip performance. According to the method, an integrated circuit design on an integrated circuit chip is analyzed. The analysis comprises calculating Vmax for vias and metal lines in the integrated circuit design over a range of sizes for the vias and the metal lines. Predicted use voltage for applications on the integrated circuit chip is determined. The size or the location of at least one of the vias and the metal lines is tailored based on performance parameters of the integrated circuit chip.

Abstract: Aspects of the disclosed technology relate to techniques of pattern-based resolution enhancement. Surrounding areas for a plurality of geometric layout elements in a layout design are partitioned into geometric space elements. The plurality of geometric layout elements and the geometric space elements are grouped, through pattern classification, into geometric layout element groups and geometric space element groups, respectively. Optical proximity correction is performed for each of the geometric layout element groups and sub-resolution assist feature insertion is performed for each of the geometric space element groups. The results are applied to the plurality of geometric layout elements and the geometric space elements in the layout design.

Abstract: A mask layout is received. An interaction-free mask model is applied to the mask layout. An edge interaction model is applied to the mask layout. The edge interaction model describes an influence due to a plurality of combinations of two or more edges interacting with one another. A thin mask model is applied to the mask layout. A near field is determined based on the applying of the interaction-free mask model, the applying of the edge interaction model, and the applying of the thin mask model.

Abstract: According to one embodiment, a mask pattern verification method includes: calculating mask pattern data; calculating an optical image and a resist image; calculating a first feature amount and a second feature amount, using a plurality of algorithms; in each of the plurality of algorithms, comparing the first feature amount with a first threshold, and detecting a critical point candidate in a first pattern; in each of the plurality of algorithms, comparing the second feature amount with a second threshold, and detecting a critical point in the first pattern; and selecting at least one of the plurality of algorithms, and displaying a detection result of the critical point corresponding to a selected algorithm.

Abstract: Optical proximity correction (OPC) based computational lithography techniques are disclosed herein for enhancing lithography printability. An exemplary mask optimization method includes receiving an integrated circuit (IC) design layout having an IC pattern; generating target points for a contour corresponding with the IC pattern based on a target placement model, wherein the target placement model is selected based on a classification of the IC pattern; and performing an OPC on the IC pattern using the target points, thereby generating a modified IC design layout. The method can further include fabricating a mask based on the modified IC design layout. The OPC can select an OPC model based on the classification of the IC pattern. The OPC model can weight the target placement model.

Abstract: Disclosed are techniques for processing layout designs based on dynamically-generated lithographic models. Lithographic models are determined for a plurality of regions of a reticle prior to lithographic simulation. During lithographic simulation, lithographic models for a small area within a particular region are generated based on the lithographic models for the particular region, the lithographic models for one or more neighboring regions, and location information of the small area relative to the region and to the one or more neighboring regions. The lithography models comprise illuminating and imaging system models and mask electro-magnetic field models.

Abstract: A method comprises: defining a set of rules for an inspection and detection of a defect in two or more electronic devices on a semiconductor chip, the set of rules being based on a modulation transfer function providing a response as contrast versus spatial frequency of the pattern spacings of the two or more electronic devices on the semiconductor chip; generating two or more care areas for two or more pattern spacings of the electronic devices on the semiconductor chip using a hierarchical set of spacing rules; and inspecting the two or more pattern spacings of the electronic devices on the semiconductor chip for defects.

Abstract: A pattern sorting method used in OPC verification, comprises the following steps: obtaining sizes of comparison areas of patterns and extracting pattern boundaries; processing pattern boundaries; cutting off all the pattern edges outside comparison areas; setting grid sizes for filtering; setting directions for pattern boundaries; pattern division processing: dividing each pattern into 4 blocks of an equal size; recalculating the apexes of pattern boundaries in each block; implementing coordinate transformation for each block; calculating block characteristic values for each block; implementing rotating, upward and downward mirroring or leftward and rightward mirroring adjustment for blocks in accordance with corresponding block characteristic values; calculating overall characteristic values of patterns in accordance with various block characteristic values.

Abstract: A computer-implemented method for simulating a scattered radiation field of a patterning device including one or more features, in a lithographic projection apparatus, the method including: determining a scattering function of the patterning device using one or more scattering functions of feature elements of the one or more features; wherein at least one of the one or more features is a three-dimensional feature, or the one or more scattering functions characterize scattering of incident radiation fields at a plurality of incident angles on the feature elements.

Abstract: An integrated circuit (IC) may include a plurality of standard cells. At least one standard cell of the plurality of standard cells may include a power rail configured to supply power to the at least one standard cell, the power rail extending in a first direction, a cell area including at least one transistor configured to determine a function of the at least one standard cell, a first dummy area and a second dummy area respectively adjacent to two sides of the cell area in the first direction, and an active area extending in the first direction across the cell area, the first dummy area, and the second dummy area. A region of the active area, which is included in the first dummy area or the second dummy area, is electrically connected to the power rail.

Abstract: A method of performing a resolution enhancement technique such as OPC on an initial layout description involves fragmenting a polygon that represents a feature to be created into a number of edge fragments. One or more of the edge fragments is assigned an initial simulation site at which the image intensity is calculated. Upon calculation of the image intensity, the position and/or number of initial simulation sites is varied. New calculations are made of the image intensity with the revised placement or number of simulation sites in order to calculate an OPC correction for the edge fragment. In other embodiments, fragmentation of a polygon is adjusted based on the image intensities calculated at the simulation sites. In one embodiment, the image intensity gradient vector calculated at the initial simulation sites is used to adjust the simulation sites and/or fragmentation of the polygon.