Abstract: An integrated circuit product includes a first chip, a second chip, a third chip, a fourth chip, a fifth chip, a sixth chip, a seventh chip, and an eighth chip. The areas and constituent components of the first chip, the second chip, the third chip, and the fourth chip are substantially the same. The areas and constituent components of the fifth chip, the sixth chip, the seventh chip, and the eighth chip are substantially the same. The first chip, the second chip, the third chip, and the fourth chip are respectively arranged on the four sides of the integrated circuit product. The fifth chip, the sixth chip, the seventh chip, and the eighth chip are arranged in a central area of the integrated circuit product.

Abstract: A method of in situ point spread function (PSF) retrieval is disclosed which includes encoding 3D location of molecules into PSFs, receiving molecule-generated images containing PSFs, segmenting the images into sub-PSFs, initializing template PSFs from a pupil function, determining a maximum normalized cross correlation (NCC) coefficient (NCCmax) between the sub- and template PSFs, associating each of the sub-PSFs with a template PSF based on the NCCmax and storing the sub-PSFs in associated bins, aligning and averaging the binned sub-PSFs, applying a phase retrieval algorithm to the averaged sub-PSFs to update the pupil function, regenerating the template PSFs, repeating until a difference between a new and a prior generation pupil function is below a predetermined threshold, generating in situ PSFs from the last pupil function, and applying a maximum likelihood estimation algorithm based on the in situ PSFs and the sub-PSFs to thereby generate lateral and axial locations of molecules.

Abstract: An optical proximity correction (OPC) device and method is provided. The OPC device includes an analysis unit, a reverse pattern addition unit, a first OPC unit, a second OPC unit and an output unit. The analysis unit is configured to analyze a defect pattern from a photomask layout. The reverse pattern addition unit is configured to provide a reverse pattern within the defect pattern. The first OPC unit is configured to perform a first OPC procedure on whole of the photomask layout. The second OPC unit is configured to perform a second OPC procedure on the defect pattern of the photomask layout to enhance an exposure tolerance window. The output unit is configured to output the photomask layout which is corrected.

Abstract: Disclosed is a method for producing a wafer map. More specifically, the present invention relates to: a method for producing a wafer map used for manufacturing chips in the semiconductor field, wherein a geographic information system (GIS) technique is used to produce the wafer map; and a method and system for providing wafer test results using same. According to an embodiment of the present invention, a semiconductor wafer is formed as a map by using the GIS technique, a coordinate system used in the GIS is utilized to create a map of the same size as an actual semiconductor wafer, and each of various constituent elements constituting the wafer can be stratified to reflect the actual size of the element to create a wafer map in which each of the elements is geocoded.

Abstract: A method of improving mask data used in fabrication of a semiconductor device includes, in part, setting a threshold value associated with a defect based on stochastic failure rate of the defect, performing a first optimal proximity correction (OPC) of the mask data using nominal values of mask pattern contours, identifying locations within the first OPC mask data where stochastically determined mask pattern contours may lead to the defect, placing check figures on the identified locations to enable measurement of distances between the stochastically determined mask pattern contours, and performing a second OPC of the first OPC mask data so as to cause the measured distances to be greater than the threshold value.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A boundary condition between blocks is formulated by the Barycenter compact model. Boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.

Abstract: A method of generating an integrated circuit (IC) layout diagram of an IC device includes receiving the IC layout diagram of the IC device, the IC layout diagram including a gate region having a width across an active region. The width is divided into a plurality of width segments based on a location of a gate via, and a simulation is performed based on the IC layout diagram and including an effective resistance calculated using at least one width segment of the plurality of width segments.

Abstract: Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.

Abstract: Various embodiments described herein provide for a method and system for relative placement of components for a circuit layout by retrieving a data structure of a first circuit design, the data structure including a location of each component, determining a component characteristic for each component, and selecting a first group of two or more components having a shared component characteristic. Additionally, the method and system can instantiate a second circuit design and retrieve the data structure after the second circuit design is instantiated. The method and system include, for the second circuit design, calculating a first scaling factor and scaling each of the components of the first group from the first circuit design and placing the first group at a location in the second circuit design corresponding to location of the first group within the first circuit design.

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

Abstract: A method and system for measuring overlay in a semiconductor manufacturing process comprise capturing an image of a feature in an article at a predetermined manufacturing stage, deriving a quantity of an image parameter from the image and converting the quantity into an overlay measurement. The conversion is by reference to an image parameter quantity derived from a reference image of a feature at the same predetermined manufacturing stage with known overlay (“OVL”). There is also disclosed a method of determining a device inspection recipe for use by an inspection tool comprising identifying device patterns as candidate device care areas that may be sensitive to OVL, deriving an OVL response for each identified pattern, correlating the OVL response with measured OVL, and selecting some or all of the device patterns as device care areas based on the correlation.

Abstract: A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.

Abstract: A pattern grouping method may include receiving an image of a first pattern, generating a first fixed-dimensional feature vector using trained model parameters applying to the received image, and assigning the first fixed-dimensional feature vector a first bucket ID. The method may further include creating a new bucket ID for the first fixed-dimensional feature vector in response to determining that the first pattern does not belong to one of a plurality of buckets corresponding to defect patterns, or mapping the first fixed-dimensional feature vector to the first bucket ID in response to determining that the first pattern belongs to one of a plurality of buckets corresponding to defect patterns.

Abstract: In various embodiments, a training application generates a trained encoder that automatically generates shape embeddings having a first size and representing three-dimensional (3D) geometry shapes. First, the training application generates a different view activation for each of multiple views associated with a first 3D geometry based on a first convolutional neural network (CNN) block. The training application then aggregates the view activations to generate a tiled activation. Subsequently, the training application generates a first shape embedding having the first size based on the tiled activation and a second CNN block. The training application then generates multiple re-constructed views based on the first shape embedding. The training application performs training operation(s) on at least one of the first CNN block and the second CNN block based on the views and the re-constructed views to generate the trained encoder.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: In an embodiment, a method for optimizing an integrated circuit physical design for an integrated circuit. A physical design graph includes a plurality of physical design sub-configurations, each including a placement of a group of physical cells and having annotated characteristics. The method includes identifying, in the integrated circuit physical design, a first physical design sub-configuration including a first placement of a first group of the physical cells and having first annotated characteristics, the first annotated characteristics being outside target characteristics. The method includes selecting from the physical design graph, based on the first group of the physical cells and the target characteristics, at least a second physical design sub-configuration including a second placement of the first group of the physical cells and being within the target characteristics.

Abstract: Methods and apparatus for pattern matching and classification are disclosed. In one example of the disclosed technology, a method of performing pattern matching according to a puzzle-matching the methodology includes analyzing an original source layout pattern and determining a signature for the original source layout pattern. A target layout is scanned to search for one or more portions of the target layout that have a signature that matches or is similar to the signature of the original source pattern. Similar patterns are searched based on a signature comparison of the source pattern and the target layout. In some examples of the disclosed technology, it is possible to match partial context to the original source pattern. In some examples, matches can be made in the target layout for different orientations of layout.

Abstract: A method for generating and updating position distribution graph comprises: generating a position distribution graph according to a circuit bitmap and an exposure pattern, performing an exposure simulation according to the position distribution graph to generate an exposure result graph, comparing the circuit bitmap with the exposure result graph to generate a plurality of error distribution candidate graphs, selecting one of the error distribution candidate graphs to serve as an error distribution graph, and performing a zero-one integer programming to update the position distribution graph according to the circuit bitmap and the error distribution graph, wherein the updated position distribution graph is associated with the error distribution graph.

Abstract: A method of enhancing a layout pattern includes determining a target layout pattern comprising a disk shape associated with a hole. The method includes defining a polygon having a plurality of vertices on the disk shape. The plurality of vertices coincide with a boundary of the disk shape and the polygon is an initial layout pattern of the hole. The method includes performing an iterative correction of the initial layout pattern. The iterative correction includes projecting the layout pattern of the hole onto a substrate, determining an error between the target layout pattern and the projected layout pattern, and adjusting the layout pattern by moving the vertices of the polygon to generate a next iteration of the layout pattern. The method includes continuing the adjusting, projecting, and determining until a criterion is satisfied and a final iteration of the layout pattern of the hole is generated.

Abstract: According to one embodiment, a model training system includes a processor. The processor is configured to input a first image to a model and acquire a second image output from the model, and generate a third image by correcting the second image. The processor is configures to train the model by using the first image as input data and using the third image as teacher data.

Abstract: A mask layout is received. An interaction-free mask model is applied to the mask layout. An edge interaction model is applied to the mask layout. The edge interaction model describes an influence due to a plurality of combinations of two or more edges interacting with one another. A thin mask model is applied to the mask layout. A near field is determined based on the applying of the interaction-free mask model, the applying of the edge interaction model, and the applying of the thin mask model.

Abstract: Compute-in-memory (CIM) bit cell array circuits include CIM bit cell circuits for multiply-accumulate operations. The CIM bit cell circuits include a memory bit cell circuit for storing a weight data in true and complement form. The CIM bit cell circuits include a true pass-gate circuit and a complement pass-gate circuit for generating a binary product of the weight data and an activation input on a product node. An RWL circuit couples the product node to a ground voltage for initialization. The CIM bit cell circuits also include a plurality of consecutive gates each coupled to at least one of the memory bit cell circuit, the true pass-gate circuit, the complement pass-gate circuit, and the RWL circuit. Each of the CIM bit cell circuits in the CIM bit cell array circuit is disposed in an orientation of a CIM bit cell circuit layout including the RWL circuit.

Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.

Abstract: A routing process applied to design integrated circuits uses keep-through regions. Keep-through regions specify areas which metal shapes may overlap but where metal shapes may not have line ends. The keep-through regions are generated based on end-of-line rules applicable to routing of the design. These keep-through regions are then used in determining the layout of interconnects for the design.

Abstract: Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A boundary condition between blocks is formulated by the Barycenter compact model. Boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model.

Abstract: Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.

Abstract: The present disclosure provides a photomask and a method of forming a photomask, in which the photomask may obtain an optimized uniformity via a simplified process flow. The photomask includes a plurality of stair-like patterns parallel disposed with each other, wherein each of the stair-like patterns includes a plurality of first right angles at one side and a plurality of second right angle at another side opposite to the side, and each of the first right angles and each of the second right angles are not in a same vertical axis.

Abstract: According to one embodiment, a method of displaying model includes: sampling a pattern to acquire an attention point; calculating a spatial or planar distribution that indicates any one of a design density, a lithography target density, a mask transmittance, or an optical image intensity at N points (N being an integer equal to or greater than 1) on the pattern including the attention point; calculating a threshold for the pattern; estimating, based on the distribution and the threshold, N elements respectively corresponding to the N points as a model; and displaying the estimated model.

Abstract: A pixel cell includes a photodiode disposed in a pixel cell region and proximate to a front side of a semiconductor layer to generate image charge in response to incident light directed through a backside to the photodiode. A cell deep trench isolation (CDTI) structure is disposed in the pixel cell region along an optical path of the incident light to the photodiode and proximate to the backside. The CDTI structure includes a central portion extending a first depth from the backside towards the front side. Planar outer portions extend laterally outward from the central portion. The planar output portions further extend a second depth from the backside towards the front side. The first depth is greater than the second depth. Planes formed by each of the planar outer portions intersect in a line coincident with a longitudinal center line of the central portion of the CDTI structure.

Abstract: A noise map is used for defect detection. One or more measurements of intensities at one or more pixels are received and an intensity statistic is determined for each measurement. The intensity statistics are grouped into at least one region and stored with at least one alignment target. A wafer can be inspected with a wafer inspection tool using the noise map. The noise map can be used as a segmentation mask to suppress noise.

Abstract: A metrology target may include a first rotationally symmetric working zone with one or more instances of a first pattern and a second rotationally-symmetric working zone with one or more instances of a second pattern, where at least one of the first pattern or the second pattern is a Moiré pattern formed from a first grating structure with a first pitch along a measurement direction on a first sample layer and a second grating structure with a second pitch different than the first pitch along the measurement direction on a second sample layer. Centers of rotational symmetry of the first and second working zones may overlap by design when an overlay error between the first sample layer and the second layer is zero. A difference between the centers of rotational symmetry of the first and second working zones may indicate an overlay error between the first and second sample layers.

Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

Abstract: Disclosed is a method implemented with a computer system executing instructions for a semiconductor design simulation. The method includes generating a plurality of floor plans placing a plurality of circuit blocks differently, generating a plurality of power models from the plurality of floor plans, and selecting a layout corresponding to one of the plurality of floor plans by selecting at least one power model satisfying system requirements from among the plurality of power models.

Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.

Abstract: In one embodiment, a device obtains certificate information for a plurality of network addresses. The device constructs, based on the certificate information, a bipartite graph that maps nodes representing common names from the certificate information to nodes representing autonomous systems. The device determines edge counts from the bipartite graph for the nodes representing the autonomous systems. The device identifies, based on the edge counts, a particular one of the common names as botnet-related by comparing edge counts for the autonomous systems associated with that particular common name to edge counts for the autonomous systems associated with one or more of the other common names.

Abstract: A system may include a model calibration engine configured to determine a candidate lithography model set from which to calibrate a lithography model according to multiple objectives, including by initializing a population of parent candidate models, generating child candidate models, merging the parent and child candidate models into a merged population, classifying the candidate models of the merged population into tiers of non-dominated fronts according to respective objective functions for the multiple objectives, determining a subset of the merged population based on the classified tiers, and identifying, as the candidate lithography model set, a Pareto-optimal front of the subset of the merged population determined based on the classified tiers. The system may also include a model selection engine configured to set a given candidate lithography model in the candidate lithography model set as a calibrated lithography model for simulating a lithographic process.

Abstract: A system for reducing printable defects on a pattern mask is disclosed. The system includes a controller configured to be communicatively coupled to a characterization sub-system, the controller including one or more processors configured to execute program instructions causing the one or more processors to: direct the characterization sub-system to perform inspection of a mask blank; generate a cost function based on a first characteristic and a second characteristic, the first characteristic comprising areas of defect regions exposed by mask patterns, the second characteristic comprising pattern complexity of a design pattern; determine one or more values indicative of a minimum of the cost function via a non-linear optimization procedure; and generate one or more control signals to adjust rotation and translation of the mask blank relative to the design pattern based on the determined one or more values indicative of the minimum of the cost function.

Abstract: Methods, systems and computer program products for providing flexible constraint-based logic cell placement are provided. Aspects include determining a cell placement restriction rule that specifies an offset requirement between a first type of logic cell and a second type of logic cell. Responsive to placing a first cell that is the first type of logic cell within a semiconductor layout, aspects include tagging the first cell with the cell placement restriction rule. Aspects also include placing a second cell that is the second type of logic cell at an initial position within the semiconductor layout. Responsive to determining that the initial position of the second cell violates the cell placement restriction rule, aspects include repositioning the first cell or the second cell to a modified position within the semiconductor layout such that the modified position satisfies the cell placement restriction rule.

Abstract: A method and a system of performing layout enhancement include: providing a first design layout comprising a plurality of cells; updating a first cell in the plurality of cells using optical proximity correction to provide a first updated cell and a data set; updating a second cell from remaining cells in the first design layout based on the data set to provide a second updated cell; and manufacturing a mask based on the first updated cell and the second updated cell in the first design layout.

Abstract: An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in an layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: There is provided a system and method of examination of a semiconductor specimen using an examination recipe. The method includes obtaining a registered image pair, for each design-based structural element associated with a given layer, calculating an edge attribute, using a trained classifier to determine a class of the design-based structural element, and generating a layer score usable to determine validity of the registered image pair. There is also provided a system and method of generating the examination recipe usable for examination of a semiconductor specimen.

Abstract: In a method of manufacturing a photomask, a layout of a circuit mask pattern in a mask region corresponding to a chip region of a substrate is designed. A layout of a monitoring mask pattern representing a critical dimension (CD) of the circuit mask pattern in the mask region is designed. The monitoring mask pattern includes a mask-critical dimension uniformity (CDU) detection pattern configured to detect CDU in mask and a wafer-CDU detection pattern configured to detect CDU in wafer. A first optical proximity correction (OPC) is performed on the mask-CDU detection pattern. A second optical proximity correction is performed on the wafer-CDU detection pattern. A photomask having the circuit mask pattern and the monitoring mask pattern is formed.

Abstract: A mask process development having a consistent mask targeting is described. A method includes receiving an integrated circuit (IC) design. A test mask is generated that converts the IC design into one or more physical layouts. A set of one or more sub-resolution assist features (SRAFs) is inserted into the test mask. The set of one or more SRAFs is inserted into one or more other masks, which are derived from the test mask for mask targeting, such that the test mask and the one or more other masks include a same set of the one or more SRAFs.

Abstract: An integrated platform is provided that enables the various steps of development operations from design to sales, the virtualization, the visualization and the interpretation of a device so it may be fully created (designed), viewed, manipulated, packaged, simulated, tested, published and marketed right from within the platform. The resulting virtual device (VD) may be a multi-layered, -dimensional, -angular, -disciplinary, -documentarian, -service, manipulated and used in multiple ways. The provided VD may include visual representations of the VD via a traditional display device in a non-immersive environment and/or within an immersive environment via new virtual-reality (VR) devices. For instance, a user may create, manipulate, in real-time, layered multi-dimensional views of a VD in a virtual-reality, augmented-reality (AR), augmented virtual-reality (AVR), and/or mixed-reality (MR) environments.

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

Abstract: The disclosed computer-implemented method may include a display calibration apparatus. The display calibration apparatus may include a lens and an actively-cooled electromagnetic radiation detector configured to detect electromagnetic radiation emitted from various pixels of an electronic display panel under test. The electromagnetic radiation may travel through the lens prior to reaching the detector. The display calibration apparatus may also include a special-purpose computing device configured to: analyze the detected electromagnetic radiation from the pixels of the electronic display panel and generate calibration data for the electronic display panel using a specified calibration algorithm. As such, the electronic display panel may operate using the generated calibration data. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method, including: obtaining a set of conditions for a resist development model for simulating a resist development process of a resist layer; and performing, by a hardware computer system, a computer simulation of the resist development process using the set of conditions and the resist development model to obtain a characteristic of the development of the resist layer, wherein the computer simulation separately simulates different certain different physical and chemical processes and characteristics of the resist development process.

Abstract: Systems, methods, devices, and non-transitory media of the various embodiments enable converting massive mesh datasets that may carry a single material to a hierarchical format. Various embodiments may provide processing efficiency and scalability in creating hierarchical format representations of massive mesh datasets and/or in rendering massive mesh datasets.