Abstract: A method for verifying data plane programs is provided in some embodiments. Because the behavior of a data plane program (e.g., a program written in the P4 language) is determined in part by the control plane populating match-action tables with specific forwarding rules, in some embodiments, programmers are provided with a way to document assumptions about the control plane using annotations (e.g., in the form of “assertions” or “assumptions” about the state based on the unknown control plane contribution). In some embodiments, annotations are added automatically to verify common properties, including checking that every header read or written is valid, that every expression has a well-defined value, and that all standard metadata is manipulated correctly. The method in some embodiments translates programs from a first language (e.g., P4) to a second language (e.g., Guarded Command Language (GCL)) for verification by a satisfiability modulo theory (SMT) solver.

Abstract: Disclosed are systems and methods related to providing for the optimized software implementations of artificial intelligence (“AI”) networks. The system receives operations (“ops”) consisting of a set of instructions to be performed within an AI network. The system then receives microkernels implementing one or more instructions to be performed within the AI network for a specific hardware component. Next, the system generates a kernel for each of the operations. Generating the kernel for each of the operations includes configuring input data to be received from the AI network; detecting a specific hardware component to be used; selecting one or more microkernels to be invoked by the kernel based on the detection of the specific hardware component; and configuring output data to be sent to the AI network as a result of the invocation of the microkernel(s).

Abstract: This document relates to compilation of source code into services. One example method involves receiving input source code, identifying data dependencies in the input source code, and identifying immutability points in the input source code based at least on the data dependencies. The example method also involves converting at least some of the input source code occurring after the immutability points to one or more service modules.

Abstract: In one example, a computing system includes a device, the device including: a non-volatile memory divided into a plurality of selectable locations, each bit in the non-volatile memory configured to have corresponding data independently altered, wherein the selectable locations are grouped into a plurality of data lines; and one or more processing units coupled to the non-volatile memory, each of the processing units associated with a data line of the plurality of data lines, and each of the processing units configured to compute, based on data in an associated data line of the plurality of data lines, corresponding results, wherein the non-volatile memory is configured to selectively write, based on the corresponding results, data in selectable locations of the associated data line reserved to store results of the computation from the process unit associated with the associated data line.

Abstract: Techniques for an ultra-fact software compilation of source code are provided. A compiler receives software code and may divide it into code sections. A map of ordered nodes may be generated, such that each node in the map may include a code section and the order of the nodes indicates an execution order of the software code. Each code section may be compiled into an executable object in parallel and independently from other code sections. A binary executable may be generated by linking executable objects generated from the code sections. The methodology significantly differs from existing source code compilation techniques because conventional compilers build executable sequentially, whereas the embodiments divide the source code into multiple smaller code sections and compile them individually and in parallel. Compiling multiple code sections improves the compilations in order of magnitude from conventional techniques.

Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of data tracks. A plurality of access commands including a plurality of write commands are stored in a command queue, and the access commands are sorted into an execution order. A first write command is selected from the command queue based on the execution order, and a first part of the first write command is executed leaving a runt write command. The runt write command is executed between two of the sorted access commands so that the runt write command does not affect the execution order.

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

Abstract: A system for compiling programs for execution thereof using a hierarchical processing system having two or more levels of memory hierarchy can perform memory-level-specific optimizations, without exceeding a specified maximum compilation time. To this end, the compiler system employs a polyhedral model and limits the dimensions of a polyhedral program representation that is processed by the compiler at each level using a focalization operator that temporarily reduces one or more dimensions of the polyhedral representation. Semantic correctness is provided via a defocalization operator that can restore all polyhedral dimensions that had been temporarily removed.

Abstract: A hardware acceleration method includes: obtaining compilation policy information and a source code, where the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor, analyzing a code segment in the source code according to the compilation policy information, determining a first code segment belonging to the first code type or a second code segment belonging to the second code type, compiling the first code segment into a first executable code, sending the first executable code to the first processor, compiling the second code segment into a second executable code, and sending the second executable code to the second processor.

Abstract: A hardware acceleration method includes: obtaining compilation policy information and a source code, where the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor, analyzing a code segment in the source code according to the compilation policy information, determining a first code segment belonging to the first code type or a second code segment belonging to the second code type, compiling the first code segment into a first executable code, sending the first executable code to the first processor, compiling the second code segment into a second executable code, and sending the second executable code to the second processor.

Abstract: A data processing system comprises compile time logic, runtime logic, a control bus, and instrumentation units operatively coupled to processing units of an array. The compile time logic is configured to generate configuration files for a dataflow graph. The runtime logic is configured to execute the configuration files on the array, and to trigger start and stop events, as defined by the configuration files, in response to implementation of compute and memory operations of the dataflow graph on the array. A control bus is configured to form event routes in the array. The instrumentation units have inputs and outputs connected to the control bus and to the processing units. The instrumentation units are configured to consume the start events on the inputs and start counting clock cycles, consume the stop events on the inputs and stop counting the clock cycles, and report the counted clock cycles on the outputs.

Abstract: A data processing device according to the present invention includes: a loop counter group that includes a loop-control register set; a loop controller that controls the loop counter group, based on a value of the loop counter group, and generates a loop end signal; a controller that controls the loop counter group and the loop controller, based on an instruction word taken from an instruction memory and the loop end signal, and generates a calculator control signal and a program-counter control signal; a calculator that executes a calculation, based on the calculator control signal; and a program counter that performs a count operation in response to the program-counter control signal, and stores an address of the instruction memory storing an instruction word to be executed next.

Abstract: In accordance with an embodiment, the system provides support for large queries in a multidimensional database computing environment. A kernel-based data structure, referred to herein as an odometer retriever, or odometer, that manages pointers to data blocks, contains control information, or otherwise operates as an array of arrays of pointers to stored members. When used with a dynamic flow, the approach enables the system to be used, for example to handle grid queries, Multidimensional Expressions (MDX) queries, or other types of queries in which the potential size of the query can be up to 264 bits.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve FPGA pipeline emulation efficiency on CPUs. An example disclosed apparatus includes a loop detector to identify a register shift loop in field programmable gate array (FPGA) code, an unroller to shift and store pipeline stages in the register shift loop to a temporary unroll array, an intermediate canceller to cancel out intermediate load and store values of the temporary unroll array to retain last shifted values of the pipeline stages, and a propagator to improve emulation efficiency of the FPGA code by generating a scalar loop of the retained last shifted values for a vectorization input.

Abstract: Embodiments described herein provide a solution for optimizing a compiling of program code. A proposed state pointer, which corresponds to a current state pointer to a current state node that represents a section of the program code, is added in an intermediate language (IL) representation of the program code. When the optimizing compiler determines that an optimization should be made to a section of code, the current state node is copied to create a proposed state node, which is then referenced by the proposed state pointer. The proposed state node is edited to include the optimization while the current state node remains unchanged. The success of the optimization is evaluated, and an updated IL representation is generated in which any references to nodes that are no longer included in the flow of the former IL representation are removed.

Abstract: In an embodiment, the present invention is directed to a processor including a decode logic to receive a multi-dimensional loop counter update instruction and to decode the multi-dimensional loop counter update instruction into at least one decoded instruction, and an execution logic to execute the at least one decoded instruction to update at least one loop counter value of a first operand associated with the multi-dimensional loop counter update instruction by a first amount. Methods to collapse loops using such instructions are also disclosed. Other embodiments are described and claimed.

Abstract: Systems, apparatuses and methods may provide for technology that determines that a control loop is to be executed for an unspecified number of iterations and automatically forces the control loop to be executed for a fixed number of iterations in addition to the unspecified number of iterations, where execution of the control loop for the fixed number of iterations is conducted in parallel. In one example, the technology also removes one or more dataflow tokens associated with the execution of the control loop for the fixed number of iterations.

Abstract: An enhanced object allocation optimization selectively traverses an intermediate representation detecting on-stack replacement transitions, which when found are analyzed to determine whether a control flow-edge from a first block to a second block that is marked as an OSR resumption block exists. Responding to when the second block is marked, a pseudo call including arguments of all live local variables holding pointers to objects is inserted into the intermediate representation while optimization opportunities exist and executing a modified escape analysis on a modified intermediate representation examining each pseudo call as an escape point for all object references received by the pseudo call as arguments; ignoring uses of local variables dominated by these pseudo calls; and stack allocating objects to handle the non-local control flow due to on-stack replacement control flow using the pseudo call.

Abstract: A control device according to the present invention includes a plurality of arithmetic units that operate in parallel. A sensor value of the control amount is input to the first arithmetic unit in a signal transmission sequence, and a correction amount for the manipulation amount is output from the last arithmetic unit in the signal transmission sequence. The first arithmetic unit has a controller that produces an output by processing the input sensor value, and the arithmetic units other than the first arithmetic unit has a delay element that delays an input by a predetermined number of steps and a controller that produces an output by processing the delayed input.

Abstract: In a sequence of major computational steps or in an iterative computation, a stencil amplifier can increase the number of data elements accessed from one or more data structures in a single major step or iteration, thereby decreasing the total number of computations and/or communication operations in the overall sequence or the iterative computation. Stencil amplification, which can be optimized according to a specified parameter such as compile time, run time, code size, etc., can improve the performance of a computing system executing the sequence or the iterative computation in terms of run time, memory load, energy consumption, etc. The stencil amplifier typically determines boundaries, to avoid erroneously accessing data elements not present in the one or more data structures.

Abstract: In accordance with an embodiment, described herein is a system and method for supporting queries having sub-select constructs in a multidimensional database computing environment. The system enables a sub-select construct to be provided as part of an input query, for example using a Multidimensional Expressions (MDX), or other type of query. The inner sub-select, specified by the input query, is not executed by the system before the main query, but is used to restrict the data space for execution of the main select. The approach to processing the sub-select enables support for security-sensitive or other types of aggregation use cases.

Abstract: A hardware acceleration method, a compiler, and a device, to improve code execution efficiency and implement hardware acceleration. The method includes: obtaining, by a compiler, compilation policy information and source code, where the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor; analyzing, by the compiler, a code segment in the source code according to the compilation policy information, and determining a first code segment belonging to the first code type or a second code segment belonging to the second code type; and compiling, by the compiler, the first code segment into first executable code, and sending the first executable code to the first processor; and compiling the second code segment into second executable code, and sending the second executable code to the second processor.

Abstract: An information processing apparatus sets, in a second program: a second array where an occurrence pattern indicating whether elements are subjected to computation is a repetition of a pattern for every power-of-two number of elements; a second mask array generated by adding masks indicating that corresponding elements are not subjected to the computation to a first mask array so that the second mask array includes as many masks as the number of elements included in a second pattern; and a second instruction string providing an instruction for the computation of elements corresponding to masks indicating that corresponding elements are subjected to the computation, among the elements set in the second array. Each mask in the second mask array to be applied to an element in the second array is specified by a bitwise logical AND using a value indicating the position of the element in the second array.

Abstract: The program development support system which creates a program described in a graph form, and arranged for executing data processing by a target device includes: a GUI part; a program-creating part; a process-executing function database; and a data-transfer function database. On condition that a process included in the data processing can be executed by different kinds of processing units provided in a target device, process-executing functions for executing the process by the respective processing units are held in the process-executing function database, and data-transfer functions therefor are held in the data-transfer function database. Which processing unit to use for executing the process can be selected by the GUI part. The program-creating part reads a process-executing function corresponding to the processing unit thus selected, and data-transfer functions and creates a program for making a target device execute the intended data processing.

Abstract: Obtaining a performance metric in a system for conveying web content from a server node to a terminal node along one or more network nodes, involving an inspecting of a data flow transmitting said web content toward the terminal node for extracting web content records. The extracted web content records are correlated to at least one web session. The extracted web content records are associated to a performance of one or more of said nodes. The performance metric is calculated from the correlated and associated web content records for at least one web session and one or more of said nodes.

Abstract: A specification unit specifies numbers of cores executing processing when a predetermined number of processings to be executed in parallel is allocated to cores by same amount by changing number of processings to be allocated within a range of numbers of cores capable of executing parallel processing. A determination unit determines number of cores with highest processing performance as the number of cores executing the parallel processing from among the specified numbers of cores.

Abstract: A system can generate and impose constraints on a compiler/scheduler so as to specifically minimize the footprints of one or more program variables. The constraints can be based on scopes of the variables and/or on dependence distances between statements specifying operations that use the one or more program variables.

Abstract: A compilation system can compile a program to be executed using an event driven tasks (EDT) system that requires knowledge of dependencies between program statement instances, and generate the required dependencies efficiently when a tiling transformation is applied. To this end, the system may use pre-tiling dependencies and can derive post-tiling dependencies via an analysis of the tiling to be applied.

Abstract: A program optimization method, executed by an arithmetic processing device, includes collecting profile information including a runtime analysis result by causing a computer to execute an original program to be optimized, calculating a calculation wait time based on the profile information, and generating a tuned-up program, when the calculation wait time is longer than a first threshold, by inserting an SIMD operation control line that performs an SIMD operation for an instruction in IF statement in the loop when an SIMD instruction ratio in the loop in the original program is lower than a second threshold.

Abstract: A high level programming language provides a nested communication operator that partitions a computational space. An indexable type with a rank and element type defines the computational space. The nested communication operator partitions a specified dimension of an index indexable type into segments specified by a segmentation vector and returns an output indexable type that represents the segments. By doing so, the nested communication operator allows data parallel algorithms to operate on the segments as individual units.

Abstract: A storage unit stores source code including loop processing that is written with an array referenced by an index, a loop variable, and a parameter. A computing unit generates a conditional expression indicating that the index of the array satisfies a predetermined condition, using the loop variable and the parameter. The computing unit generates determination information on the parameter, by eliminating the loop variable from the conditional expression through formula manipulation. Then, the computing unit generates object code corresponding to the source code in accordance with the determination information.

Abstract: In certain embodiments, source code that includes at least one request to send an asynchronous message between state machines is obtained at a computing system. The computing system determines whether the asynchronous message can be implemented as an inlined message. Executable machine code corresponding to the source code is compiled such that the asynchronous message is compiled as an inlined message.

Abstract: Methods are disclosed of compiling a software application having multiple functions. At least one of the functions is identified as a targeted function having a significant contribution to performance of the software application. A code version of the targeted function is generated with one of multiple machine models corresponding to different target utilizations for a target architecture, specifically corresponding to the one with the greatest of the different target utilizations. The generated code version of the targeted function is matched with an application thread of the target architecture.

Abstract: Heterogeneous thread scheduling techniques are described in which a processing workload is distributed to heterogeneous processing cores of a processing system. The heterogeneous thread scheduling may be implemented based upon a combination of periodic assessments of system-wide power management considerations used to control states of the processing cores and higher frequency thread-by-thread placement decisions that are made in accordance with thread specific policies. In one or more implementations, a system workload context is periodically analyzed for a processing system having heterogeneous cores including power efficient cores and performance oriented cores. Based on the periodic analysis, cores states are set for some of the heterogeneous cores to control activation of the power efficient cores and performance oriented cores for thread scheduling.

Abstract: Loop abstraction includes determining an original loop within the source code. The original loop includes a control statement and a loop body such that the original loop causes the loop body to be repeatedly executed based on the control statement. Further, output variables in the original loop and a number of blocks associated with the original loop are identified. The number of blocks is indicative of a count of unconditionally executed statement sets in which at least one output variable is computed. An abstract loop corresponding to the original loop is generated by adding a modified expression for accelerated assignment for each output variable in a subset of the output variables, and replacing the control statement with a bounded control statement. The original loop is replaced with the abstract loop for generating an abstract source code for the model checking.

Abstract: A compiler determines executability of loop fusion, for each of a plurality of loops existing in a code to be processed, based on performance information of a system where the code to be processed is executed and based on operands and number of data transfers executed inside each of the loops. Then, the compiler executes fusion of loop processing in accordance with a determination result of executability of the loop fusion.

Abstract: A graph analytics appliance can be employed to extract data from a graph database in an efficient manner. The graph analytics appliance includes a router, a worklist scheduler, a processing unit, and an input/output unit. The router receives an abstraction program including a plurality of parallel algorithms for a query request from an abstraction program compiler residing on computational node or the graph analytics appliance. The worklist scheduler generates a prioritized plurality of parallel threads for executing the query request from the plurality of parallel algorithms. The processing unit executes multiple threads selected from the prioritized plurality of parallel threads. The input/output unit communicates with a graph database.

Abstract: A graph analytics appliance can be employed to extract data from a graph database in an efficient manner. The graph analytics appliance includes a router, a worklist scheduler, a processing unit, and an input/output unit. The router receives an abstraction program including a plurality of parallel algorithms for a query request from an abstraction program compiler residing on computational node or the graph analytics appliance. The worklist scheduler generates a prioritized plurality of parallel threads for executing the query request from the plurality of parallel algorithms. The processing unit executes multiple threads selected from the prioritized plurality of parallel threads. The input/output unit communicates with a graph database.

Abstract: The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

Abstract: A stream processing platform that provides fast execution of stream processing applications within a safe runtime environment. The platform includes a stream compiler that converts a representation of a stream processing application into executable program modules for a safe environment. The platform allows users to specify aspects of the program that contribute to generation of modules that execute as intended. A user may specify aspects to control a type of implementation for loops, order of execution for parallel paths, whether multiple instances of an operation can be performed in parallel or whether certain operations should be executed in separate threads. In addition, the stream compiler may generate executable modules in a way that cause a safe runtime environment to allocate memory or otherwise operate efficiently.

Abstract: Loop instructions are analyzed and assigned stage numbers based on dependencies between them and machine resources available. The loop instructions are selectively executed based on their stage numbers, thereby eliminating the need for explicit loop set-up and tear-down instructions. On a Single Instruction, Multiple Data machine, the final instance of each instruction may be executed on a subset of the processing elements or vector elements, dependent on the number of iterations of the original loop.

Abstract: A storage unit stores source code including loop processing that is written with an array referenced by an index, a loop variable, and a parameter. A computing unit generates a conditional expression indicating that the index of the array satisfies a predetermined condition, using the loop variable and the parameter. The computing unit generates determination information on the parameter, by eliminating the loop variable from the conditional expression through formula manipulation. Then, the computing unit generates object code corresponding to the source code in accordance with the determination information.

Abstract: Crash notification between debuggers, including: initiating, by a first debugger, a first debug session of a first application; detecting, by the first debugger, an error condition in the first application; determining, by the first debugger, whether any variables utilized by the first application are related to variables utilized by a second application, wherein the second application is being debugged in a second debug session by a second debugger; and communicating, by the first debugger to a second debugger, information associated with the error condition in the first application.

Abstract: The current application is directed to flexible and run-time-modifiable implementation of crosscutting functionalities, including code instrumentation, error logging, and other such crosscutting functionalities. These crosscutting functionalities generally violate, or run counter to, modern code-development strategies and programming-language features that seek to partition logic into hierarchically organized compartments and modules with related functionalities, attribute values, and other common features. One feature of the methods and systems for implementing crosscutting functionalities to which the current application is directed is an intelligent switch that can be controlled, at run time, to alter invocation and behavior of crosscutting-functionality implementations, including data-collection instrumentation, error logging, and other crosscutting-functionality implementations.

Abstract: System and methods for the parallelization of software applications are described. In some embodiments, a compiler may automatically identify within source code dependencies of a function called by another function. A persistent database may be generated to store identified dependencies. When calls the function are encountered within the source code, the persistent database may be checked, and a parallelized implementation of the function may be employed dependent upon the dependency indicated in the persistent database.

Abstract: A compiling method compiles an object program to be executed by a processor having a plurality of execution units operable in parallel. In the method a first availability chain is created from a producer instruction (p1), scheduled for execution by a first one of the execution units (20: AGU), to a first consumer instruction (c1), scheduled for execution by a second one of the execution units (22: EXU) and requiring a value produced by the said producer instruction. The first availability chain comprises at least one move instruction (mv1-mv3) for moving the required value from a first point (20: ARF) accessible by the first execution unit to a second point (22: DRF) accessible by the second execution unit.

Abstract: A tracing just-in-time (TJIT) compiler system is described for performing parallelization of code in a runtime phase in the execution of code. Upon detecting a hot loop during the execution of the code, the compiler system extracts trace information from sequentially recorded traces. In a first phase, the compiler system uses the trace information to identify at least one group of operation components that can be operated on in a parallel manner. In a second phase, the compiler system provides instructions which allocate the group of operation components to plural processing resources. A native code generator module carries out those instructions by recompiling native code that directs the operation of a native system to perform parallel processing. The compiler system terminates a group if it encounters program data in a loop iteration that is not consistent with previously encountered predicated information (upon which it records a new trace in a sequential manner).

Abstract: Embodiments are directed to implementing a generic SIMD data type in software code. In an embodiment, a computer system accesses a portion of software code that includes an algorithm with a generic SIMD data type that includes a variable number of elements. The algorithm with the generic SIMD data type is to be processed by a specific processor that includes various specific hardware features. The computer system determines at runtime a portion of customized processor-specific code that is to be used with the specified processor based on the generic SIMD data type, wherein the runtime determination resolves the number of elements that are to be used with the specified processor. The computer system also processes the software code including the algorithm with the generic SIMD data type using the determined, customized processor-specific code.

Abstract: A system and associated method for automatically pipeline parallelizing a nested loop in sequential code over a predefined number of threads. Pursuant to task dependencies of the nested loop, each subloop of the nested loop are allocated to a respective thread. Combinations of stage partitions executing the nested loop are configured for parallel execution of a subloop where permitted. For each combination of stage partitions, a respective bottleneck is calculated and a combination with a minimum bottleneck is selected for parallelization.

Abstract: Systems and methods for the vectorization of software applications are described. In some embodiments, a compiler may automatically generate both scalar and vector versions of a function from a single source code description. A vector interface may be exposed in a persistent dependency database that is associated with the function. This may allow a compiler to make vector function calls from within vectorized loops, rather than making multiple serialized scalar function calls from within a vectorized loop. This may in turn facilitate the vectorization of hierarchical code, which may improve application performance when vector execution resources are available.