Abstract: A ripple push method for a graph cut includes: obtaining an excess flow ef(v) of a current node v; traversing four edges connecting the current node v in top, bottom, left and right directions, and determining whether each of the four edges is a pushable edge; calculating, according to different weight functions, a maximum push value of each of the four edges by efw=ef(v)*W, where W denotes a weight function; and traversing the four edges, recording a pushable flow of each of the four edges, and pushing out a calculated flow. The ripple push method explores different push weight functions, and significantly improves the actual parallelism of the push-relabel algorithm.

Abstract: A compiler optimization for structure peeling an array of structures (AOS) into a structure of arrays (SOA) by which a pointer to an array in the original program, is transformed into a tagged index that includes both an array index, and a memory identifier tagging the array index. Once processed by the compiler, each array index is identified by a respective memory identifier, hence if the program instructions call for redefining an array during run time, its array element can still be retrieved by referring to the memory identifier it is tagged with.

Abstract: A system for managing network connected devices, comprising at least one hardware processor adapted to produce a plurality of unique device descriptors, each describing one of a plurality of network connected devices, by: for each of a plurality of device descriptors, each having a plurality of supported actions, and one or more domain device identifiers, each identifier associating the device descriptor with one of a plurality of management domains: for each of the plurality of management domains not associated with the device descriptor: and instructing execution on a network connected device described by the device descriptor a domain identification query according to the descriptor's plurality of supported actions, to determine a new domain device identifier.

Abstract: In some implementations, a system may receive, from a software repository, a difference file indicating changes, to software code, that was submitted to the software repository. The system may parse the difference file to determine files, associated with the software code, affected by the changes and to determine content associated with the changes. The system may apply rules, from a rule dictionary, based on comparing identifiers, associated with the files, with identifiers included in the rules and based on comparing the content, associated with the changes, with content included in the rules. The system may generate software review checklist items based on applying the rules and output the software review checklist items for display. The system may receive, based on input from a user, confirmation of the changes and commit the changes to the software repository based on the confirmation.

Abstract: A code completion tool uses a deep learning model to predict the likelihood of a method completing a method invocation. In one aspect, the deep learning model is a LSTM trained on features that represent the syntactic context of a method invocation derived from an abstract tree representation of the code fragment.

Abstract: Systems, methods, and apparatuses relating to unstructured data flow in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a data path having a first branch and a second branch, and the data path comprises at least one processing element; a switch circuit comprising a switch control input to receive a first switch control value to couple an input of the switch circuit to the first branch and a second switch control value to couple the input of the switch circuit to the second branch; a pick circuit comprising a pick control input to receive a first pick control value to couple an output of the pick circuit to the first branch and a second pick control value to couple the output of the pick circuit to a third branch of the data path; a predicate propagation processing element to output a first edge predicate value and a second edge predicate value based on (e.g.

Abstract: Methods for logging strings during execution of a program running on an embedded system without storing the strings in the memory of the embedded system include, during the build process, receiving source code for a program that comprises one or more log statements that identifies a string to be logged; generating object code based on the source code that comprises a special log section that includes the identified strings, and, for each log statement one or more instructions that cause a reference to the corresponding string to be stored in memory of the embedded system; generating execution code based on the object code wherein the special log section is marked as non-loadable and each reference is a location of the corresponding string in the special log section; and, loading the generated executable code into the memory of the embedded system such that the identified strings are not loaded into the memory of the embedded system.

Abstract: The present application discloses a data acquisition method, a microprocessor and an apparatus with storage function. The method may include: a request information for obtaining a target information may be received. The request type of the request information may be an instruction request or a data request. The instruction cache and the data cache may be queried respectively, to determine whether the target information matching with the requested information exits in the instruction cache and the data cache. If the target information exists in another cache that does not match with the request type of the request information, then the target information may be returned from the cache that does not match with the request type of the request information. The present application may physically separate the instruction cache and the data cache, thereby improving the data acquisition efficiency.

Abstract: In one approach, a method comprises receiving one or more higher-level instructions specifying to assign a value of a particular value type to a particular container of a plurality of containers, wherein the plurality of containers represent a data structure for maintaining one or more variables during execution of a block of code, wherein at least two containers of the plurality of containers are different sizes; generating one or more lower-level instructions that assign the value to the particular container based on applying one or more assignment rules to the one or more higher-level instructions based on the particular value type and executing the one or more lower-level instructions.

Abstract: An information processing method executed by a computer, the method includes executing a target program to acquire number of executions for each of a plurality of program codes; selecting a combination of program codes related to a plurality of assignment statements from among program codes related to assignment statements having a higher number of executions based on the acquired number of executions; when the target program is changed, executing the changed target program to calculate an execution accuracy and an operation time so that parallel processing using an SIMD operation function is executed for each of the program codes related to the plurality of assignment statements included in the selected combination; and searching for the combination so that the calculated execution accuracy and operation time satisfy a predetermined condition.

Abstract: Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.

Abstract: A computing system receives a program. The program is in a first computer language and specifies computer operations on stored data. The computing system is configured to partition the stored data into sets of partitioned data for performing parallel execution on each of the sets of partitioned data. The computing system determines whether the program comprises a thread program component. The computing system, responsive to determining that the program comprises a thread program component, generates computer-generated computer instructions. The computer-generated computer instructions are in a second computer language. The computer-generated computer instructions are dependent on whether the thread program component specifies information for partitioning and grouping the stored data; whether the program comprises a data program component; or whether the data program component specifies information for partitioning and grouping the output data of the thread program component.

Abstract: In traditional systems and methods, to provide infrastructure, a plurality of data models needs to be created individually for each of the respective cloud or container technologies. The creation of data models is complex, time consuming, and has tight coupling with the Infra provider, resulting in vendor lock-in.

Abstract: A code completion tool uses a deep learning model to predict the likelihood of a method completing a method invocation. In one aspect, the deep learning model is a LSTM trained on features that represent the syntactic context of a method invocation derived from an abstract tree representation of the code fragment.

Abstract: During source code compilation to a first processor instruction set architecture (ISA), a compiler encounters a memory ordering constraint specified in the source code. The compiler generates binary emulation metadata that is usable during emulation of emitted machine code instructions of the first ISA, in order to enforce the memory ordering constraint within corresponding machine code instructions of a second ISA. An emulator utilizes this binary emulation metadata during emulation of a resulting executable image at a processor implementing the second ISA. When the emulator encounters a machine code instruction in the image that performs a memory operation, it identifies an instruction memory address corresponding to the instruction. The emulator determines whether the binary emulation metadata identifies the instruction memory address as being associated with a memory ordering constraint.

Abstract: An embodiment of a semiconductor package apparatus may include technology to identify a field of a data structure as a candidate for a size reduction, perform a runtime analysis on the field, and reduce the size of the field based on the runtime analysis. Other embodiments are disclosed and claimed.

Abstract: Signature-based cache optimization for data preparation includes performing a first set of sequenced data preparation operations on one or more sets of data to generate a plurality of transformation results. It further includes caching one or more of the plurality of transformation results and one or more corresponding operation signatures, a cached operation signature being derived based at least in part on a subset of sequenced operations that generated a corresponding result. It further includes receiving a specification of a second set of sequenced operations. It further includes determining an operation signature associated with the second set of sequenced operations. It further includes identifying a cached result among the cached results based at least in part on the determined operation signature; and outputting the cached result.

Abstract: Compilers for compiling computer programs and apparatuses including compilers are disclosed herein. A compiler may include one or more analyzers to parse and analyze source instructions of a computer program including identification of nested loops of the computer program. The compiler may also include a code generator coupled to the one or more analyzers to generate and output executable code for the computer program that executes on a data flow machine, including a data flow graph, based at least in part on results of the analysis. In embodiments, the executable code may include executable code that recursively computes predicates of identified nested loops for use to generate control signal for the data flow graph to allow execution of each loop to start when the loop's predicate is available, independent of whether any other loop is in execution or not. Other embodiments may be disclosed or claimed.

Abstract: In a method for collaborating, a first computing device determines capabilities needed for an application to function. The first computing device enables one or more other computing devices to connect to the application. The first computing device determines capabilities of a second computing device, wherein the second computing device is connected to the application. The first computing device determines the capabilities needed for the application to function are met. The first computing device configures a user interface of the second device.

Abstract: According to an embodiment, a code processing apparatus includes a determining unit, a concealing unit, an instructing unit, and an unconcealing unit. The determining unit is configured to determine, based on relocation information included in first code data that includes a code body and relocation information representing a portion of the code body to be relocated by a linker, a first portion including at least a part of the code body that is other than the portion. The concealing unit is configured to conceal the first portion. The instructing unit is configured to instruct the linker to process the first code data having the first portion concealed. The unconcealing unit is configured to unconceal the concealed portion of second code data that is generated from the first code data by the linker.

Abstract: The present invention provides information for making a decision so as to efficiently localize environment-dependent portions of a program. Man-hours required to localize the environment-dependent portions are calculated by means of a unique method using program structure data and environment-dependent portions data. An effect of localizing the environment-dependent portions is calculated and visualized based on a Lorenz curve and a Gini coefficient.

Abstract: An illustrative embodiment of a computer-implemented process for managing aliasing constraints, identifies an object to form an identified object, identifies a scope of the identified object to form an identified scope, and assigns a unique value to the identified object within the identified scope. The computer-implemented process further demarcates an entrance to the identified scope, demarcates an exit to the identified scope, optimizes the identified object using a property of the identified scope and associated aliasing information, tracks the identified object state to form tracked state information; and uses the tracked state information to update the identified object.

Abstract: Systems and methods are disclosed for computing resource allocation based on flow graph translation. First, a high-level description of logic circuitry is obtained and translated to generate a flow graph representing sequential operations. Using the flow graph, similar processing elements in an array are interchangeably allocated to perform computational, communication, and storage tasks as needed. The sequential operations are executed using the array of interchangeable processing elements. Data is provided from the storage elements through the communication elements to the computational elements. Computational results are stored in the storage elements. Outputs from some of the computational elements provide inputs to other computational elements. Execution of the instructions can be controlled with time stepping. The processors are reallocated as needed, based on changes to the flow graph.

Abstract: Methods and apparatuses, including computer program products, are described for secure validation of financial transactions. A server computing device registers a mobile device to receive notification messages from the server computing device. The server computing device transmits a notification message via a first communication channel to a notification agent executing on the registered mobile device, where the message identifies activity associated with a financial account of a user of the registered mobile device. The server computing device receives a response to the notification message via a second communication channel from an application executing on the registered mobile device, if the notification message requires a response. The server computing device stores the response in a database coupled to the server computing device, and determines whether to (i) allow, (ii) deny, or (iii) deny and report as fraud the identified activity based upon the response.

Abstract: Methods, storage systems and computer program products implement embodiments of the present invention that include receiving, by a computer, source code for an application, the source code including multiple instructions to be executed in a single thread. A first static analysis is performed on the application source code in order to identify a given instruction including an asynchronous handler, and a plurality of entry points to the application. Based on the static analysis, an order of execution of the multiple instructions is determined, and an intermediate representation is generated that includes the multiple instructions arranged in the determined order of execution. In some embodiments, a second static analysis can be performed on the intermediate representation that can identify an anti-pattern in the intermediate representation, and then correct the anti-pattern in the source code.

Abstract: A memory management system is described herein that receives information from applications describing how memory is being used and that allows an application host to exert more control over application requests for using memory. The system provides an application memory management application-programming interface (API) that allows the application to specify more information about memory allocations that is helpful for managing memory later. The system also provides an ability to statically and/or dynamically analyze legacy applications to give applications that are not modified to work with the system some ability to participate in more effective memory management. The system provides application host changes to leverage the information provided by applications and to manage memory more effectively using the information and hooks into the application's use of memory.

Abstract: Techniques are disclosed relating to data transformation for distributing workloads between processors or cores within a processor. In various embodiments, a first processing element receives a set of bytecode. The set of bytecode specifies a set of tasks and a first data structure that specifies data to be operated on during performance of the set of tasks. The first data structure is stored non-contiguously in memory of the computer system. In response to determining to offload the set of tasks to a second processing element of the computer system, the first processing element generates a second data structure that specifies the data. The second data structure is stored contiguously in memory of the computer system. The first processing element provides the second data structure to the second processing element for performance of the set of tasks.

Abstract: There is provided a multi-core system that includes a lower-subsystem including a first processor and a number of slave processing cores. Each of the slave processing cores can be a coprocessor or a digital signal processor. The first processor is configured to control processing on the slave processing cores and includes a system dispatcher configured to control transactions for execution on the slave processing cores. The system dispatcher is configured to generate the transactions to be executed on the slave processing cores. The first processor can include a number of hardware drivers for receiving the transactions from the system dispatcher and providing the transactions to the slave processing cores for execution. The multi-core system can further include an upper sub-system in communication with the lower-subsystem and including a second processor configured to provide protocol processing.

Abstract: In a method for collaborating, a first computing device determines capabilities needed for an application to function. The first computing device enables one or more other computing devices to connect to the application. The first computing device determines capabilities of a second computing device, wherein the second computing device is connected to the application. The first computing device determines the capabilities needed for the application to function are met. The first computing device configures a user interface of the second device.

Abstract: Techniques for debugging are presented. Executable instructions, as they are executed, along with variable values, as they appear when being processed, are output as an executable instruction set when an executable application comprising the executable instructions are processed. The outputted executable instruction set includes the processing flow sequence that occurred within the executable application when the executable application was processed.

Abstract: Disclosed herein are representative embodiments of tools and techniques for installing, executing, and/or updating managed applications through generation of native code from code in an intermediate language. According to one exemplary technique, a computing device receives machine dependent intermediate language code (MDIL code) generated by an online provider for an application. Additionally, the computing device installs the application on the computing device by generating a native image for the application, which includes binding a portion of the MDIL code with one or more libraries on the computing device. Also, the native image is stored on the computing device for use in loading the application for execution.

Abstract: A language-based model to support asynchronous operations set forth in a synchronous syntax is provided. The asynchronous operations are transformed in a compiler into an asynchronous pattern, such as an APM-based pattern (or asynchronous programming model based pattern). The ability to compose asynchronous operations comes from the ability to efficiently call asynchronous methods from other asynchronous methods, pause them and later resume them, and effectively implementing a single-linked stack. One example includes support for ordered and unordered compositions of asynchronous operations. In an ordered composition, each asynchronous operation is started and finished before another operation in the composition is started. In an unordered composition, each asynchronous operation is started and completed independently of the operations in the unordered composition.

Abstract: Architecture introduces a new pattern operator referred to as called an augmented transition network (ATN), which is a streaming adaptation of non-reentrant, fixed-state ATNs for dynamic patterns. Additional user-defined information is associated with automaton states and is accessible to transitions during execution. ATNs are created that directly model complex pattern continuous queries with arbitrary cycles in a transition graph. The architecture can express the desire to ignore some events during pattern detection, and can also detect the absence of data as part of a pattern. The architecture facilitates efficient support for negation, ignorable events, and state cleanup based on predicate punctuations.

Abstract: A compiler includes a vector instruction processing mechanism that generates instructions for vector instructions in a way that assures correct operation in a bi-endian environment, wherein the processor architecture contains instructions with an inherent endian bias, along with at least one memory access instruction with a contrary endian bias. The compiler uses a code generation endian preference that matches the inherent computer system endian bias. The compiler generates instructions for vector instructions by determining whether the vector instruction has an endian bias that matches the code generation endian preference. When the endian bias of the vector instruction matches the code generation endian preference, the compiler generates one or more instructions for the vector instruction as normal.

Abstract: A compiler may receive source code including two user source code blocks, each capable of throwing an exception. The received source code may be associated with a policy that discards a pending exception when a subsequent exception occurs. The compiler may transform the source code such that it allows for a propagation policy that supports multiple exceptions. The transformed source code may be executed in an execution environment. Upon execution of the transformed code, a pending exception may be propagated out and a later-in-time exception may be stored.

Abstract: A user can input a search query. By assessing terms in the search query, the search query can be categorized (e.g., as a navigational, functional or browse query). The categorization can depend on an analysis of terms in the search query, a preliminary search, and/or empirical data tied to previous and similar searches. For example, searches estimated to be directed to finding a specific app can be categorized as navigational, based on capitalized letters, quotation marks, a short number of words in the query, and a tight distribution of apps typically downloaded subsequent to viewing results from the search. Based on the categorization, a search strategy can be identified. Search strategies can differentially weight and/or use text-based strategies.

Abstract: A system for automation of processes in a working environment to achieve targeted deliverables, said system comprising: mapping means adapted to map discrete processes in a working environment; reader means adapted to read human instructions in relation to targeted deliverables at mapped discrete processes; interpreter means adapted to interpret said read instructions into a machine readable instruction format; compiler means adapted to compile said machine readable instruction format into a pre-defined operating system executable instruction format; packager means adapted to classify and package said operating system executable instruction format in a pre-defined format; and installer means adapted to install and deploy said packaged format in said working environment to complete the automation process and achieve targeted deliverables.

Abstract: Custom data is injected into a comment field in an APK file. This creates a data driven, customized app, without unzipping, resigning or re-zipping the APK file. The APK file and the injected custom data are transmitted to a mobile computing device. The custom data can be injected into a comment field at the end of the APK file, which allows the non-customized version of the APK file and the custom data to be transmitted to the mobile computing device in succession, such that the transmission is received as a single, customized APK file. The content of the non-customized APK file and the custom data can instead be written to a new, customized APK file, which is then transmitted to the mobile computing device.

Abstract: A microprocessor is configured to execute programs divided into discrete phases. A scheduler is provided for scheduling instructions. A plurality of resources are for executing instructions issued by the scheduler, wherein the scheduler is configured to schedule each phase of the program only after receiving an indication that execution of the preceding phase of the program has been completed. By splitting programs into multiple phases and providing a scheduler that is able to determine whether execution of a phase has been completed, each phase can be separately scheduled and the results of preceding phases can be used to inform the scheduling of subsequent phases. In one example, different numbers of threads and/or different numbers of data instances per thread may be processed for different phases of the same program.

Abstract: Disclosed here are methods, systems, paradigms and structures for optimizing intermediate representation (IR) of a script code for fast path execution. A fast path is typically a path that handles most commonly occurring tasks more efficiently than less commonly occurring ones which are handled by slow paths. The less commonly occurring tasks may include uncommon cases, error handling, and other anomalies. The IR includes checkpoints which evaluate to two possible values resulting in either a fast path or slow path execution. The IR is optimized for fast path execution by regenerating a checkpoint as a labeled checkpoint. The code in the portion of the IR following the checkpoint is optimized assuming the checkpoint evaluates to a value resulting in fast path. The code for handling situations where the checkpoint evaluates to a value resulting in slow path is transferred to a portion of the IR identified by the label.

Abstract: System and methods are provided for loop process suspension. One or more loop instructions associated with a loop process are loaded in a code cache. One or more branch instructions associated with a branch of the loop process in the code cache are determined. A suspension event is detected. The branch instructions are replaced with one or more jump instructions in the code cache upon the detection of the suspension event. If the jump instructions are executed in the code cache, the branch instructions in the code cache are restored, and the loop process is suspended. One or more suspension instructions associated with the suspension event are executed in an interpreter.

Abstract: Where data are shared by multiple computer processing threads, modifying the data by determining whether modifying data associated with a first computer processing thread violates a constraint associated with the data, and responsive to determining that modifying the data associated with the computer processing thread violates the constraint associated with the data, using the data associated with the first computer processing thread to modify the data shared by the multiple computer processing threads that includes the first computer processing thread, where the constraint associated with the data associated with the first computer processing thread represents a portion of a tolerance value that is associated with the data shared by the multiple computer processing threads and that is divided among multiple constraints, where each of the constraints is associated with a different one of the multiple computer processing threads.

Abstract: A method and system for a command processor for efficient processing of a program multi-processor core system with a CPU and GPU. The multi-core system includes a general purpose CPU executing commands in a CPU programming language and a graphic processing unit (GPU) executing commands in a GPU programming language. A command processor is coupled to the CPU and GPU. The command processor sequences jobs from a program for processing by the CPU or the GPU. The command processor creates commands from the jobs in a state free command format. The command processor generates a sequence of commands for execution by either the CPU or the GPU in the command format. A compiler running a meta language converts program data for the commands into a first format readable by the CPU programming language and a second format readable by the GPU programming language.

Abstract: The described embodiments comprise a PredCount instruction and a SegCount instruction. When executed by a processor, the PredCount instruction causes the processor to analyze a predicate vector to determine a number of active elements in the predicate vector that exhibit a predetermined condition (e.g., that are set to a predetermined value) and to return a result indicating that number. When executed by a processor, the SegCount instruction causes the processor to determine a number of times that a GeneratePredicates instruction would be executed to generate a full set of predicates using active elements of an input vector.

Abstract: A method for flattening conditional statements, the method comprises: obtaining a program code, the program code comprising a conditional control flow program construct, which conditional control flow program construct when read by a target processor, causes the target processor to select a control flow path for execution between at least a first and a second control flow paths, wherein said selection is based on an evaluation of a condition of the conditional control flow program construct; replacing the conditional control flow program construct with a transaction-based control flow program construct, which when read by the target processor is operative to cause the target processor to commence a transaction, the transaction configured to execute the first control flow path; and wherein the transaction-based control flow program construct is operative to cause the target processor to execute the conditional control flow program construct in case the transaction is rolled back.

Abstract: A system and method for automatically generating exploits, such as exploits for target code, is described. In some implementations, the system received binary code and/or source code of a software applications, finds one or more exploitable bugs within the software application, and automatically generates exploits for the exploitable bugs.

Abstract: An example method includes obtaining annotated source code and based at least in part on a first annotation, separating the source code into first and second source code portions. The method also includes generating from the first source code portion a first source code stream to be supplied for compilation by a first compiler, the first source code stream augmented, based on the first annotation, to include additional coordination code not present in the obtained source code, and the first compiler specific to the first-type subset of the target CPUs. The method further includes generating from the second source code portion a second source code stream to be supplied for compilation by a second compiler, the second compiler specific to a second-type subset of the target CPUs. The target CPUs of the first- and second-type subsets have one or more different functionalities.

Abstract: The embodiments of the present invention relate to controlling interactions between one or more components of a computer system, where each component is assigned a fixed security level and all currently active and newly requested interactions between components of the system are monitored.

Abstract: Embodiments of techniques and systems associated with binary translation (BT) in computing systems are disclosed. In some embodiments, a BT task to be processed may be identified. The BT task may be associated with a set of code and may be identified during execution of the set of code on a first processing core of the computing device. The BT task may be queued in a queue accessible to a second processing core of the computing device, the second processing core being different from the first processing core. In response to a determination that the second processing core is in an idle state or has received an instruction through an operating system to enter an idle state, at least some of the BT task may be processed using the second processing core. Other embodiments may be described and/or claimed.

Abstract: Example embodiments described herein may comprise a transfer of firmware execution within a non-volatile memory device to one or more replacement instructions at least in part in response to a match between a code fetch address and an address stored in a trap address register.