Dependency Based Cooperative Processing Of Multiple Programs Working Together To Accomplish A Larger Task Patents (Class 718/106)
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Publication number: 20140026148Abstract: Technologies for low power execution of one or more threads of a multithreaded program by one or more processing elements are generally disclosed.Type: ApplicationFiled: September 24, 2013Publication date: January 23, 2014Applicant: Empire Technology Development LLCInventor: Yan Solihin
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Publication number: 20140026145Abstract: A human-machine interface (HMI) application (26) uses parallel processing. The HMI engineering system (24) allows explicit specification (44) of different cores of a multi-core processor (16) for different elements and/or actions. The programmer may design the HMI application for concurrent operation. The HMI engineering system (24) or runtime system (28) may test (56) for data dependency amongst the elements or actions and automatically assigns different cores where data is independent. During runtime, different threads for the HMI application (e.g., different elements and/or actions) are scheduled for different cores.Type: ApplicationFiled: February 1, 2012Publication date: January 23, 2014Applicants: SIEMENS AKTIENGESELLSCHAFT, SIEMENS CORPORATIONInventors: Arquimedes Martinez Canedo, Sven Hermann, Lingyun Max Wang, Holger Strobel
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Patent number: 8631160Abstract: One embodiment of the present invention provides a method for supporting the development of a parallel/distributed application, wherein the development process comprises a design phase, an implementation phase and a test phase. A script language can be provided in the design phase for representing elements of a connectivity graph and the connectivity between them. In the implementation phase, modules can be provided for implementing functionality of the application, executors can be provided for defining a type of execution for the modules, and process-instances can be provided for distributing the application over several computing devices. In the test phase, abstraction levels can be provided for monitoring and testing the application.Type: GrantFiled: May 4, 2006Date of Patent: January 14, 2014Assignee: Honda Research Institute Europe GmbHInventors: Frank Joublin, Christian Goerick, Antonello Ceravola, Mark Dunn
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Patent number: 8631412Abstract: A scheduler is provided, which takes into account the location of the data to be accessed by a set of jobs. Once all the dependencies and the scheduling constraints of the plan are respected, the scheduler optimizes the order of the remaining jobs to be run, also considering the location of the data to be accessed. Several jobs needing an access to a dataset on a specific disk may be grouped together so that the grouped jobs are executed in succession, e.g., to prevent activating and deactivating the storage device several times, thus improving the power consumption and also avoiding input output performances degradation.Type: GrantFiled: May 2, 2012Date of Patent: January 14, 2014Assignee: International Business Machines CorporationInventors: Giuseppe Longobardi, Scot MacLellan
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Patent number: 8631416Abstract: A system, method, and computer-readable medium, is described that enables a parallelizing scheduler to analyze database instructions, determine data dependencies among instructions, and provide a multi-threaded approach to running instructions in parallel while preserving data dependencies.Type: GrantFiled: March 31, 2011Date of Patent: January 14, 2014Assignee: Verisign, Inc.Inventor: John Rodriguez
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Patent number: 8630296Abstract: A method for configuring a packet destination, that includes creating the packet destination on a host, obtaining a network configuration for the packet destination, determining whether the host comprises a virtual network stack, where the virtual network stack includes the network configuration, and assigning the packet destination to the virtual network stack.Type: GrantFiled: July 20, 2006Date of Patent: January 14, 2014Assignee: Oracle America, Inc.Inventors: Erik Nordmark, Sunay Tripathi, Nicolas G. Droux
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Patent number: 8631414Abstract: In a portable computing device having a node-based resource architecture, a first or distributed node controlled by a first processor but corresponding to a second or native node controlled by a second processor is used to indirectly access a resource of the second node. In a resource graph defining the architecture each node represents an encapsulation of functionality of one or more resources, each edge represents a client request, and adjacent nodes represent resource dependencies. Resources defined by a first graph are controlled by the first processor but not the second processor, while resources defined by a second graph are controlled by the second processor but not the first processor. A client request on the first node may be received from a client under control of the first processor. Then, a client request may be issued on the second node in response to the client request on the first node.Type: GrantFiled: September 2, 2011Date of Patent: January 14, 2014Assignee: QUALCOMM IncorporatedInventors: Norman S. Gargash, Yizheng Zhou, Vinod Vijayarajan
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Patent number: 8627330Abstract: Described herein is a workload manager for managing a workload in a database that includes: an admission controller operating to divide the workload into a plurality of batches, with each batch having at least one workload process to be performed in the database, and each batch having a memory requirement based on the available memory for processing workloads in the database; a scheduler operating to assign a unique priority to each of the at least one workload process in each of the plurality of batches, the unique priority provides an order in which each workload process is executed in the database; and an execution manager operating to execute the at least one workload process in each of the plurality of batches in accordance with the unique priority assigned to each workload process.Type: GrantFiled: October 22, 2008Date of Patent: January 7, 2014Assignee: Hewlett-Packard Development Company, L.P.Inventors: Abhay Mehta, Chetan Kumar Gupta, Umeahwar Dayal
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Patent number: 8627331Abstract: A technique is described for improving throughput in a processing system, such as a network storage server. The technique provides multiple levels (e.g., a hierarchy) of parallelism of process execution within a single mutual exclusion domain, in a manner which allows certain operations on metadata to be parallelized as well as certain operations on user data. The specific parallelization scheme used in any given embodiment is based at least partly on the underlying metadata structures used by the processing system. Consequently, a high degree of parallelization possible, which improves the throughput of the processing system.Type: GrantFiled: April 30, 2010Date of Patent: January 7, 2014Assignee: NetApp, Inc.Inventors: David Grunwald, Jeffrey S. Kimmel
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Patent number: 8627451Abstract: A sandbox tool can cooperate with components of a secure operating system to create an isolated execution environment for accessing untrusted content without exposing other processes and resources of the computing system to the untrusted content. The sandbox tool can allocate resources (storage space, memory, etc) of the computing system, which are necessary to access the untrusted content, to the isolated execution environment, and apply security polices of the operating system to the isolated execution environment such that untrusted content running in the isolated execution environment can only access the resources allocated to the isolated execution environment.Type: GrantFiled: August 21, 2009Date of Patent: January 7, 2014Assignee: Red Hat, Inc.Inventors: Daniel J. Walsh, Eric Lynn Paris
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Publication number: 20140007133Abstract: Processing logic and a method to provide single thread access to a specific memory region without suspending processing activity for all other cores and/or threads within or in association with a processor, computer system, or other processing apparatus. Single thread access may be provided through implementation of microcode which may control thread access to model specific registers (“MSRs”) within a processor. One MSR may provide a mutex, which a single thread may claim, and another MSR may provide a range of memory locations, which may be accessed by the thread that has claimed the mutex.Type: ApplicationFiled: June 29, 2012Publication date: January 2, 2014Inventor: Nicholas J. ADAMS
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Publication number: 20140007134Abstract: Systems, methods and computer program products manage computing resources for a system. A system includes a set of processors having multiple processor cores present in the computer system, where the processor cores form an aggregated set of processor cores for the system. A dependency analyzer determines dependencies among a set of workload components executing on the set of processor cores. A policy includes rules associated with managing one or more of power consumption, heat production, operating cost or workload balancing for the set of aggregated processor cores. In response to a workload event, a management component sets a state of one or more of the processor cores in accordance with the workload event, the policy and the set of dependencies.Type: ApplicationFiled: February 26, 2013Publication date: January 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James C. Fletcher, Balachandar Rajaraman
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Patent number: 8621472Abstract: A scheduler is provided, which takes into account the location of the data to be accessed by a set of jobs. Once all the dependencies and the scheduling constraints of the plan are respected, the scheduler optimizes the order of the remaining jobs to be run, also considering the location of the data to be accessed. Several jobs needing an access to a dataset on a specific disk may be grouped together so that the grouped jobs are executed in succession, e.g., to prevent activating and deactivating the storage device several times, thus improving the power consumption and also avoiding input output performances degradation.Type: GrantFiled: November 2, 2010Date of Patent: December 31, 2013Assignee: International Business Machines CorporationInventors: Giuseppe Longobardi, Scot MacLellan
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Patent number: 8621482Abstract: A method, computer program, and database system are disclosed. A plurality of instances of a request to a database system are received. All instances of the request have a same set of variables to use in executing the request. The values of the variables are supplied by data in a data source. A specific plan for executing one instance of the request is generated. Generating the specific plan includes taking into account data in the data source. The specific plan is executed on the database system. A system run-time metric and a parsing time for executing the specific plan are captured and saved. A generic plan is generated and cached based on a comparison of the system run-time metric and the parsing time for executing the specific plan.Type: GrantFiled: September 5, 2008Date of Patent: December 31, 2013Assignee: Teradata US, Inc.Inventors: Bhashyam Ramesh, Donald Pederson, Manjula Koppuravuri
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Publication number: 20130347001Abstract: A exclusion control method includes setting, for at least one or more operation information defining operations for an information processing apparatus and being included in a plurality of work flow information that indicate operation procedures, exclusive sections that indicate units of exclusion control performing an exclusive lock, calculating priorities of the exclusive sections using operation importance level information that indicate importance levels of the operations according to types of the operation information and operation urgency level information that indicate an urgency levels of the operations, when the operations are executed based on the operation information corresponding to the exclusive sections of the plurality of workflow information, and executing the exclusion control in the exclusive sections for a plurality of workflow based on the priorities, when a competitive regarding the exclusive lock occurs between the exclusive sections.Type: ApplicationFiled: April 1, 2013Publication date: December 26, 2013Applicant: FUJITSU LIMITEDInventors: Masakazu FURUKAWA, Yusuke Kuchiwaki, Takashi Ikezaki
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Patent number: 8615765Abstract: Computer micro-jobs are disclosed. A computer job is divided into micro-jobs. In one embodiment, the micro-jobs have a size that allows a particular micro-job to complete within an allotted time for which the particular micro-job owns a resource used to execute the micro-job. In one embodiment, the allotted time is a quantum. In one embodiment, an entire computer job is divided into micro-jobs and the computer job is then executed micro-job by micro-job until the entire computer job is complete. Each of the micro-jobs may complete its execution within its quantum, in one embodiment. In one embodiment, the execution of the micro-jobs is allocated to times when needed resources comply with one or more idleness criteria. A software program executed with micro-jobs may be run at all times while the computer is powered up without impacting the performance of other software programs running on the same computer system.Type: GrantFiled: November 2, 2011Date of Patent: December 24, 2013Assignee: Condusiv Technologies CorporationInventors: Craig Jensen, Andrew Staffer, Basil Thomas, Richard Cadruvi
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Patent number: 8615769Abstract: The present invention provides a system which executes processes in steps so as to increase the speed of processing and implement links with other systems easily. The data processing system includes: an AP execution unit which executes operational processing while referring to/updating an in-memory DB and a disk type DB; a buffer storage unit which stores output data of the operational processing in a data buffer; a response transmission unit which issues a processing end notice of the operational processing; a temporary file storage unit which stores, in a temporary file, the output data stored in the data buffer; a request transmission unit which transmits a commitment request with respect to the disk type DB; a disk type DB commitment unit which commits the disk type DB by updating a control table; a normal file storage unit which changes the temporary file to a normal file, and an in-memory DB commitment unit which commits the in-memory DB.Type: GrantFiled: February 8, 2011Date of Patent: December 24, 2013Assignee: NEC CorporationInventor: Yoshihiko Nishihata
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Patent number: 8615768Abstract: A synchronization system is described herein that synchronizes resource objects in an order based on their dependency relationships so that a referenced object is available by the time an object that references it is synchronized. Reference attributes present in resources define the dependency relationship among resources. Using these relationships, the system builds a dependency tree and orders synchronization operations for environment reconciliation by precedence so that referential integrity is preserved while still synchronizing reference attributes. The system can deterministically create a change list that guarantees referential integrity, and perform change list processing in parallel. The synchronization system attempts to order the synchronization based on references available to ensure that the system creates and updates dependent resources before their parent resources. Thus, the synchronization system provides a fast, reliable update mechanism for synchronizing two related data environments.Type: GrantFiled: September 27, 2010Date of Patent: December 24, 2013Assignee: Microsoft CorporationInventors: Billy Kwan, Joseph M. Schulman
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Patent number: 8612978Abstract: A program is executed utilizing a main hardware thread. During execution, an instruction specifies to execute a portion utilizing a worker hardware thread. If a processor state indicator is set to multi-threaded, the specified portion is executed utilizing the worker hardware thread. However, if the processor state indicator is set to single-threaded, the specified portion is executed utilizing the main hardware thread as a subroutine. The main hardware thread may pass parameter data to the worker hardware thread by copying the parameter data register or memory location for the main hardware thread to an equivalent parameter data register or memory location for the worker hardware thread. Similarly, the worker hardware thread may pass return values to the main hardware thread by copying a return value register or memory location for the worker hardware thread to an equivalent return value register or memory location for the main hardware thread.Type: GrantFiled: December 10, 2009Date of Patent: December 17, 2013Assignee: Oracle America, Inc.Inventor: Peter Carl Damron
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Patent number: 8612510Abstract: A large-scale data processing system and method for processing data in a distributed and parallel processing environment. The system includes an application-independent framework for processing data having a plurality of application-independent map modules and reduce modules. These application-independent modules use application-independent operators to automatically handle parallelization of computations across the distributed and parallel processing environment when performing user-specified data processing operations. The system also includes a plurality of user-specified, application-specific operators, for use with the application-independent framework to perform a user-specified data processing operation on a user-specified set of input files. The application-specific operators include: a map operator and a reduce operator. The map operator is applied by the application-independent map modules to input data in the user-specified set of input files to produce intermediate data values.Type: GrantFiled: January 12, 2010Date of Patent: December 17, 2013Assignee: Google Inc.Inventors: Jeffrey Dean, Sanjay Ghemawat
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Patent number: 8612991Abstract: A method for dynamically recalculating a critical path in a job scheduling system is disclosed. In selected embodiments, the method may include determining when a first job associated with a critical path is substantially complete. The method may further include identifying a successor job of the first job and identifying multiple predecessor jobs of the successor job. The method may then determine whether there is at least one predecessor job that has not completed. In the event there is at least one predecessor job that has not completed, the method may recalculate the critical path. A corresponding apparatus and computer program product for implementing the above-stated method are also disclosed.Type: GrantFiled: November 24, 2008Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventor: Valeria Perticara'
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Patent number: 8610912Abstract: An image processing apparatus displays a screen for designating cooperative processing in which the image processing apparatus and at least one other image processing apparatus cooperate based on externally received information, where if an execution instruction for processing to be executed by the image processing apparatus for the cooperative processing is received, the processing is executed. A screen displaying the status of processing in the at least one other image processing apparatus and a screen enabling designation of subsequent processing to be executed by the image processing apparatus are displayed based on the externally received screen information while the at least one other image processing apparatus is executing processing to be executed by the at least one other image processing apparatus for the cooperative processing after the execution of the processing.Type: GrantFiled: November 22, 2011Date of Patent: December 17, 2013Assignee: Canon Kabushiki KaishaInventor: Hideki Hirose
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Patent number: 8612976Abstract: Various embodiments disclose a method and system for creating a virtual part used for composing a virtual solution. In one embodiment, a user's selection of at least one virtual image is received. A set of configurability points is associated with the virtual image. A set of parameters of a virtual part is set as configurable during virtual solution composition. A set of virtual ports is generated. Each virtual port within the set of virtual ports indicates at least one of a set of virtual parts required by a virtual part including the set of virtual ports and a set of virtual parts that is compatible with the virtual part. A set of configuration operations is received. A virtual part including at least the virtual image, the set of configurability points, the set of virtual ports, and the configuration operations is generated.Type: GrantFiled: August 9, 2012Date of Patent: December 17, 2013Assignee: International Business Machines CorporationInventors: William C. Arnold, Tamar Eilam, Michael H. Kalantar, Alexander V. Konstantinou, John A. Pershing, Edward C. Snible, Alexander A. Totok
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Publication number: 20130332939Abstract: A data processing apparatus and method are provided for processing a received workload in order to generate result data. A thread group generator generates from the received workload a plurality of thread groups to be executed to process the received workload. Each thread group consists of a plurality of threads, and at least one thread group has an inter-thread dependency existing between the plurality of threads. Each thread may be either an active thread whose output is required to form the result data, or a dummy thread required to resolve the inter-thread dependency for one of the active threads but whose output is not required to form the result data. The thread group generator identifies for each thread group any dummy thread within that thread group. A thread execution unit then executes each thread within a thread group received from the thread group generator by executing a predetermined program comprising a plurality of program instructions.Type: ApplicationFiled: June 4, 2013Publication date: December 12, 2013Inventors: Andreas Due ENGH-HALSTVEDT, Jorn NYSTAD
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Patent number: 8607247Abstract: Method, system, and computer program product embodiments for synchronizing workitems on one or more processors are disclosed. The embodiments include executing a barrier skip instruction by a first workitem from the group, and responsive to the executed barrier skip instruction, reconfiguring a barrier to synchronize other workitems from the group in a plurality of points in a sequence without requiring the first workitem to reach the barrier in any of the plurality of points.Type: GrantFiled: November 3, 2011Date of Patent: December 10, 2013Assignee: Advanced Micro Devices, Inc.Inventors: Lee W. Howes, Benedict R. Gaster, Michael C. Houston, Michael Mantor, Mark Leather, Norman Rubin, Brian D. Emberling
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Patent number: 8607242Abstract: Cloud service providers are selected to perform a data processing job based on information about the cloud service providers and criteria of the job. A plan for a cloud pipeline for performing the job is designed based on the information about the cloud service providers. The plan comprises processing stages each of which indicates processing upon a subset of a data set of the job. Allocated resources of the set of cloud service providers are mapped to the processing stages. Instructions and software images based on the plan are generated. The instructions and the software images implement the cloud pipeline for performing the data processing job. The instructions and the software images are transmitted to machines of the cloud service providers. The machines and the performing of the job are monitored. If the monitoring detects a failure, then the cloud pipeline is adapted to the failure.Type: GrantFiled: September 2, 2010Date of Patent: December 10, 2013Assignee: International Business Machines CorporationInventor: Michael P. Clarke
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Patent number: 8607246Abstract: Tasks are executed in a multiprocessing system with a master processor core (10) and a plurality of slave processor cores (12). The master processor core (10), executes a program that defines a matrix of tasks at respective positions in the matrix and a task dependency pattern applicable to a plurality of the tasks and defined relative to the positions. Each dependency pattern defines relative dependencies for a plurality of positions in the matrix, rather than using individual dependencies for individual positions. In response to the program the master processor core (10) dynamically stores definitions of current task dependency patterns in a dependency pattern memory. A hardware task scheduler computes the positions of the tasks that are ready for execution at run time from information from information about positions for which tasks have been completed and the task dependency pattern applied relative to those tasks.Type: GrantFiled: July 2, 2009Date of Patent: December 10, 2013Assignee: NXP, B.V.Inventors: Ghiath Al-Kadi, Andrei Sergeevich Terechko
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Patent number: 8607245Abstract: A dynamic processor-set management method provides for transferring a process from a shared processor set to a dedicated processor set when that process meets a first utilization-related criterion. The method also provides for transferring a process between from a dedicated processor set to a shared processor set when that process meets a second utilization-related criterion. The processor sets are mapped to processor cores that execute the processes.Type: GrantFiled: May 15, 2009Date of Patent: December 10, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ryohei Leo Sakaguchi, Daniel Edward Herington, Seiji Inokuchi
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Publication number: 20130326536Abstract: A mechanism for detecting conflicting operations and providing resolutions in a tasking system is disclosed. A method includes receiving, by a processing device in a tasking system, a request for a call including at least one operation to be executed on at least one resource of a plurality of resources that are managed by the tasking system. The method also includes detecting an occurrence of a conflict between the at least one operation on the call request and queued operations associated with the plurality of resources. The method also includes generating at least one of a task or an error report for the at least one operation in the call request based on the conflict. The method further includes identifying task dependencies associated with the at least one task and executing the at least one task only after execution of the task dependencies.Type: ApplicationFiled: May 30, 2012Publication date: December 5, 2013Inventor: Jason L. Connor
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Publication number: 20130326537Abstract: A task is marked as dependent upon a preceding task. The task that is attempted to be taken for execution from a head of a pending task queue that is marked is deferred. The deferred task is removed from the pending task queue and placed in a deferred task queue. The deferred task is reinserted back into the pending task queue for execution upon determining that the preceding tasks are completed.Type: ApplicationFiled: June 5, 2012Publication date: December 5, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ron EDELSTEIN, Yariv BACHAR, Oded SONIN
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Patent number: 8601485Abstract: A data processing apparatus and method are provided for processing a received workload in order to generate result data. A thread group generator generates from the received workload a plurality of thread groups to be executed to process the received workload. Each thread may be either an active thread whose output is required to form the result data, or a dummy thread required to resolve the inter-thread dependency for one of the active threads but whose output is not required to form the result data. Execution flow modification circuitry is responsive to the received thread group having at least one dummy thread, to cause the thread execution unit to selectively omit at least part of the execution of at least one of the plurality of instructions when executing each dummy thread, in dependence on control information associated with the predetermined program.Type: GrantFiled: May 25, 2011Date of Patent: December 3, 2013Assignee: ARM LimitedInventors: Andreas Due Engh-Halstvedt, Jørn Nystad
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Patent number: 8601133Abstract: A network device establishes a logical channel with each server device of multiple server devices, where each logical channel is not shared with another server device of the multiple server devices. The network device also determines a network loopback Internet protocol (IP) address for each server device of the multiple server devices, and associates each network loopback IP address with a corresponding logical channel. The network device further receives a packet destined for a particular server device, and provides the packet to the particular server device via the logical channel associated with the particular server device.Type: GrantFiled: December 14, 2010Date of Patent: December 3, 2013Assignee: Juniper Networks, Inc.Inventors: George Rainovic, Chandra Pandey
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Patent number: 8601484Abstract: A method and system for managing resources of a portable computing device is disclosed. The method includes receiving node structure data for forming a node, in which the node structure data includes a unique name assigned to each resource of the node. A node has at least one resource and it may have multiple resources. Each resource may be a hardware or software element. The method also includes receiving marker data and creating a marker. A marker includes a legacy element such as a hardware or software element. The system includes a framework manger which handles the communications between existing nodes and markers within a node architecture. The framework manager also logs activity of each resource and marker by using its unique name. The framework manager may send this logged activity to an output device, such as a printer or a display screen.Type: GrantFiled: September 15, 2010Date of Patent: December 3, 2013Assignee: QUALCOMM IncorporatedInventors: Brian J. Salsbery, Norman S. Gargash
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Publication number: 20130318540Abstract: A data flow graph processing device that transforms a data flow graph including a loop structure into a pipeline operation capable of determining node execution order and judging whether or not executable, comprises: a delay node divider that divides a delay node included in t data flow graph into a value update node and a value output node; a dependency relation adder that adds dependency relations from the start node of the data flow graph to the value output node; and a hidden dependency relation adder that adds hidden dependency relations, indicating previous iteration and current iteration dependencies, from the value update node to the value output node.Type: ApplicationFiled: February 1, 2012Publication date: November 28, 2013Applicant: NEC CORPORATIONInventor: Takahiro Kumura
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Patent number: 8595181Abstract: The present invention is directed to methods and systems for rendering perceivable stimuli representative of information processing by a multi-tenant architecture that pre-fetches a portion of a subset of data on a multi-tenant architecture and emulates a result set of data in accordance with a report definition. To that end the method comprises identifying a subset of data on the multi-tenant architecture that is subject to a report definition. A portion of the subset is pre-fetched and analyzed to emulate a result. The emulated result is transmitted to a computer system of a user of the multi-tenant architecture. Perceivable stimuli is generated on the user computer system, in response to receiving the emulated result.Type: GrantFiled: April 25, 2011Date of Patent: November 26, 2013Assignee: salesforce.com, inc.Inventor: Guillaume Le Stum
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Patent number: 8595700Abstract: The present invention provides a component reuse method for reusing at least first component that is selected from a first software system to a second software system. The method comprises the steps of: analyzing the first software system, determining dependencies of the at least one first component of the first software system and acquiring relevant interface information; generating surrogates based on the dependencies and the interface information, which will be deployed in the first operating environment and in the second operating environment respectively, wherein the surrogates allow the second software system to invoke service provided by the at least one first component in the first operating environment and allow the at least one first component to invoke relevant service provided in the second software system.Type: GrantFiled: May 6, 2008Date of Patent: November 26, 2013Assignee: International Business Machines CorporationInventors: He Yuan Huang, Shih-Gong Li, Hua Fang Tan, Wei Zhao, Jun Zhu
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Patent number: 8593665Abstract: A system is capable of performing a processing flow based on a definition file which designates a plurality of tasks each of which can be performed by a function provided by an image forming apparatus and an order of performance of a plurality of tasks. The system includes an acquisition unit configured to acquire a definition file of the processing flow specified by a user, a determination unit configured to select one of a plurality of image forming apparatuses to perform each task included in the processing flow based on candidate information included in the definition file of the processing flow, and a performing unit configured to perform each task included in the processing flow using the image forming apparatus selected by the determination unit. The candidate information includes information on a user device that is set corresponding to each user as information for determining the image forming apparatus that performs the task.Type: GrantFiled: November 8, 2007Date of Patent: November 26, 2013Assignee: Canon Kabushiki KaishaInventor: Fumitoshi Ito
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Patent number: 8595487Abstract: Hardware virtualization support is used to isolate kernel extensions. A kernel and various kernel extensions are executed in a plurality of hardware protection domains. Each hardware protection domain defines computer resource privileges allowed to code executing in that hardware protection domain. Kernel extensions execute with appropriate computer resource privileges to complete tasks without comprising the stability of the computer system.Type: GrantFiled: November 1, 2006Date of Patent: November 26, 2013Assignee: VMware, Inc.Inventors: Kinshuk Govil, Keith Adams
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Publication number: 20130312007Abstract: Embodiments include systems and methods that implement semaphore-based protection of various system resources. In an embodiment, a job scheduling module receives a job execution request from a requesting module (e.g., a CPU or other autonomous module). In response to receiving the job execution request, the job scheduling module identifies a descriptor, where the descriptor includes code configured to access a semaphore-protected resource. The job scheduling module causes a descriptor controller module to execute the descriptor. More specifically, execution of the descriptor includes the descriptor controller module performing a semaphore-based access of the protected resource. The job scheduling module also may coordinate sharing the descriptor among multiple descriptor controller modules (e.g., allowing parallel execution of portions of the descriptor).Type: ApplicationFiled: May 15, 2012Publication date: November 21, 2013Inventor: STEVEN D. MILLMAN
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Publication number: 20130312008Abstract: An embodiment of the present invention establishes a neural network of handheld devices with a master server so that the master server may parcel out a large task into many smaller tasks to be assigned to one or more networked and subservient handheld devices. The handheld devices will then use its computing power to process the assigned smaller task and send the output to the master server for its compilation of the output data for producing an answer to the large task.Type: ApplicationFiled: May 17, 2012Publication date: November 21, 2013Inventors: Johnathan J. PARK, John K. Park
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Patent number: 8587793Abstract: A print image processing apparatus, includes N image processing circuits; a selection unit that estimates, every N pages, a necessary time corresponding to each of (i) a page-based parallel method for allocating image processing of the N pages to the image processing circuits in units of pages to perform the image processing of the N pages in parallel, and (ii) a paginal-object-based parallel method for allocating image processing of each single page to the image processing circuits in units of objects to perform the image processing of the objects of each single page in parallel, and selects one of the page-based parallel method and the paginal-object-based parallel method such that the estimated necessary time corresponding to the selected one of the parallel methods is shorter than the estimated necessary time; and an allocation unit that allocates image processing of the N pages to the N image processing circuit, respectively.Type: GrantFiled: October 26, 2010Date of Patent: November 19, 2013Assignee: Fuji Xerox Co., Ltd.Inventors: Takao Naito, Kazuo Yamada
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Patent number: 8589950Abstract: A method and computing device are provided for processing user events received via a user interface, such as a touchscreen, in multiple threads. When a user event is received for a target element in a webpage, the user event is dispatched to both a main browser thread and a secondary thread. The secondary thread processes user events in accordance with established default actions defined within the browser, while the main thread processes the user events in accordance with any event handlers defined for that target element. The main thread processing may be delayed by other interleaved task, and the secondary thread may be given priority over the main thread. When the secondary thread completes processing, an updated webpage is displayed. When the main thread subsequently completes processing, its updated rendering of the webpage is displayed. The secondary thread thus provides an early user interface response to the user event.Type: GrantFiled: January 5, 2011Date of Patent: November 19, 2013Assignee: BlackBerry LimitedInventors: Adam Chester Treat, Eli Joshua Fidler, Karl Arvid Nilsson, David Francis Tapuska, Genevieve Elizabeth Mak
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Patent number: 8589935Abstract: A computing system (10) includes a plurality of hardware computing resources (12-36) controlled at least in part by a plurality of autonomous computing agents (40,42,44). Each autonomous computing agent (40,42,44) includes or has access to operating information including processing information (46), resource information (48), optimization information (50), and communication information (52). The computing agents (40,42,44) collaborate to optimize performance of the system (10) and to assign computing tasks to the resources (12-36) according to a predetermined strategy. The predetermined strategy may seek to optimize speed, power, or communication efficiency of the system 10. Each agent (40,42,44) may optimize performance of the system (10) by assigning tasks to best-fit resources or by reconfiguring one or more resources.Type: GrantFiled: May 8, 2007Date of Patent: November 19, 2013Assignee: L-3 Communications CorporationInventors: Deepak Prasanna, Gerald L. Fudge
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Publication number: 20130305259Abstract: A hardware control method for multitasking drivers under a user mode is provided. The control method includes steps of: receiving a request for access to a hardware device from a current process under the user mode; determining whether the current process has obtained a mutual exclusion (mutex) of the hardware device; if affirmative, determining whether an identification of the current process and an identification of a previous process accessed the hardware device are the same; if negative, performing a context switch on the current process and the previous process accessed the hardware device to allow the current process to access the hardware device. Accordingly, when accessing complicated hardware devices, the disclosure significantly enhances driver performance under a user mode while also implementing secured random access to hardware devices in a multitasking environment.Type: ApplicationFiled: April 17, 2013Publication date: November 14, 2013Applicant: MStar Semiconductor, Inc.Inventors: Jian Wang, Ming-Yong Sun
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Publication number: 20130305258Abstract: One embodiment of the present disclosure sets forth a technique for enforcing cross stream dependencies in a parallel processing subsystem such as a graphics processing unit. The technique involves queuing waiting events to create cross stream dependencies and signaling events to indicated completion to the waiting events. A scheduler kernel examines a task status data structure from a corresponding stream and updates dependency counts for tasks and events within the stream. When each task dependency for a waiting event is satisfied, an associated task may execute.Type: ApplicationFiled: May 9, 2012Publication date: November 14, 2013Inventor: Luke DURANT
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Patent number: 8584137Abstract: An image processing system including: storage; image processing devices; and job divider dividing an unprocessed job into partial jobs and store them into storage. Each image processing device includes: a first judging part to judge whether partial job stored in the storage can be processed by own device; a transmitter to, if the judgment result is positive, transmit and store first information indicating condition for processing the partial job, to the storage; an obtaining part to obtain second information indicating condition with which another image processing device processes the partial job, from the storage; a second judging part to judge whether own device should process the partial job, in accordance with standard common to the image processing devices, referring to first and second information; and job processor to process the partial job if second judging part judges positively.Type: GrantFiled: January 25, 2008Date of Patent: November 12, 2013Assignee: Konica Minolta Business Technologies, Inc.Inventors: Yasuhiro Yamauchi, Taisuke Akahori, Kazuhiro Tomiyasu, Eiichi Yoshida, Tomoko Maruyama, Kenichi Sawada
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Patent number: 8578389Abstract: Methods and systems facilitating a programmer to program parts of a program in data flow programming to produce directed acyclic graphs (“DAGs”), and then merge the graphs at runtime for efficiency and scalability. Large merged DAG can typically be processed with greater efficiency than the collection of smaller DAGs. As a result, smaller DAGs may be created while the execution of the program realizes the increased efficiency of executing a larger DAG based on the merging of the smaller DAGs. In accordance with methods and systems consistent with the present invention, a programmer creates individual data flow directed acyclic graphs in a program.Type: GrantFiled: May 4, 2004Date of Patent: November 5, 2013Assignee: Oracle America, Inc.Inventor: Michael L. Boucher
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Patent number: 8578390Abstract: A communications manager in a telecommunications transaction server communicates service request messages and service response messages between one or more remotely executing service request processes and one or more service applications executing on the transaction server. A main thread in the communications manager monitors connections requests and initializes other threads. A unique logical communications connection is established between one of the service request processes and the communications manager. The communications manager creates both a read thread and a write thread for each logical communication connection that is validated and active. The read thread communicates service request messages from a service request process to an appropriate service application. The write thread communications service response messages from the service application to the service request process that issues the service request message.Type: GrantFiled: November 7, 2006Date of Patent: November 5, 2013Assignee: Verizon Business Global LLCInventors: Carolyn J. Dillow, Roger N. Tucker
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Patent number: 8572617Abstract: Processor-implemented systems and methods are provided for synchronization of a thread, wherein the thread waits for one or more events to occur before continuing execution. A processor-implemented system and method can include a wait data structure which stores event conditions in order to determine when the thread should continue execution. Event objects, executing on one or more data processors, allow for thread synchronization. A pointer is stored with respect to a wait data structure in order to provide visibility of event conditions to the event objects. The thread continues execution when the stored event conditions are satisfied.Type: GrantFiled: July 21, 2009Date of Patent: October 29, 2013Assignee: SAS Institute Inc.Inventor: Charles Scott Shorb
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Patent number: 8572615Abstract: A synchronization device includes a receiver that receives data from at least two synchronization devices establishing synchronization, and extracts synchronization information and register selection information from the received data, a transmitter that transmits data to each of the at least two synchronization devices establishing synchronization among a plurality of synchronization devices, a first and a second receiving state register that each stores the extracted synchronization information, a second receiving state register that stores the extracted synchronization information, and a controller that stores the extracted synchronization information into the first receiving state register and the second receiving state register alternately based on the register selection information, and controls the transmitter to transmit data including the register selection information to each of the at least two synchronization devices when the extracted synchronization information is completed in one of the first aType: GrantFiled: December 14, 2011Date of Patent: October 29, 2013Assignee: Fujitsu LimitedInventors: Tomohiro Inoue, Yuichiro Ajima, Shinya Hiramoto