Abstract: Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors.

Abstract: Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread.

Abstract: A system and a method are disclosed for batch execution of system calls in an operating system. In one implementation, a processing device configures a system call batching buffer table in a user space of an operating system, the system call batching buffer table including a plurality of system call units, associates a system call number with the system call batching buffer table, and issues a trap instruction to a kernel of the operating system to execute at least one of the plurality of system call units, the trap instruction including the system call number.

Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.

Abstract: A information processing apparatus having a processor is controlled to execute a procedure of reading from the memory attribute information indicating a usage frequency of a register used by a process to be executed as a next process by the processor when the processor switches a process currently being executed, saving a value of the register used by the next process to be executed by the processor to the memory when the usage frequency of the register indicated by the attribute information is larger than a certain frequency, reading from the memory owner information indicating a process using the register to be used by the next process when the usage frequency of the register indicated by the attribute information is larger than the certain frequency, and restoring a register value saved in the memory to the register when the owner information indicates a process other than the next process.

Abstract: A data processing system facilitates virtual machine migration with direct physical access control. The illustrative data processing system comprises a software-programmable trap control associated with hardware registers of a computer that selectively vectors execution control of a virtual machine (VM) between a host and a guest. The data processing system further comprises a logic which is configured for execution on the computer that programs the trap control to enable the virtual machine to directly access the hardware registers when the virtual machine is not migrated and to revoke direct access of the hardware registers in preparation for virtual machine migration.

Abstract: Data is placed in tiered storage with a suitable granularity according to application characteristics. The storage apparatus comprises a controller for managing storage areas, provided by storage media of a plurality of types of varying performance, as pools, and for assigning the storage areas in page units to a virtual volume from any tiered storage among a plurality of types of tiered storage which the pool comprises in response to a data write request from the host computer, wherein, for specific data which is managed by the host computer, the controller specifies an area with a high referencing frequency among the specific data on the basis of organization information of the specific data, and moves this area to another of the tiered storage with a higher performance than an already assigned tiered storage.

Abstract: A system and method to optimize processor performance and minimizing average thread latency by selectively loading a cache when a program state, resources required for execution of a program or the program itself change, is described. An embodiment of the invention supports a “cache priming program” that is selectively executed for a first thread/program/sub-routine of each process. Such a program is optimized for situations when instructions and other program data are not yet resident in cache(s), and/or whenever resources required for program execution or the program itself changes. By pre-loading the cache with two resources required for two instructions for only a first thread, average thread latency is reduced because the resources are already present in the cache.

Abstract: An operating system permits sharing of a sub-process (or process unit) across multiple processes (or tasks). Each shared sub-process has its own context. The sharing is enabled by tracking when a process invokes a sub-process. When a process invokes a sub-process, the process is designated as a parent process of the child sub-process. The invoked sub-process may require use of process level variable data. To enable storage of the process level variable data for each calling process, the variable data is stored in memory using a base address and a fixed offset. Although the based address may vary from process to process, the fixed offset remains the same across processes.

Abstract: Methods, systems, and computer program products for context-based data pre-fetching and notification for applications are described herein. In an embodiment, the method operates by creating a context model that includes context variables and events. The method populates context variables based upon the context of an application and instantiates a context based upon the context model. The method determines whether the context is active or inactive and infers a likely set of data needed by the application. The method executes a data selection function to generate a dataset for the application. In an embodiment, the system includes a module to create and maintain a context model. The system includes modules to: populate context variables within the context model; calculate a dataset for the application; maintain an inference engine; subscribe to changes in the context variables; and generate notifications including a dataset with associated metadata that assists with display of the dataset.

Abstract: A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications, at least one software extension is provided to the operating system. When a specific extension is requested a software exception is generated by the OS. In response to the exception, the least one software extension is called to handle context switch and dynamic configuration of the extendible logic of the microprocessor.

Abstract: An approach is provided in which a request is received from a software module to retrieve a value stored in a pre-defined location. Prior to retrieving the value, an override tank is checked for a corresponding override value. When the override tank includes an override value, the override value in the override tank is provided to the software module. When the override tank fails to include a corresponding override value, an actual value is retrieved from a pre-defined storage location and provided to the software module. In one embodiment, the override value is an override system attribute value. In another embodiment, the override value is an override function return value.

Abstract: Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating system. When the operating system scheduler has no work to schedule on the idle thread units, the operating system may issue a halt or monitor/mwait or other instruction to place the thread unit into an idle state. While the thread unit is idle, from the operating system perspective, the thread unit may be utilized to perform speculative acceleration threads in order to accelerate threads running on non-idle thread units. The context of the idle thread unit is saved prior to execution of the acceleration thread and is restored when the operating system requires use of the thread unit. The acceleration threads are transparent to the operating system. Other embodiments are also described and claimed.

Abstract: An approach is provided in which a request is received from a software module to retrieve a value stored in a pre-defined location. Prior to retrieving the value, an override tank is checked for a corresponding override value. When the override tank includes an override value, the override value in the override tank is provided to the software module. When the override tank fails to include a corresponding override value, an actual value is retrieved from a pre-defined storage location and provided to the software module. In one embodiment, the override value is an override system attribute value. In another embodiment, the override value is an override function return value.

Abstract: A queue control circuit controls the placement and retrieval of a plurality of tasks in a plurality of types of virtual queues. State registers are associated with respective tasks. Each of the state registers stores a task priority order, a queue ID of a virtual queue, and the order of placement in the virtual queue. Upon receipt of a normal placement command ENQ_TL, the queue control circuit establishes, in the state register for the placed task, QID of the virtual queue as the destination of placement and an order value indicating the end of the queue. When a reverse placement command ENQ_TP is received, QID of the destination virtual queue and an order value indicating the start of the queue are established. When a retrieval command DEQ is received, QID is cleared in the destination virtual queue.

Abstract: A method utilizes cluster-awareness to effectively support a live partition mobility (LPM) event and provide recovery from node failure within a Virtual Input/Output (I/O) Server (VIOS) cluster. An LPM utility creates a monitoring thread on a first VIOS on initiation of a corresponding LPM event. The monitoring thread tracks a status of an LPM and records status information in the mobility table of a database. The LPM utility creates other monitoring threads on other VIOSes running on the (same) source server. If the first VIOS VIOS sustains one of multiple failures, the LPM utility provides notification to other functioning nodes/VIOSes. The LPM utility enables a functioning monitoring thread to update the LPM status. In particular, a last monitoring thread may perform cleanup/update operations within the database based on an indication that there are nodes on the first server that are in failed state.

Abstract: A system and method deterministically switches context in a real-time scheduler to guarantee schedule periodicity. The method includes determining a time slice for each of the plurality of processes. The method includes determining a time slice switch duration between consecutive ones of the time slices. The method includes determining a starting point for each time slice. The method includes generating a schedule as a function of the time slices, the time slice switch durations, and the starting points of the time slices. The schedule includes an order for each of the time slices for a respective one of the plurality of processes. Each of the time slices and each of the time slice switch durations are required to run for their entire duration to guarantee a periodicity of the schedule.

Abstract: Disclosed herein are an apparatus and method for managing a data stream distributed parallel processing service. The apparatus includes a service management unit, a Quality of Service (QoS) monitoring unit, and a scheduling unit. The service management unit registers a plurality of tasks constituting the data stream distributed parallel processing service. The QoS monitoring unit gathers information about the load of the plurality of tasks and information about the load of a plurality of nodes constituting a cluster which provides the data stream distributed parallel processing service. The scheduling unit arranges the plurality of tasks by distributing the plurality of tasks among the plurality of nodes based on the information about the load of the plurality of tasks and the information about the load of the plurality of nodes.

Abstract: Application states may be stored and retrieved using policies that define various contexts in which the application is used. The application states may define configurations or uses of the application, including connections to and interactions with other applications. Applications that are virtualized may have state that is defined within a usage context and multiple states or configurations may be stored and recalled based on the usage context. Policies may define the context and what parameters are to be saved, and may be applied when applications are operated in a virtualized manner.

Abstract: A dummy layer generating/finishing section 1301 generates a dummy layer, in the case where a screen layer of a secure virtual machine 101 is generated. In the case where at least one dummy layer is generated, a display driver switching section 1322 switches the display control to the secure virtual machine 101 for causing a screen data combining section 1331 to combine screen layers. On the other hand, in the case where a dummy layer is not generated, the display driver switching section 1322 switches the display control to a non-secure virtual machine 102 for causing a screen data combining section 1321 to combine screen layers.

Abstract: An I/O device performs data input and data output between the I/O device and first and second computers. An I/O switch relays input and output data between the I/O device and each of the first and second computers. A device emulator emulates the I/O device when a virtual machine running on the first computer and directly accessing the I/O device is migrated from the first computer to the second computer. A connection controller controls switching connection between any one of the first and second computers and any one of the I/O device and the device emulator. The first computer is connected to the I/O device and the second computer is connected to the device emulator until the virtual machine running on the first computer is stopped, and the second computer is connected to the I/O device after the virtual machine running on the first computer is stopped.

Abstract: A computer-implemented method for lock-free use of a non-preemptive system resource by a preemptive thread, which may be interrupted. The method comprises registering a non-preemptive system resource and a first level reclaim handler for the non-preemptive system resource with the kernel of an operating system, registering a second level reclaim handler with the kernel, wherein the second level reclaim handler is included in an application program, and running the application program as a preemptive thread using the non-preemptive system resource. The first level reclaim handler is code that is a part of the implementation of the non-preemptive system resource in the kernel. The second level reclaim handler is code that is part of the application and is registered with the kernel before the application uses the non-preemptive system resource. The method enables a preemptive thread using a non-preemptive system resource to be preempted without crashing.

Abstract: A scheduler in a process of a computer system schedules tasks of a task group for concurrent execution by multiple execution contexts. The scheduler provides a mechanism that allows the task group to be cancelled by an arbitrary execution context or an asynchronous error state. When a task group is cancelled, the scheduler sets a cancel indicator in each execution context that is executing tasks corresponding to the cancelled task group and performs a cancellation process on each of the execution contexts where a cancel indicator is set. The scheduler also creates local aliases to allow task groups to be used without synchronization by execution contexts that are not directly bound to the task groups.

Abstract: A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.

Abstract: A method and apparatus for transferring architected state bypasses system memory by directly transmitting architected state between processor cores over a dedicated interconnect. The transfer may be performed by state transfer interface circuitry with or without software interaction. The architected state for a thread may be transferred from a first processing core to a second processing core when the state transfer interface circuitry detects an error that prevents proper execution of the thread corresponding to the architected state. A program instruction may be used to initiate the transfer of the architected state for the thread to one or more other threads in order to parallelize execution of the thread or perform load balancing between multiple processor cores by distributing processing of multiple threads.

Abstract: Embodiments of a system and method manage a configuration of a plurality of content switching devices in a networked system by generating a first configuration data file and translating the first configuration data file into one or more device specific configuration data files, each device specific configuration file corresponding to a device type of the one or more content switching devices. Some embodiments of the system and method then communicate the one or more device specific configuration data files to each content switching device of a corresponding device type to configure each content switching device.

Abstract: Embodiments describe herein provide an apparatus, a computer readable medium and a method for simultaneously processing tasks within an APD. The method includes processing a first task within an APD. The method also includes reducing utilization of the APD by the first task to facilitate simultaneous processing of the second task, such that the utilization remains below a threshold.

Abstract: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20a through 20n from each other.

Abstract: Methods, apparatuses, and computer program products for utilizing a kernel administration hardware thread of a multi-threaded, multi-core compute node of a parallel computer are provided. Embodiments include a kernel assigning a memory space of a hardware thread of an application processing core to a kernel administration hardware thread of a kernel processing core. A kernel administration hardware thread is configured to advance the hardware thread to a next memory space associated with the hardware thread in response to the assignment of the kernel administration hardware thread to the memory space of the hardware thread. Embodiments also include the kernel administration hardware thread executing an instruction within the assigned memory space.

Abstract: Embodiments maintain high availability of software application instances in a fault domain. Subordinate hosts are monitored by a master host. The subordinate hosts publish heartbeats via a network and datastores. Based at least in part on the published heartbeats, the master host determines the status of each subordinate host, distinguishing between subordinate hosts that are entirely inoperative and subordinate hosts that are operative but partitioned (e.g., unreachable via the network). The master host may restart software application instances, such as virtual machines, that are executed by inoperative subordinate hosts or that cease executing on partitioned subordinate hosts.

Abstract: A mechanism for providing an operating system history is disclosed. A method includes placing, by an operating system (OS) of a processing device, a pointer to context of a first application in a history context of plurality of applications in a direct interface array (DIR) of the OS upon indication of switching from an interface of a first application to the interface of a second application. The method also includes moving the pointer from the context of the first application to the context of the second application in the DIR in view of an indication of a closing of the interface of the second application. The second application is closed in a foreground of the OS and is executing in a background of the OS. The method further includes providing the interface of the second application in the foreground of the OS upon activation of a global back function.

Abstract: A virtual storage management method that can increase the overall processing speed while preventing a processor from being overloaded. A request for acquisition of a memory area in a primary storage device is received from a process executed by a processor. It is determined whether or not the process that has made the acquisition request is a utility process executable in cooperation with another process. Control is provided so as to restrict swap-out of the utility process when it is determined that the process that has made the received acquisition request is a utility process executable in cooperation with another process, and a process cooperating with the utility process executed by the processor is a preferred process of which swap-out is restricted, and a processor utilization of the preferred process is greater than a predetermined value.

Abstract: A method and system for creating and executing tasks within a multithreaded application composed according to the OpenMP application programming interface (API). The method includes generating threads within a parallel region of the application, and setting a counter equal to the quantity of the threads. The method also includes, for each one of the plurality of threads, assigning an implicit task, and executing the implicit task. Further, the method includes, upon encountering a task construct, during execution of the implicit tack, for an explicit asynchronous task generating the explicit asynchronous task, adding the explicit asynchronous task to a first task queue, where the first task queue corresponds to the one of the plurality of threads; and incrementing the counter by one.

Abstract: A method and system for managing software application states selects a plurality of stateful applications for reinstatement at a later time. A set of data contexts is generated based on the selected applications. The set of data contexts is pushed onto a data stack. Thereafter the set of data contexts is popped from the data stack for reinstatement. Each step or function may be initiated automatically or through user input, and may be used in a single-user, multi-user or collaborative setting.

Abstract: Architecture that facilitates a user experience for continuing computer and/or application tasks across user devices. Task status can be synchronized across devices via a cloud service or via a short-range wireless peer-to-peer (P2P). When applied to searching, for example, the user experience enables users to resume the same search session across devices in several ways. The disclosed architecture can also be extended to other tasks such as web browsing, online meetings, office application sessions, etc. The client application of each device collects the states of each application (e.g., document links, websites, online meeting information, etc.) as part of the synchronization, and uses the states to resume the same applications on different devices (e.g., open the same word processing document, a browser to the same websites, re-join online meetings, etc.).

Abstract: A multi-core processing system includes a first processing core, a second processing core, a task manager coupled to the first and second processing cores. The task manager is operable to receive context information of a task from the first processing core and provide the context information to the second processing core. The second processing core continues executing the task using the context information.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: An apparatus and method for controlling a multi-core SoC including a main core and at least one sub-core are disclosed. The apparatus includes a determination unit, a storage unit, and a control unit. The determination unit determines whether or not to drive the sub-core by taking the performance or power of the multi-core SoC into consideration. The storage unit stores state information including a register of the main core or the sub-core in accordance with a determination of the determination unit. The control unit performs control so that the main core and the sub-core execute a sub-task, that is, a task of the sub-core, through exchange by sharing the state information.

Abstract: A virtual machine system is provided with a processor having only two privileged modes, a low privileged mode and a high privileged mode, and achieves both a security function for protecting digital copyrighted works or the like and an operating system switching function that guarantees system reliability. The virtual machine system is provided with a first and a second processor and executes a hypervisor on the first processor in the high privileged mode. An operating system on the second processor is executed by cooperation between the hypervisor running on the first processor and a program running on the second processor in low privileged mode. This eliminates the need for running the hypervisor on the second processor in the high privileged mode, thus allowing for execution on the second processor in the high privileged mode of a program for implementing the security function.

Abstract: An information processing apparatus includes a user interface, a switching unit, and a computer. The user interface is for a user that operates a first processing unit that runs a first operating system or a second processing unit that runs a second operating system. The switching unit selectively switches between the first processing unit and the second processing unit to be associated with the user interface. The computer functions as the first processing unit. The computer functions as the second processing unit. The computer runs a first application program on the first operating system. The computer activates, on the second operating system, a second application program related to the first application program, in a state in which the first processing unit is associated with the user interface. The computer controls the switching unit upon completion of the activation of the second application program.

Abstract: Methods and systems for implementing virtual processors are disclosed. For example, in an embodiment a processing apparatus configured to act as a plurality of virtual processors includes a first virtual program space that includes a first program execution memory, the first program execution memory including code to run a non-real-time operating system capable of supporting a one or more non-real-time applications, a second virtual program space that includes a second program execution memory, the second program execution memory including code to run one or more real-time processes, and a central processing unit (CPU) configured to operate in a first operating mode and a second operating mode, the CPU being configured to perform operating system and application activities using the first virtual program space for the first operating mode without using the second virtual program space and without appreciably interfering with the one or more real-time processes that are running in the second operating mode.

Abstract: Provided is a method and apparatus for an adaptive context switching for a fast block input/output. The adaptive context switching method may include: requesting, by a process, an input/output device to perform an input/output of data; comparing a Central Processing Unit (CPU) effectiveness based on whether the context switching is performed; and performing the input/output through the context switching to a driver context of the input/output device, or directly performing, by the process, the input/output based on a comparison result of the CPU effectiveness.

Abstract: Systems and methods of enhancing computing performance may provide for detecting a request to acquire a lock associated with a shared resource in a multi-threaded execution environment. A determination may be made as to whether to grant the request based on a context-based lock condition. In one example, the context-based lock condition includes a lock redundancy component and an execution context component.

Abstract: Disclosed is an automatic optimization system capable of searching for an allocation with a good performance from among a plurality of task allocations which can be scheduled in a system of a development target configured with a plurality of periodic tasks. A task allocation optimization system for a multi-core processor including a plurality of cores calculates a response time of each of a plurality of tasks which are core allocation decision targets, and outputs an accumulative value of the calculated response time as an evaluation function value which is an index representing excellence of a task allocation. A task allocation from which a good evaluation function value is calculated is searched based on the evaluation function value. A candidate having a good evaluation function value among a plurality of searched task allocation candidates is held.

Abstract: A computer-implemented method for reclaiming storage space from virtual machine disk images may include (1) identifying a virtual machine that uses a virtual machine disk image as a virtual disk for storage, the virtual machine disk image being stored on a thin-provisioned volume within a host file system, (2) determining that a portion of the virtual machine disk image represents a portion of the virtual disk that is unused by a file system of the virtual machine, (3) based on determining that the portion of the virtual machine disk image represents the portion of the virtual disk that is unused by the file system of the virtual machine, marking the portion of the virtual machine disk image for reclamation from the thin-provisioned volume, and (4) reclaiming the marked portion of the virtual machine disk image from the thin-provisioned volume. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Operating a data processing system comprises defining a plurality of profiles, each profile comprising a list of one or more applications; receiving a defined user input requesting a switch from a first profile to a second profile; hibernating the (or each) application listed in the first profile; and recalling from hibernation the (or each) application listed in the second profile. Preferably, a graphical user interface is adjusted to reflect a change in status of each application that has been hibernated or recalled from hibernation.

Abstract: A method for controlling processor usage on a computing device is described. The method includes identifying targeted processes and obtaining a total processor usage for a processor on the computing device. The method also includes determining an amount of time to suspend threads within the targeted processes and suspending the threads for the determined amount of time.

Abstract: A technique for managing read-copy update readers that have been preempted while executing in a read-copy update read-side critical section. A single blocked-tasks list is used to track preempted reader tasks that are blocking an asynchronous grace period, preempted reader tasks that are blocking an expedited grace period, and preempted reader tasks that require priority boosting. In example embodiments, a first pointer may be used to segregate the blocked-tasks list into preempted reader tasks that are and are not blocking a current asynchronous grace period. A second pointer may be used to segregate the blocked-tasks list into preempted reader tasks that are and are not blocking an expedited grace period. A third pointer may be used to segregate the blocked-tasks list into preempted reader tasks that do and do not require priority boosting.

Abstract: Operating a data processing system comprises defining a plurality of profiles, each profile comprising a list of one or more applications; receiving a defined user input requesting a switch from a first profile to a second profile; hibernating the (or each) application listed in the first profile; and recalling from hibernation the (or each) application listed in the second profile. Preferably, a graphical user interface is adjusted to reflect a change in status of each application that has been hibernated or recalled from hibernation.

Abstract: A technique for executing normally interruptible threads of a process in a non-preemptive manner includes in response to a first entry associated with a first message for a first thread reaching a head of a run queue, receiving, by the first thread, a first wake-up signal. In response to receiving the wake-up signal, the first thread waits for a global lock. In response to the first thread receiving the global lock, the first thread retrieves the first message from an associated message queue and processes the retrieved first message. In response to completing the processing of the first message, the first thread transmits a second wake-up signal to a second thread whose associated entry is next in the run queue. Finally, following the transmitting of the second wake-up signal the first thread releases the global lock.