Abstract: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.

Abstract: A memory device includes: a memory including a first magnetic layer having no retaining force and a second magnetic layer having a retaining force, the first magnetic layer and the second magnetic layer being stacked; a first magnet to magnetize the first magnetic layer in a first direction; and a second magnet to apply a magnetic field to a region through which the memory passes when the memory is removed and to magnetize the second magnetic layer in a second direction.

Abstract: A perpendicular spin-transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

Abstract: A device comprising: an assembly consisting of two, respectively upper and lower thin layers each forming a ferromagnetic element and separated by a thin layer forming a non magnetic element, said assembly being made up so that the layers forming the ferromagnetic elements are magnetically coupled through the layer forming a non magnetic element; an electrode, a layer forming a ferroelectric element in which the polarization may be oriented in several directions by applying an electric voltage through said layer, said layer forming a ferroelectric element being positioned between the layer forming a lower ferromagnetic element and the electrode; said device being configured so as to allow control of the magnetic configuration of the layers forming ferromagnetic elements by the direction of the polarization in the layer forming a ferroelectric element.

Abstract: A spin logic device which includes an electron confinement layer confining an electron gas in a two-dimensional area (2DEG) subtended by a direction x and a direction y, the latter perpendicular to the former. The spin logic device is configured for the 2DEG to support a persistent spin helix (PSH) formed therein with a given spin component oscillating with periodicity ? along direction x but not oscillating along direction y. Majority logic circuit of the spin logic device includes: at least one input device energizable to create respective local spin-polarizations of the 2DEG in first regions of the confinement layer. The input device is configured to detect in a second region of the confinement layer an average spin-polarization of the 2DEG diffused through resulting PSHs, wherein a projection of a distance between the second region and first regions onto direction x is equal to n?/a, n integer, a equal to 2 or 4.

Abstract: A multi-bit cell of magnetic random access memory comprises a magnetoresistive element including first and second free layers, each free layer comprising a reversible magnetization direction directed substantially perpendicular to a layer plane in its equilibrium state and a switching current, first and second tunnel barrier layers, and a pinned layer comprising a fixed magnetization direction directed substantially perpendicular to the layer plane, the pinned layer is disposed between the first and second free layers and is separated from the free layers by one of the tunnel barrier layers; a selection transistor electrically connected to a word line, and a bit line intersecting the word line; the magnetoresistive element is disposed between the bit line and the selection transistor and is electrically connected to the bit line and the selection transistor, wherein the first and second free layers have substantially different switching currents.

Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; a first electrode and a second electrode provided to different locations of the magnetic nanowire; a third electrode including a magnetic layer, the third electrode being provided to a location of the magnetic nanowire between the first electrode and the second electrode; an intermediate layer provided between the magnetic nanowire and the third electrode, the intermediate layer being in contact with the magnetic nanowire and the third electrode; a fourth electrode of a nonmagnetic material provided onto the magnetic nanowire and being on the opposite side of the magnetic wire from the third electrode; and an insulating layer provided between the magnetic nanowire and the fourth electrode, the insulating layer being in contact with the magnetic nanowire and the fourth electrode.

Abstract: A magnetic memory element includes a first magnetic layer, a second magnetic layer, a first intermediate layer, a first magnetic wire, a first input unit, and a first detection unit. The first magnetic layer has magnetization fixed. The second magnetic layer has magnetization which is variable. The first intermediate layer is between the first magnetic layer and the second magnetic layer. The first magnetic wire extends in a first direction perpendicular to a direction connecting from the first magnetic layer to the second magnetic layer and is adjacent to the second magnetic layer. In addition, write-in is performed by propagating a first spin wave through the first magnetic wire and by passing a first current from the first magnetic layer toward the second magnetic layer. Read-out is performed by passing a second current from the first magnetic layer toward the second magnetic layer.

Abstract: A perpendicular spin transfer torque magnetic random access memory (STTMRAM) element includes a fixed layer having a magnetization that is substantially fixed in one direction and a barrier layer formed on top of the fixed layer and a free layer. The free layer has a number of alternating laminates, each laminate being made of a magnetic layer and an insulating layer. The magnetic layer is switchable and formed on top of the barrier layer. The free layer is capable of switching its magnetization to a parallel or an anti-parallel state relative to the magnetization of the fixed layer during a write operation when bidirectional electric current is applied across the STTMRAM element. Magnetic layers of the laminates are ferromagnetically coupled to switch together as a single domain during the write operation and the magnetization of the fixed and free layers and the magnetic layers of the laminates have perpendicular anisotropy.

Abstract: A memory element has a layered configuration, including a memory layer in which a magnetization direction is changed corresponding to information; the magnetization direction being changed by applying a current in a lamination direction of the layered configuration to record the information in the memory layer, a magnetization-fixed layer in which a magnetization direction is fixed, an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer, and a perpendicular magnetic anisotropy inducing layer, the memory layer including a first ferromagnetic layer, a first bonding layer, a second ferromagnetic layer, a second bonding layer and a third ferromagnetic layer laminated in the stated order.

Abstract: One embodiment of a magnetic memory device comprises a substrate and a plurality of planar memory arrays stacked on the substrate, each memory array includes a plurality of parallel first conductive lines, each first conductive line includes a ferromagnetic cladding, a plurality of parallel second conductive lines overlapping the first conductive lines at a plurality of intersection regions, a plurality of magnetic tunnel junctions, each magnetic tunnel junction has a controllable electrical resistance, is disposed at an intersection region and electrically coupled to one of the first conductive lines at its first end and to one of the second conductive lines at its second end. The electrical resistance of the magnetic tunnel junction is controlled by a joint effect of a spin-polarized current running between the first and second ends and a bias magnetic field applied simultaneously to said each magnetic tunnel junction. Other embodiments are described and shown.

Abstract: Methods using a sequence of externally generated magnetic fields to initialize the magnetization directions of each of the layers in perpendicular MTJ MRAM elements for data and reference bits when the required magnetization directions are anti-parallel are described. The coercivity of the fixed pinned and reference layers can be made unequal so that one of them can be switched by a magnetic field that will reliably leave the other one unswitched. Embodiments of the invention utilize the different effective coercivity fields of the pinned, reference and free layers to selectively switch the magnetization directions using a sequence of magnetic fields of decreasing strength. Optionally the chip or wafer can be heated to reduce the required field magnitude. It is possible that the first magnetic field in the sequence can be applied during an annealing step in the MRAM manufacture process.

Abstract: A semiconductor device includes a memory cell. The cell includes: a magnetic recording layer (MRL) formed of ferromagnetic material; first and second magnetization fixed layers (MFLs) coupled to the MRL; first and second reference layers (RLs) opposed to the MRL; and first and second tunnel barrier films (TBFs) inserted between the MRL and the first and second reference layers (RLs), respectively. The first MFL has a magnetization fixed in a first direction, and the second MFL has a magnetization fixed in a second direction opposite to the first direction. The first and second RLs and the first and second TBFs are positioned between the first and second MFLs. The first RL has a magnetization fixed in a third direction which is selected from the first and second directions, and the second RL has a magnetization fixed in a fourth direction opposite to the third direction.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer.

Abstract: One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.

Abstract: A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. The tunnel junction programming circuit is configured to apply a current through the magnetic tunnel junction to generate a write temperature in the magnetic tunnel junction and to write to the free layer of the magnetic tunnel junction.

Abstract: The present disclosure concerns a multilevel magnetic element comprising a first tunnel barrier layer between a soft ferromagnetic layer having a magnetization that can be freely aligned and a first hard ferromagnetic layer having a magnetization that is fixed at a first high temperature threshold and freely alignable at a first low temperature threshold. The magnetic element further comprises a second tunnel barrier layer and a second hard ferromagnetic layer having a magnetization that is fixed at a second high temperature threshold and freely alignable at a first low temperature threshold; the soft ferromagnetic layer being comprised between the first and second tunnel barrier layers. The magnetic element disclosed herein allows for writing four distinct levels using only a single current line.

Abstract: A thermal spin torque transfer magnetoresistive random access memory (MRAM) apparatus includes a magnetic tunnel junction and a tunnel junction programming circuit. The magnetic tunnel junction includes a reference layer having a fixed magnetic polarity, a tunnel barrier layer, and a free layer on an opposite side of the tunnel barrier layer from the reference layer. The free layer includes a first layer having a first Curie temperature and a second layer having a second Curie temperature different from the first Curie temperature. The tunnel junction programming circuit is configured to apply a current through the magnetic tunnel junction to generate a write temperature in the magnetic tunnel junction and to write to the free layer of the magnetic tunnel junction.

Abstract: Provided is a magnetic tunneling junction device including a fixed magnetic structure; a free magnetic structure; and a tunnel barrier between the fixed magnetic structure and the free magnetic structure, at least one of the fixed magnetic structure and the free magnetic structure including a perpendicular magnetization preserving layer, a magnetic layer between the perpendicular magnetization preserving layer and the tunnel barrier, and a perpendicular magnetization inducing layer between the perpendicular magnetization preserving layer and the magnetic layer.

Abstract: A semiconductor device includes: a spin torque written in-plane magnetization magnetoresistive element, placed over the main surface of a semiconductor substrate, whose magnetization state can be changed according to the direction of a current flow; and a first wiring electrically coupled with the magnetoresistive element and extended toward the direction along the main surface. The aspect ratio of the magnetoresistive element as viewed in a plane is a value other than 1. In a memory cell area where multiple memory cells in which the magnetoresistive element and a switching element are electrically coupled with each other are arranged, the following measure is taken: multiple magnetoresistive elements adjoining to each other in the direction of length of each magnetoresistive element as viewed in a plane are so arranged that they are not on an identical straight line extended in the direction of length.

Abstract: Magnetic memory devices are provided, the devices include at least memory cell and a reference cell on a substrate. The memory cells include a first base magnetic layer, a free layer, and a first tunnel barrier layer between the first base magnetic layer and free layer. The reference memory cell includes a second base magnetic layer, a reference magnetic layer, and a second tunnel barrier layer between the second base magnetic layer and reference magnetic layer. The reference magnetic layer has a magnetic direction substantially perpendicular to that of the free layer.

Abstract: A memory element including a memory layer to hold the information by the magnetization state of a magnetic substance, a magnetization pinned layer having magnetization serving as a reference of the information stored in the memory layer, an intermediate layer formed from a nonmagnetic substance disposed between the memory layer and the magnetization pinned layer, a magnetic coupling layer disposed adjoining the magnetization pinned layer and opposing to the intermediate layer, and a high coercive force layer disposed adjoining the magnetic coupling layer, wherein the information is stored by reversing magnetization of the memory layer, making use of spin torque magnetization reversal generated along with a current passing in the lamination direction of the layered structure including the memory layer, the intermediate layer, and the magnetization pinned layer, and the magnetic coupling layer has a two-layer laminate structure.

Abstract: A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film.

Abstract: A magnetoresistive effect element includes: a magnetization free layer having an invertible magnetization; an insulating layer being adjacent to the magnetization free layer; and a magnetization fixed layer being adjacent to the insulation layer and in an opposite side of the insulation layer to the magnetization free layer. The magnetization free layer includes: a first magnetization free layer being adjacent to the insulating layer and comprising Fe or Co; and a second magnetization free layer being adjacent to the first magnetization layer and comprising NiFeB.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer.

Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. High and low resistance states of the MRLC occurs based on the relative magnetization orientations of SRL and CFL. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. A voltage-induced switching principle can be used with MRLC embodiments of the present invention to switch the SRL to parallel or anti-parallel with respect to the magnetization CFL in both perpendicular and in-plane anisotropy embodiments.

Abstract: A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. The high resistance state of the MRLC occurs when the switchable reference and common free layers have opposite magnetization orientations. The low resistance state occurs when the orientations are the same. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. The SRL is switched with reference to the CFL by a voltage effect generated by a selected longer voltage pulse that does not switch the CFL.

Abstract: According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a memory region; and a conductive region. The transistor controls a conduction of each of a current in a first direction flowing between the first line and the second line and a current in a second direction opposite to the first direction. The memory region has a first magnetic tunnel junction element which is connected between the first line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction. The conductive region is connected between the second line and the other end of the transistor.

Abstract: Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.

Abstract: A carrier-mediated magnetic phase change spin transistor is disclosed. In general, the spin transistor includes a Dilute Magnetic Semiconductor (DMS) channel and a gate stack formed on the DMS channel. The gate stack includes a multiferroic gate dielectric on the DMS channel, and a gate contact on a surface of the multiferroic gate dielectric opposite the DMS channel. The multiferroic gate dielectric is formed of a multiferroic material that exhibits a cross-coupling between magnetic and electric orders (i.e., magnetoelectric coupling), which in one embodiment is BiFeO3 (BFO). As a result, the multiferroic material layer enables an electrically modulated magnetic exchange bias that enhances paramagnetic to ferromagnetic switching of the DMS channel. The DMS channel is formed of a DMS material, which in one embodiment is Manganese Germanium (MnGe). In one embodiment, the DMS channel is a nanoscale DMS channel.

Abstract: A spintronic electronic apparatus having a multilayer structure. The apparatus includes a substrate, having disposed in succession upon the substrate; a bottom interface layer; a pinned layer; a tunneling barrier; a free layer; and a top interface layer, wherein the apparatus operates as a non-resonant magnetic tunnel junction in a large amplitude, out-of-plane magnetization precession regime having weakly current dependent, large diode volt-watt sensitivity when external microwave signals that exceed a predetermined threshold current and have a frequency that is lower than a predetermined level excite the magnetization precession.

Abstract: A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed.

Abstract: A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed.

Abstract: A magnetic resistance memory apparatus capable of implementing various levels and a method of driving the same are provided. The magnetic resistance memory apparatus includes a first magnetic device that includes a fixed layer having a fixed magnetization direction, a tunnel layer disposed on the fixed layer, and a first free layer disposed on the tunnel layer having a variable magnetization direction, and a second magnetic device disposed on the first magnetic device including a plurality of free layers insulated with a spacer layer interposed.

Abstract: A relation between a drive current of a selection transistor of a magnetic memory and a threshold magnetization switching current of the magnetoresistance effect element is optimized. In order to optimize the relation between the drive current of the selection transistor and the threshold magnetization switching current of the magnetoresistance effect element 101 of the magnetic memory cell, a mechanism 601-604 for dropping the threshold magnetization switching current on “1” writing is provided that applies a magnetic field that is in the inverse direction of the pinned layer to the recording layer of the magnetoresistance effect element.

Abstract: A method of initializing a magnetic random access memory (MRAM) element that is configured to store a state when electric current flows therethrough is disclosed. The MRAM element includes a first magnetic tunnel junction (MTJ) for storing a data bit and a second MTJ for storing a reference bit. The direction of magnetization of the FL is determinative of the data bit stored in the at least one MTJ and each MTJ further includes a magnetic reference layer (RL) having a magnetization with a direction that is perpendicular to the film plane, and a magnetic pinned layer (PL) having a magnetization with a direction that is perpendicular to the film plane. The direction of magnetization of the RL and the PL are anti-parallel relative to each other in the first MTJ. The direction of magnetization of the FL, the RL and the PL are parallel relative to each other in the second MTJ for storing reference bit.

Abstract: Magnetoresistive structures, memory devices including the same, and methods of manufacturing the magnetoresistive structures and the memory devices, include a plurality of free layers each having a magnetization direction that is changeable, a separation layer covering at least two of the plurality of free layers, and at least one pinned layer opposing the plurality of free layers. The separation layer is between the at least one pinned layer and the plurality of free layers. The at least one pinned layer has a magnetization direction that is fixed.

Abstract: A magnetic device includes a reference layer, the magnetization direction of which is fixed, and a storage layer, the magnetization direction of which is variable. In a write mode, the magnetization direction of the storage layer is changed so as to store a “1” or a “0” in the storage layer. In a reading mode, the resistance of the magnetic device is measured so as to know what is stored in the storage layer. The magnetic device also includes a control layer, the magnetization direction of which is variable. The magnetization direction of the control layer is controlled so as to increase the effectiveness of the spin-transfer torque in the event writing to the storage layer is desired, and to decrease the effectiveness of the spin-transfer torque in the event reading the information contained in the storage layer, without modifying the information, is desired.

Abstract: A semiconductor storage device according to the present embodiment includes a magnetic tunnel junction element capable of storing data according to a change in resistance state and rewriting the data using a current. A cell transistor is provided for the magnetic tunnel junction element and is placed in a conducting state when a current is allowed to flow through the magnetic tunnel junction element. A current limiter limits a current flowing through the cell transistor and the magnetic tunnel junction element upon data writing.

Abstract: A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body.

Abstract: A method of programming a MTJ includes selecting a MTJ that is coupled to an access transistor at the drain of the access transistor. The gate of the access transistor is coupled to a selected word line (WL), the selected WL is substantially at a first voltage, Vdd; whereas the WLs that are not coupled to the MTJ are left to float. A second voltage, Vx, is applied to the unselected bit lines (BLs) and further applied to a source line (SL), the SL being coupled to the source of the access transistor. A third voltage, Vdd or 0 Volts, is applied to a selected BL, the selected BL is coupled the MTJ. The first voltage is applied to a SL, the SL is coupled to the source of the access transistor thereby causing the WL to boot above the first voltage.

Abstract: An atomic-scale structure according to one embodiment has a net magnetic moment of zero or about zero, two or more stable magnetic states, and an array of atoms that has magnetic moments that alternate between adjacent magnetic atoms along one or more directions. Such structures may be used to store data at ultra-high densities. An antiferromagnetic nanostructure according to another embodiment includes multiple arrays each corresponding to a bit. Each array has at least eight antiferromagnetically coupled magnetic atoms. Each array has at least two readable magnetic states that are stable for at least one picosecond. Each array has a net magnetic moment of zero or about zero. No external stabilizing structure exerts influence over the arrays for stabilizing the arrays. Each array has 100 atoms or less along a longest dimension thereof.

Abstract: A magnetoresistive random access memory (MRAM) apparatus includes a first conductive line and a second conductive line. A magnetic tunnel junction is in electrical communication with the first conductive line and the second conductive line. The magnetic tunnel junction includes at least one programmable magnetic layer. The MRAM apparatus also includes an insulating layer radially surrounding the magnetic tunnel junction, and the insulating layer has a cavity adjacent to the magnetic tunnel junction.

Abstract: The invention relates to a material composed of nanoparticles essentially comprising a spin transition compound. The compound corresponds to the formula [ ( Fe 1 - y ? M y ? L 3 ) w ? L 3 ] [ X 2 x ? ( 1 - z x ? ) ? Y 2 ? ? z x ? ] w in which L represents a 1,2,4-triazole ligand carrying an R substituent on the nitrogen in the 4 position; X is an anion having the valency x, 1?x?2; Y is an anion other than X having the valency x?, 1?x??2; R is an alkyl group or an R1R2N— group in which R1 and R2 represent, each independently of the other, H or an alkyl radical; M is a metal having a 3d4, 3d5, 3d6 or 3d7 configuration, other than Fe; 0?y?1; 0?z?2; 3?w?1500. Applications: thermochromic pigment, data storage, optical limiters, contrast agent.

Abstract: A mechanism is provided for reading a cross point cell array. Voltage biasing is applied to the cross point cell array to determine a state of a target cell on a selected bit line. A negative magnetic field is generated for a selected write bit line corresponding to the target cell. A first current is measured through a selected word line responsive to the negative magnetic field. A positive magnetic field is generated for the selected write bit line corresponding to the target cell. A second current is measured through the selected word line responsive to the positive magnetic field. The state of the target cell is determined based on the first current relative to the second current.

Abstract: There is disclosed a memory element including a memory layer that maintains information through the magnetization state of a magnetic material, a magnetization-fixed layer with a magnetization that is a reference of information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer. The storing of the information is performed by inverting the magnetization of the memory layer by using a spin torque magnetization inversion occurring according to a current flowing in the lamination direction of a layered structure having the memory layer, the intermediate layer, and the magnetization-fixed layer, the memory layer includes an alloy region containing at least one of Fe and Co, and a magnitude of an effective diamagnetic field which the memory layer receives during magnetization inversion thereof is smaller than the saturated magnetization amount of the memory layer.

Abstract: According to one embodiment, a magnetoresistive element includes an electrode layer, a first magnetic layer, a second magnetic layer and a nonmagnetic layer. The electrode layer includes a metal layer including at least one of Mo, Nb, and W. The first magnetic layer is disposed on the metal layer to be in contact with the metal layer and has a magnetization easy axis in a direction perpendicular to a film plane and is variable in magnetization direction. The second magnetic layer is disposed on the first magnetic layer and has a magnetization easy axis in the direction perpendicular to the film plane and is invariable in magnetization direction. The nonmagnetic layer is provided between the first and second magnetic layers. The magnetization direction of the first magnetic layer is varied by a current that runs through the first magnetic layer, the nonmagnetic layer, and the second magnetic layer.

Abstract: A memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a word line. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a unipolar voltage across the magnetic tunnel junction data cell. A diode is electrically coupled between the magnetic tunnel junction data cell and the word line or bit line. A voltage source provides the unipolar voltage across the magnetic tunnel junction data cell that writes the high resistance state and the low resistance state.

Abstract: A method of forming a magnetoresistive random access memory (MRAM) apparatus includes forming a first conductive line on a first insulating layer, forming a second insulating layer on the first conductive line and forming a magnetic tunnel junction through the second insulating layer to contact the first conductive line. The method also includes forming a cavity adjacent to the magnetic tunnel junction in the second insulating layer and forming a second conductive line on the second insulating layer to contact the magnetic tunnel junction.

Abstract: A magnetic random access memory (MRAM) cell includes an embedded MRAM and an access transistor. The embedded MRAM is formed on a number of metal-interposed-in-interlayer dielectric (ILD) layers, which each include metal dispersed there through and are formed on top of the access transistor. A magneto tunnel junction (MTJ) is formed on top of a metal formed in the ILD layers that is in close proximity to a bit line. An MTJ mask is used to pattern the MTJ and is etched to expose the MTJ. Ultimately, metal is formed on top of the bit line and extended to contact the MTJ.