Abstract: Described embodiments provide an interleaved sampler having N sample and hold circuits for sampling an input signal, and M multiplexers. Each multiplexer is adapted to couple all N of the plurality of sample and hold circuits to a respective output of the interleaved sampler. The interleaved sampler samples at a sample rate of fs, has an interleaved sampling period of M/fs, where M is greater than one and less than N. Because there are more sample and hold circuits than there are samples taken during an interleaved sampling period, different combinations of the sample and hold circuits are used from interleaved sample period to interleaved sample period. This reduces spurious tones generated from offset voltages when using interleaved sample and hold circuits. The order of the sample and hold circuits are clocked might be random, pseudorandom, or a fixed pattern longer than the interleaved sampling period.

Abstract: Approaches for determining the timing latency of a communication path are described. Some embodiments involve a method for testing timing latency. A signal is driven on a first data path and is returned through a second data path through a loop back element. The timing latency of at least a portion of the communication path that includes the first data path and the second data path is tested using the signal returned on the second data path. The gain of the second data path is adjusted to a test value during the testing of the timing latency.

Abstract: A motor drive device has a driver circuit generating an output current for a motor and a control circuit controlling the drive circuit. The control circuit, when switching the driver circuit from a PWM-driving state to a linear-driving state, controls the timing of the switching such that the path of the output current does not change between before and after the switching, and in addition, in the middle of the switching, switches the driver circuit to a high-output-impedance state momentarily.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a read/write head configured to read data from and write data to the storage disk, and control circuitry coupled to the read/write head and configured to process data received from and supplied to the read/write head. The control circuitry comprises clock adjustment circuitry configured to generate a control signal for adjusting a parameter of a clock signal based at least in part on timing information obtained by detecting a timing pattern on a surface of the storage disk. The control signal is generated utilizing at least a predictive correction control loop, with the clock adjustment circuitry comprising predictive control firmware that implements at least a portion of the predictive correction control loop.

Abstract: A servo control device includes a plurality of reproduction channels, a plurality of analog/digital (A/D) converters, a servo error detecting circuit that generates a servo error signal, a servo signal processing device that executes predetermined processing for the servo error signal to generate a control signal, and a sampling frequency converter that converts the sampling frequency between the servo error detecting circuit and the servo signal processing device. A first clock is included as a sampling clock of the A/D converters and a processing clock of the servo error detecting circuit. A second clock is included as a processing clock of the servo signal processing device. The sampling frequency converter converts the sampling frequency by processing the servo error signal by the servo error detecting circuit in synchronization with the first clock and processing the signal processed in synchronization with the first clock in synchronization with the second clock.

Abstract: Aspects of the disclosure provide a signal processing circuit that includes a signal processing circuit includes a processing path configured to process an electrical signal to produce input data samples, and a feed-forward correction module configured to delay the input data samples to produce delayed data samples, to apply the delayed data samples to a timing loop during periods when a profile variation of the data samples is not detected, and to apply the input data sample to the timing loop during periods when a profile variation of the data samples is detected.

Abstract: A player device uses playlists having names of contents. Users can update the playlists via network. The player device includes a storage device for storing digital data of the contents, a reception/reception circuit for downloading playlists, a display for displaying the titles of contents included in the playlists, a pointing device for specifying displayed titles, a circuit for retrieving digital data from the storage device in the event that digital data of a content specified by the pointing device is stored within the storage device, and an output circuit for outputting the retrieved digital data.