Abstract: This envelope-detecting circuit comprises: a first multiplier able to multiply a first example of a signal received on an input port by itself, a modifier able to modify the amplitude of the power spectrum, of a second example of the signal received on the input port, at the frequency fc without modifying the amplitude of this power spectrum in a useful frequency band, a second multiplier able to multiply the modified signal by itself, a subtractor able to subtract from each other the signals delivered by the multipliers, a filter able to remove frequency components higher than or equal to 2fc in a signal obtained from the signal delivered by the subtractor, this filter being able to deliver the result of this filtering on an output connected to an output port of the envelope-detecting circuit.

Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.

Abstract: A circuit is configured to generate periodic control signals including at least two mutually phase-shifted control signals. The circuit includes a plurality of generator circuits, where a separate generator circuit is provided for each control signal output by the circuit. Each generator circuit includes a phase value memory configured to store a phase value, where the phase value defines a phase shift. Each generator circuit includes an activation input and, in response to application of an activation level to the activation input, is configured to initiate a generation of a control signal which is phase-shifted by an amount defined by the phase value. The activation inputs of the generator circuits are connected together to an activation circuit for outputting an activation level to the generator circuits simultaneously.

Abstract: A digital circuit portion comprises a flip-flop (20) having a clock input (22) and an output (data); a clock signal (ck); and a gate (24) between said clock signal (ck) and said clock input (22), said gate (24) being arranged selectively to couple the clock signal (ck) to the clock input (22) in dependence upon the output of the flip-flop (20).

Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.

Abstract: In an exemplary implementation, a detection circuit for regulating a power converter is configured to receive a combined sense signal comprising a first sense signal from the power converter superimposed with a second sense signal from the power converter. The detection circuit is further configured to generate a first detect signal from the combined sense signal and generate a second detect signal from the combined sense signal. The first detect signal can correspond to the first sense signal and the second detect signal can correspond to the second sense signal. The detection circuit can generate a filtered signal corresponding to the first sense signal from the combined sense signal to generate the first detect signal from the combined sense signal. Also, the detection circuit can generate an offset signal based on the combined sense signal to generate the second detect signal from the combined sense signal.

Abstract: One or more circuits may comprise at least one first-type analog-to-digital converter (ADC) and at least one second-type ADC. The circuit(s) may be operable to receive a plurality of signals, each of which may comprise a plurality of channels. The circuit(s) may be operable to digitize a selected one or more of the channels. Which, if any, of the selected channels are digitized via the at least one first-type ADC and which, if any, of the selected channels are digitized via the at least one second-type ADC, may be based on which of the plurality of channels are the selected channels and/or based on power consumption of the circuit(s). A bandwidth of each first-type ADC may be on the order of the bandwidth of one of the received signals. A bandwidth of each second-type ADC may be on the order of the bandwidth of one of the plurality of channels.

Abstract: A clock signal recovery device has a digital data signal input for the input of a digital data signal and a clock signal output for the output of a recovered clock signal. The digital data signal has a given nominal clock signal frequency. The clock signal recovery device is a digital circuit.

Abstract: Circuits and methods to provide a digital clock signal, which can be instantly halted without glitches and then resumes under control of an asynchronous suspend signal with whole width clock pulses has been achieved. The circuit suspends the clock output in either a high or a low state, instantaneously with the suspend signal. There is no restriction on either the suspend pulse width or position in relation to the input clock. The asynchronous logic implementation is using standard cell logic gates. The circuit functionality is not dependent on the manufacturing technology, i.e. CMOS, bipolar, BI-CMOS, GaAs, etc. implementations are all valid.

Abstract: Multiple characteristics of a DC-DC converter, such as its mode of operation (e.g., either forced continuous conduction mode, or discontinuous conduction mode), and an operational parameter (such as the dead-time between switching times of the output switching devices (upper and lower MOSFETs) of the converter, whose associated driver integrated circuit has a pin usage that leaves only a single pin available for auxiliary purposes, are programmed by a single pin-based digital and analog information extracting circuit that couples both digital information and analog information within the same control signal to the driver IC by way of only the one available pin.

Abstract: The present invention relates to a wire-bound transmission of data, as occurs, for example, between a sensor and a control unit. In order to save lines, both the supply voltage and the data signal to be transmitted are transmitted over the same line. The field of the present invention relates to the extraction of data signals from the supply voltage line.

Abstract: A method for generating a clock signal and a device having clock generating capabilities, the device includes: (i) a first divider, adapted to receive an input clock signal and divide the input clock signal to provide a first clock signal; (ii) a second divider, adapted to receive an input clock signal and divide the input clock signal to provide a second clock signal; wherein the first clock signal is phase shifted in relation to the second clock signal by half an input clock cycle; wherein a delay period of the first divider substantially equals a delay period of the second divider over a large range of delay affecting parameter values; (iii) a reconstruction circuit, connected to the first and second divider circuits, adapted to receive the first and second clock signals and apply a logical operation on the first and second clock signals to provide a reconstructed clock signal; and (iv) a selection circuit, connected to the first divider, second divider and reconstruction circuit, adapted to output an outp

Abstract: The invention relates to an electronic circuit making it possible to extract a clock signal from an incident binary data sequence arriving at a constant rate. The electronic circuit comprises an oscillator (VCO) with voltage-controlled frequency providing a sinusoidal signal, a circuit (R, Cp, RD, I1, I2) for extracting the transition edges of the binary sequence producing a brief pulse at each transition, a sampler (MLT) for tapping off the level of the sinusoidal voltage at the instant of the brief pulse, and an integrator (AOP, R1, C1) for integrating this level in tandem with the successive pulses, the output of the integrator being applied as control voltage to the oscillator with controlled frequency, the output of the oscillator being the desired clock frequency with a slaved phase passing through zero substantially in the middle of the interval between two binary data transitions.

Abstract: The detector is reduced in DC power consumption when an input signal is at a low amplitude level. The detector includes first and second input terminals, first and second transistors, and a load element. The first and second input terminals are supplied with complementary input signals reverse to each other in phase. The first input terminal is connected to the first input electrode of the first transistor and the second input electrode of the second transistor. The second input terminal is connected to the second input electrode of the first transistor and the first input electrode of the second transistor. The load element is connected between output electrodes of the transistors and an operating voltage point. A detection voltage resulting from full-wave rectification arises from a circuit node. In the condition where a signal input to the input terminals is at a low amplitude level, the transistors are both in OFF state. Thus, DC power consumption is reduced.

Abstract: A clock signal recovery device has a digital data signal input for the input of a digital data signal and a clock signal output for the output of a recovered clock signal. The digital data signal has a given nominal clock signal frequency. The clock signal recovery device is a digital circuit.

Abstract: A harmonic processor receiving an input signal and providing an output signal, the input signal comprising a first analog signal having amplitude, frequency and phase components and being converted to an instantaneous magnitude output signal, or the input signal comprising an instantaneous magnitude signal for inverse conversion to an output analog signal having amplitude, frequency and phase components, comprising a first component comprising a resistive plane, the first component having a first zone and a second zone, the first zone comprising a first set of first electrodes contacting the resistive plane at first defined locations and the second zone comprising a second set of electrodes contacting the resistive plane at second defined locations; the first electrodes comprising a first subset of first electrodes permanently connected to external terminals; and a second subset of first electrodes for connection to external terminals during controlled time periods; the second electrodes comprising a first su

Abstract: Methods and apparatus are provided for separating DC and AC components of a composite signal Is=Idc+Iac from a current source, e.g., a photodiode current source. Four current mirrors CM-1 . . . CM-4 are used with common branches and overlap. CM-1 through CM-3 mirror Is and CM-4 mirrors Idc where lac has been removed by a frequency selective branch. Outputs of the Cm-3 and Cm-4 are combined at a node to provide a signal proportional substantially only to Iac. Complementary devices are used where Cm-1 and Cm-4 are of one type and Cm-2 and Cm-3 are of opposite type. The arrangement allows detection of AC signals (e.g., pulses) that are orders of magnitude smaller than the DC background. An I-to-V converter with a large feedback resistance is used at the output to produce a comparatively large voltage output proportional to lac.

Abstract: A bus architecture for the application of data transmission between distinct integrated circuits. The bus architecture includes at least one transmission line connecting with I/O pin of ICs for transmitting data. In a middle point of the transmission line, there is a middle resistor with a resistance value preferably equal to the characteristic impedance of the transmission line. In addition, there are internal pull-up resistors within the ICs, which has a first end coupled to the I/O pin and a second end coupled to the voltage source. Each pull-up resistor has a resistance value higher than the characteristic impedance of the transmission line, for example, 2 or 3 times of the characteristic impedance, for suppressing the rising edge ringback.

Abstract: In a signal read circuit including a plurality of circuit rows each having a charge amplifier connected to a photoelectric conversion element PD and a CDS circuit 2S for performing correlated double sampling for an output from the charge amplifier, a dummy circuit row DMY having the same configuration as a circuit row SLT is connected in parallel with this circuit row SLT. By calculating the difference between these circuit rows connected in parallel, offset variations generated in the two circuit rows SLT and DMY can be removed.

Abstract: Phase-locked-loop based data and clock extraction comprising a phase detector that generates up and down pulses. Down pulses are maintained in width approximately equal to 1.5 unit intervals of a local sampling clock. Up pulses are allowed to vary with the phase relationship between the local sampling clock and an incoming encoded bit stream. The up pulses are allowed to vary between 1 and 2 unit intervals of the local sampling clock. The up and down pulses drive a charge pump D/A converter that generates a control voltage. The control voltage sets the frequency of the local sampling clock generated by a voltage controlled oscillator. Shift register controlled by a state machine and clocked by the local clock allows reception of complex data packets arriving by the encoded bit stream.

Abstract: A circuit (11) for tracking rapid changes in peak and trough voltages of a data signal includes a peak detector circuit (13) and a trough detector circuit (14) coupled to the input for detecting peaks and troughs in the data signal and providing a peak and trough detect output signals, respectively. A peak level rate of change detector (17) is coupled to the peak detector circuit (13) for detecting a rate of increase in the voltage level of detected peaks and to the trough detector circuit (14) for controlling the trough detector circuit to detect troughs when the voltage level of detected peaks rises rapidly. Similarly, a trough level rate of change detector (18) is coupled to the trough detector circuit (14) for detecting a rate of decrease in the voltage level of detected troughs and to the peak detector circuit (13) for controlling the peak detector circuit (13) to detect peaks when the voltage level of detected troughs falls rapidly.

Abstract: In a simultaneous bidirectional transmission circuit for conducting simultaneous two-way communication between LSIs via a transmission line, an input/output circuit connected to the transmission line is included in an LSI. The input/output circuit has a driver and a receiver. The driver sends out an output signal depending on a logical signal within the LSI to the transmission line. The receiver receives a mixed signal having a mixture of a received signal and the output signal via the transmission line. The signal to be received by the receiver in an LSI has been sent out to the transmission line by the other party i.e., another LSI in communication therewith. The receiver receives the logical signal output as well. The receives derives a difference between the mixed signal and the logical signal output, thereby removing the component of the logical signal from the mixed signal, and outputs the received signal.

Abstract: A data transfer circuit device including a data transfer circuit, a latch control circuit and a data latch circuit. The data transfer circuit outputs data therefrom in response to an externally supplied transfer signal. The latch control circuit generates a data latch signal, based on the transfer signal and a latch control signal. The data latch circuit latches the data supplied from the data transfer circuit, based on the data latch signal, and outputs the latched data as output data. When the data is being switched, the latch control circuit prevents the data latch signal from being supplied to the data latch circuit.

Abstract: An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a transmission source are prefixed with two data bits of known values. The data separator is also supplied with four clock signals per bit, one corresponding to an ideal rising edge and three following every 5 nanoseconds. The two prefix bits preceding a data packet are then sampled at each of the clock signals. Since all information in a given data packet undergoes the same systematic distortion, the logic of the adaptive data separator can determine the optimum clock signal to use in sampling each bit of data for the packet. Through several multiplexers the incoming data is then clocked to the optimal clock signal for sampling.

Abstract: The delay line separator extracts a clock signal from a combined data/clock encoded signal received over a serial data bus, despite the presence of significant duty cycle distortion. Such distortion affects the width of symbols within received data packets but does not affect the timing between successive rising edges within the received pulse string. To extract the clock signal from the distorted signal, the separator exploits a pre-filter circuit which generates 20-nanosecond pulses synchronized with each rising edge in the received signal. A 20-nanosecond pulse train is transmitted down a delay line having twelve delay elements. Circuits are connected to every other delay element within the delay line for generating 10-nanosecond pulses, synchronized with each rising edge of the pulse train. Outputs from the circuits are combined using an OR gate to yield a 10-nanosecond clock signal.

Abstract: Apparatus for extracting a target signal from a composite signal. The apparatus makes use of the composite signal to generate a DC power supply, whereupon no external power supply is needed for the apparatus to operate.

Abstract: A pulse-signal extracting method and apparatus which are capable of generating an accurate pulse output even if the pulse input signal greatly pulsates due to a low-frequency noise component. A predetermined offset voltage is added to the input signal where the low-frequency noise component is superimposed on a pulse waveform which is the signal component so as to obtain an amplified signal. This amplified signal is inputted to a low-pass filter so as to output only the amplified flow-frequency component, and the original input signal is compared with the amplified low-frequency component in a comparator so as to extract the pulse waveform, which is the signal component, on the basis of the comparison result.