Ground Plane Patents (Class 365/54)
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Patent number: 10469472Abstract: A computing device operating system providing a plurality of secure domains. A domain manager selectively creates a plurality of secure domains, and one of the secure domains is selected as a current domain. A domain policy service stores and enforces, for each secure domain, a policy comprising a rule set controlling access to files and applications associated with the domain. A package manager enforces, for each secure domain, installation of the applications associated with the domain. A domain message service provides communication between running processes associated with different ones of the secure domains. An activity manager selectively switches the current domain. Domain isolation is achieved while enabling a unified user interface providing concurrent access to the resources of multiple domains.Type: GrantFiled: August 11, 2014Date of Patent: November 5, 2019Inventors: Alexander James Main, James Henry Allan Puderer
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Patent number: 9042149Abstract: A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation.Type: GrantFiled: December 10, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Michael Ju Hyeok Lee, Bao G Truong
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Patent number: 8637170Abstract: A magnetic sensor comprises a support; a nonmagnetic conductive layer disposed on the support; a fixed magnetization layer disposed on a first part of the nonmagnetic conductive layer and on the support; a free magnetization layer disposed on a second part of the nonmagnetic conductive layer different from the first part and on the support; and a nonmagnetic low resistance layer, disposed on a part overlapping the nonmagnetic conductive layer in at least one of the fixed magnetization layer and free magnetization layer, having an electrical resistivity lower than that of the one layer.Type: GrantFiled: May 26, 2009Date of Patent: January 28, 2014Assignee: TDK CorporationInventor: Tomoyuki Sasaki
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Patent number: 8514603Abstract: A serial advanced technology attachment dual in-line memory module (SATA DIMM) includes a control chip having a first input output (I/O) pin and a second I/O pin, first and second switches, a resistor, and a number of storage chips connected to the control chip. First terminals of the first and second switches are respectively connected to the first and second I/O pins. Second terminals of the first and second switches are grounded. The first and second I/O pins receive different signals through controlling the first and second switches, to change work modes of the storage chips.Type: GrantFiled: December 10, 2011Date of Patent: August 20, 2013Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Xiao-Gang Yin, Guo-Yi Chen
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Patent number: 8351236Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.Type: GrantFiled: March 26, 2010Date of Patent: January 8, 2013Assignee: SanDisk 3D LLCInventors: Tianhong Yan, George Samachisa
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Patent number: 7795900Abstract: An integrated circuit has a memory array with a four-plex of SEU-hardened memory cells. Each of the SEU-hardened memory cells has an orientation different from each of the other SEU-hardened memory cells in the four-plex, and each of the SEU-hardened memory cells has a different critical ion track. Providing a four-plex of SEU-hardened memory cells, each with a different critical ion track, reduces the probability of a single ion upsetting adjacent memory cells.Type: GrantFiled: June 16, 2009Date of Patent: September 14, 2010Assignee: Xilinx, Inc.Inventors: Austin H. Lesea, Tan C. Hoang
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Patent number: 7633789Abstract: Embodiments of the invention relate generally to a planar third dimensional memory with multi-port access, the planar third dimensional memory including memory planes composed of a plurality of memory layers. The memory layers can include non-volatile memory elements. The planar third dimensional memory can also include insulation layers, each being formed to separate a memory layer from another memory layer, and a logic plane configured to control access to the plurality of memory planes. In some cases, the memory planes can be formed vertically above the logic plane. The logic plane can be formed in a substrate, such as a semiconductor wafer, for example. The planar third dimensional memory can include a multi-port interface that can be configured to provide access between a plurality of ports and the plurality of memory planes.Type: GrantFiled: December 4, 2007Date of Patent: December 15, 2009Inventor: Robert Norman
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Patent number: 7515452Abstract: A memory array has a first memory cell with a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value. A first portion of the plurality of transistors is in a first cell portion and a second portion of the plurality of transistors is in a second cell portion. A second memory cell has a third cell portion and a fourth cell portion. The third cell portion is between the first cell portion and the second cell portion and adjacent to each of the first cell portion and the second cell portion. In a particular embodiment, the memory cell is a single-event-upset (“SEU”) tolerant memory cell and the first and second cell portions are each a half cell of a sixteen transistor memory cell.Type: GrantFiled: January 3, 2007Date of Patent: April 7, 2009Assignee: XILINX, Inc.Inventors: Jan L. de Jong, Susan Xuan Nguyen, Raymond C. Pang
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Patent number: 7483286Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.Type: GrantFiled: July 27, 2006Date of Patent: January 27, 2009Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Salman Akram
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Patent number: 7391637Abstract: A memory device is provided with a structure for improved transmission line operation on integrated circuits. The structure for transmission line operation includes a first layer of electrically conductive material on a substrate. A first layer of insulating material is formed on the first layer of the electrically conductive material. A number of high permeability metal lines are formed on the first layer of insulating material. The number of high permeability metal lines includes composite hexaferrite films. A number of transmission lines is formed on the first layer of insulating material and between and parallel with the number of high permeability metal lines. A second layer of insulating material is formed on the transmission lines and the high permeability metal lines. The structure for transmission line operation includes a second layer of electrically conductive material on the second layer of insulating material.Type: GrantFiled: August 3, 2004Date of Patent: June 24, 2008Assignee: Micron Technology, Inc.Inventors: Leonard Forbes, Kie Y. Ahn, Salman Akram
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Patent number: 7184293Abstract: A crosspoint-type ferroelectric memory is provided. In the crosspoint-type ferroelectric memory, a first memory cell array and a second memory cell array are stacked with a first interlayer insulating layer and a second interlayer insulating layer therebetween. The first memory cell array includes lower electrodes formed in stripes, upper electrodes formed in stripes in a direction that crosses the lower electrodes, ferroelectric capacitors that are disposed at least at intersecting parts of the lower electrodes and the upper electrodes, and an embedded insulating layer formed between the ferroelectric capacitors. The interlayer insulating layer includes a conductive layer between a first insulating layer and a second insulating layer.Type: GrantFiled: October 27, 2004Date of Patent: February 27, 2007Assignee: Seiko Epson CorporationInventors: Kazumasa Hasegawa, Hiroyuki Aizawa
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Patent number: 6903423Abstract: An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.Type: GrantFiled: May 12, 2004Date of Patent: June 7, 2005Assignee: Infineon Technologies, AGInventors: Helmut Fischer, Jens Egerer
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Patent number: 6829179Abstract: A semiconductor storage device in the invention comprises a first control transistor which is connected between a bit line and a first node and whose control terminal is connected to a word line, a data retention circuit which includes a first transistor that is connected between the first node and a second reference voltage terminal, as well as a first inverter that includes a second transistor connected between a second node and the second reference voltage terminal, and a substrate potential control circuit which selectively alters a substrate potential of the first transistor so as to make a threshold voltage of the first transistor higher as compared with threshold voltages of the first control transistor and the second transistor. Thus, it is permitted to provide the semiconductor storage device of static type which realizes a reduced layout area and a lower-dissipation-power operation while ensuring the reliability and high operating speed of the write and read of data.Type: GrantFiled: December 27, 2002Date of Patent: December 7, 2004Assignee: Oki Electric Industry Co., Ltd.Inventor: Koichi Morikawa
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Patent number: 6812555Abstract: A memory card substrate includes a first solder pad assembly formed on a top edge of the memory card substrate. The first solder pad assembly has multiple first solder pads equally spaced from each other and multiple first gaps each sandwiched between two adjacent first solder pads. A second solder pad assembly is formed on a bottom edge of the memory card substrate and has multiple second solder pads equally spaced from each other and multiple second gaps each sandwiched between two adjacent second solder pads. Each first solder pad corresponds to one of the second gaps so that the first solder pads are alternately arranged on the top edge relative to the second solder pads on the bottom edge.Type: GrantFiled: March 10, 2003Date of Patent: November 2, 2004Assignee: Everstone Industry Corp.Inventor: Chien-Hung Chen
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Patent number: 6628528Abstract: A method including routing a signal from a memory device on an integrated circuit in a package to a memory module, and returning the signal to a reference line in the package between the memory module and the integrated circuit. Also, a method including providing a memory module including at least one memory package configured for electrically coupling to a bus on a system board, the at least one memory package comprising an integrated circuit including a plurality of memory devices, and a package substrate including a surface having a plurality of externally accessible contact points coupled to the memory devices and an externally accessible reference signal line and a surface of the package, and tuning the electrical characteristics of the memory package using an electrical potential between the contact points and the reference signal line.Type: GrantFiled: November 30, 2000Date of Patent: September 30, 2003Inventor: Theodore Zale Schoenborn
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Patent number: 6594172Abstract: The invention includes a method of fabricating a circuit in a manner to place certain structures within a predefined distance of one another. Electrical connections are formed between certain structures of silicon, by annealing a conductive material to cause silicon out-diffusing to form local interconnects. The silicon out-diffusion can be facilitated without a masking step thereby simplifying as well as speeding up the fabrication process. The invention also includes a local interconnect thus formed.Type: GrantFiled: November 19, 2001Date of Patent: July 15, 2003Assignee: Micron Technology, Inc.Inventors: Todd Abbott, Jigish D. Trivedi, Mike Violette, Chuck Dennison
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Patent number: 6421296Abstract: A double protection virtual ground memory circuit and column decoder. Through the introduction of a double protection circuit, leakage current from the virtual ground memory is reduced and power consumed by the memory circuit is lowered. Ultimately, sensing range of data within the memory by a sense amplifier is improved.Type: GrantFiled: May 4, 2001Date of Patent: July 16, 2002Assignee: Macronix International Co., Ltd.Inventors: Lai-Ching Lin, Yu-Wei Lee, Sheau-Yung Shyu
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Patent number: 6295220Abstract: A memory bar for use in high density memory modules. A memory bar comprises a substrate that provides a mounting for at least two IC chips, such that the substrate and associated IC chips may be mounted, for example, on one side of a memory module.Type: GrantFiled: November 3, 1998Date of Patent: September 25, 2001Assignee: Zomaya Group, Inc.Inventors: Rashwan B. Darwish, Trung Huynh
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Dual-bank memory module with shared capacitors and R-C elements integrated into the module substrate
Patent number: 5841686Abstract: A memory module has DRAM chips mounted on both a front and a back surface but decoupling capacitors mounted on only the front surface. Each decoupling capacitor is for suppressing current spikes from a pair of DRAM chips. The pair of DRAM chips includes a first DRAM chip on the same surface as the capacitor and a second DRAM chip opposite the first DRAM chip on the back surface of the module. The first DRAM chip belongs to a first bank while the second DRAM chip belongs to a second bank. Two RAS signals are for controlling access to the two banks. Since only one bank is accessed at any time, and access causes current spikes, only one bank and only one DRAM chip in the pair of DRAM chips creates a current spike at any time. Thus a capacitor can be shared between the two DRAM chips in the pair. The shared capacitor can be mounted next to or under one of the DRAM chips, or formed within the multi-layer substrate itself.Type: GrantFiled: November 22, 1996Date of Patent: November 24, 1998Assignee: MA Laboratories, Inc.Inventors: Tzu-Yih Chu, Abraham C. Ma -
Patent number: 5067000Abstract: A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. N-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions.Type: GrantFiled: August 9, 1989Date of Patent: November 19, 1991Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takahisa Eimori, Shinichi Satoh, Wataru Wakamiya, Hiroji Ozaki, Yoshinori Tanaka
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Patent number: 4175288Abstract: In a magnetic bubble memory device, positive signal lines interconnecting a magnetic bubble memory chip located at substantially the center of an insulating substrate and lead pins at the end of the substrate are surrounded by a plurality of grounded conductors for shielding the positive signal lines so as to decrease noise induced therein by a voltage drop across coils for producing the rotating magnetic field.Type: GrantFiled: February 23, 1978Date of Patent: November 20, 1979Assignee: Hitachi, Ltd.Inventors: Hirofumi Ohta, Toshio Futami, Kazuo Umeyama